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GET /api/patches/388383/?format=api
{ "id": 388383, "url": "http://patchwork.ozlabs.org/api/patches/388383/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1410467527-19623-2-git-send-email-yorksun@freescale.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1410467527-19623-2-git-send-email-yorksun@freescale.com>", "list_archive_url": null, "date": "2014-09-11T20:32:07", "name": "[U-Boot,2/2] board/ls1021aqds_d4: Add DDR4 support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "7dc173f5ac971db69d1b9c36ef93bd2c7de66d94", "submitter": { "id": 3777, "url": "http://patchwork.ozlabs.org/api/people/3777/?format=api", "name": "York Sun", "email": "yorksun@freescale.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1410467527-19623-2-git-send-email-yorksun@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/388383/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/388383/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id B0B86140131\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 12 Sep 2014 06:49:34 +1000 (EST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 0F31AA760A;\n\tThu, 11 Sep 2014 22:49:33 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id s+eWh19kwuNo; Thu, 11 Sep 2014 22:49:32 +0200 (CEST)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 00BB5A7601;\n\tThu, 11 Sep 2014 22:49:22 +0200 (CEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 154A6A7600\n\tfor <u-boot@lists.denx.de>; Thu, 11 Sep 2014 22:49:16 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id MmMAX3f12LnM for <u-boot@lists.denx.de>;\n\tThu, 11 Sep 2014 22:49:06 +0200 (CEST)", "from na01-bn1-obe.outbound.protection.outlook.com\n\t(mail-bn1bon0134.outbound.protection.outlook.com [157.56.111.134])\n\tby theia.denx.de (Postfix) with ESMTPS id 91915A7608\n\tfor <u-boot@lists.denx.de>; Thu, 11 Sep 2014 22:48:51 +0200 (CEST)", "from BN3PR0301CA0053.namprd03.prod.outlook.com (25.160.152.149) by\n\tBY2PR03MB159.namprd03.prod.outlook.com (10.242.36.18) with\n\tMicrosoft\n\tSMTP Server (TLS) id 15.0.1029.13; Thu, 11 Sep 2014 20:32:36 +0000", "from BY2FFO11FD001.protection.gbl (2a01:111:f400:7c0c::123) by\n\tBN3PR0301CA0053.outlook.office365.com (2a01:111:e400:401e::21) with\n\tMicrosoft SMTP Server (TLS) id 15.0.1024.12 via Frontend Transport;\n\tThu, 11 Sep 2014 20:32:35 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBY2FFO11FD001.mail.protection.outlook.com (10.1.14.123) with\n\tMicrosoft SMTP\n\tServer (TLS) id 15.0.1019.14 via Frontend Transport; Thu, 11 Sep 2014\n\t20:32:35 +0000", "from oslab-l1.am.freescale.net ([10.214.85.24])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\ts8BKWPvC004191; Thu, 11 Sep 2014 13:32:33 -0700" ], "X-Virus-Scanned": [ "Debian amavisd-new at theia.denx.de", "Debian amavisd-new at theia.denx.de" ], "X-Greylist": "delayed 966 seconds by postgrey-1.27 at theia;\n\tThu, 11 Sep 2014 22:48:51 CEST", "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "York Sun <yorksun@freescale.com>", "To": "<u-boot@lists.denx.de>", "Date": "Thu, 11 Sep 2014 13:32:07 -0700", "Message-ID": "<1410467527-19623-2-git-send-email-yorksun@freescale.com>", "X-Mailer": "git-send-email 1.7.9.5", "In-Reply-To": "<1410467527-19623-1-git-send-email-yorksun@freescale.com>", "References": "<1410467527-19623-1-git-send-email-yorksun@freescale.com>", "X-EOPAttributedMessage": "0", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI;\n\tEFV:NLI; SFV:NSPM;\n\tSFS:(10019020)(6009001)(189002)(199003)(50226001)(84676001)(106466001)(19580395003)(81342001)(6806004)(87286001)(4396001)(95666004)(21056001)(88136002)(87936001)(81542001)(76482001)(105606002)(229853001)(2351001)(107046002)(97736003)(46102001)(85306004)(74502001)(74662001)(83072002)(80022001)(62966002)(92726001)(68736004)(85852003)(92566001)(104166001)(20776003)(77156001)(31966008)(47776003)(50986999)(64706001)(575784001)(93916002)(79102001)(76176999)(26826002)(86362001)(110136001)(99396002)(19580405001)(83322001)(90102001)(44976005)(50466002)(102836001)(89996001)(33646002)(36756003)(77982001)(48376002)(104016003);\n\tDIR:OUT; SFP:1102; SCL:1; SRVR:BY2PR03MB159;\n\tH:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm;\n\tPTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; ", "MIME-Version": "1.0", "X-Microsoft-Antispam": "BCL:0;PCL:0;RULEID:;UriScan:;", "X-Forefront-PRVS": "03319F6FEF", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=yorksun@freescale.com; ", "X-OriginatorOrg": "freescale.com", "Cc": "York Sun <yorksun@freescale.com>", "Subject": "[U-Boot] [PATCH 2/2] board/ls1021aqds_d4: Add DDR4 support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.11", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "LS1021AQDS has a variant with DDR4 slot. This patch adds a new target for\nthis variant and enables DDR4 support. RAW timing parameters are not added\nfor DDR4. The board timing parameters are only tuned for single-rank 1600\nand 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to availability.\n\nSigned-off-by: York Sun <yorksun@freescale.com>\n---\n arch/arm/Kconfig | 3 +++\n arch/arm/include/asm/arch-ls102xa/config.h | 5 +++++\n board/freescale/ls1021aqds/Kconfig | 2 +-\n board/freescale/ls1021aqds/ddr.c | 9 ++++++++-\n board/freescale/ls1021aqds/ddr.h | 10 ++++++++++\n ...s_nor_defconfig => ls1021aqds_d4_nor_defconfig} | 1 +\n include/configs/ls1021aqds.h | 4 +++-\n 7 files changed, 31 insertions(+), 3 deletions(-)\n copy configs/{ls1021aqds_nor_defconfig => ls1021aqds_d4_nor_defconfig} (50%)", "diff": "diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\nindex 11143a8..49c4b5a 100644\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -473,6 +473,9 @@ config TARGET_LS2085A_SIMU\n config TARGET_LS1021AQDS\n \tbool \"Support ls1021aqds_nor\"\n \n+config TARGET_LS1021AQDS_D4\n+\tbool \"Support ls1021aqds_nor with DDR4\"\n+\n config TARGET_LS1021ATWR\n \tbool \"Support ls1021atwr_nor\"\n \ndiff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h\nindex ed78c33..a500b5b 100644\n--- a/arch/arm/include/asm/arch-ls102xa/config.h\n+++ b/arch/arm/include/asm/arch-ls102xa/config.h\n@@ -50,7 +50,11 @@\n #ifdef CONFIG_DDR_SPD\n #define CONFIG_SYS_FSL_DDR_BE\n #define CONFIG_VERY_BIG_RAM\n+#ifdef CONFIG_SYS_FSL_DDR4\n+#define CONFIG_SYS_FSL_DDRC_GEN4\n+#else\n #define CONFIG_SYS_FSL_DDRC_ARM_GEN3\n+#endif\n #define CONFIG_SYS_FSL_DDR\n #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE\t\t((phys_size_t)2 << 30)\n #define CONFIG_MAX_MEM_MAPPED\t\t\tCONFIG_SYS_LS1_DDR_BLOCK1_SIZE\n@@ -71,6 +75,7 @@\n #define CONFIG_MAX_CPUS\t\t\t\t2\n #define CONFIG_SYS_FSL_IFC_BANK_COUNT\t\t8\n #define CONFIG_NUM_DDR_CONTROLLERS\t\t1\n+#define CONFIG_SYS_FSL_DDR_VER\t\t\tFSL_DDR_VER_5_0\n #else\n #error SoC not defined\n #endif\ndiff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig\nindex c28bd2b..1f60d95 100644\n--- a/board/freescale/ls1021aqds/Kconfig\n+++ b/board/freescale/ls1021aqds/Kconfig\n@@ -1,4 +1,4 @@\n-if TARGET_LS1021AQDS\n+if TARGET_LS1021AQDS || TARGET_LS1021AQDS_D4\n \n config SYS_CPU\n \tstring\ndiff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c\nindex 679c654..5898e33 100644\n--- a/board/freescale/ls1021aqds/ddr.c\n+++ b/board/freescale/ls1021aqds/ddr.c\n@@ -79,7 +79,6 @@ found:\n \t */\n \tpopts->wrlvl_override = 1;\n \tpopts->wrlvl_sample = 0xf;\n-\tpopts->cswl_override = DDR_CSWL_CS0;\n \n \t/*\n \t * Rtt and Rtt_WR override\n@@ -89,9 +88,17 @@ found:\n \t/* Enable ZQ calibration */\n \tpopts->zq_en = 1;\n \n+#ifdef CONFIG_SYS_FSL_DDR4\n+\tpopts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);\n+\tpopts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |\n+\t\t\t DDR_CDR2_VREF_OVRD(70);\t/* Vref = 70% */\n+#else\n+\tpopts->cswl_override = DDR_CSWL_CS0;\n+\n \t/* DHC_EN =1, ODT = 75 Ohm */\n \tpopts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);\n \tpopts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);\n+#endif\n }\n \n #ifdef CONFIG_SYS_DDR_RAW_TIMING\ndiff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h\nindex 16d87cb..f819c99 100644\n--- a/board/freescale/ls1021aqds/ddr.h\n+++ b/board/freescale/ls1021aqds/ddr.h\n@@ -30,6 +30,13 @@ static const struct board_specific_parameters udimm0[] = {\n \t * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T\n \t * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |\n \t */\n+#ifdef CONFIG_SYS_FSL_DDR4\n+\t{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},\n+\t{2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},\n+\t{1, 1666, 0, 4, 8, 0x090A0B0B, 0x0C0D0E0C,},\n+\t{1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,},\n+\t{1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,},\n+#elif defined(CONFIG_SYS_FSL_DDR3)\n \t{1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},\n \t{1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},\n \t{1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},\n@@ -39,6 +46,9 @@ static const struct board_specific_parameters udimm0[] = {\n \t{2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},\n \t{2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},\n \t{2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},\n+#else\n+#error DDR type not defined\n+#endif\n \t{}\n };\n \ndiff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_d4_nor_defconfig\nsimilarity index 50%\ncopy from configs/ls1021aqds_nor_defconfig\ncopy to configs/ls1021aqds_d4_nor_defconfig\nindex 9e42d61..3c57481 100644\n--- a/configs/ls1021aqds_nor_defconfig\n+++ b/configs/ls1021aqds_d4_nor_defconfig\n@@ -1,2 +1,3 @@\n+CONFIG_SYS_EXTRA_OPTIONS=\"SYS_FSL_DDR4\"\n CONFIG_ARM=y\n CONFIG_TARGET_LS1021AQDS=y\ndiff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h\nindex 657e3b6..bb47813 100644\n--- a/include/configs/ls1021aqds.h\n+++ b/include/configs/ls1021aqds.h\n@@ -49,10 +49,12 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_DDR_SPD\n #define SPD_EEPROM_ADDRESS\t\t0x51\n #define CONFIG_SYS_SPD_BUS_NUM\t\t0\n-#define CONFIG_SYS_DDR_RAW_TIMING\n \n #define CONFIG_FSL_DDR_INTERACTIVE\t/* Interactive debugging */\n+#ifndef CONFIG_SYS_FSL_DDR4\n #define CONFIG_SYS_FSL_DDR3\t\t/* Use DDR3 memory */\n+#define CONFIG_SYS_DDR_RAW_TIMING\n+#endif\n #define CONFIG_DIMM_SLOTS_PER_CTLR\t1\n #define CONFIG_CHIP_SELECTS_PER_CTRL\t4\n \n", "prefixes": [ "U-Boot", "2/2" ] }