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{ "id": 379857, "url": "http://patchwork.ozlabs.org/api/patches/379857/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1407998707-9632-12-git-send-email-b18965@freescale.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1407998707-9632-12-git-send-email-b18965@freescale.com>", "list_archive_url": null, "date": "2014-08-14T06:45:00", "name": "[U-Boot,v4,11/18] arm: ls102xa: Add basic support for LS1021AQDS board", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "cfb796497d8fc92d02487c3087affb27172aab5a", "submitter": { "id": 13010, "url": "http://patchwork.ozlabs.org/api/people/13010/?format=api", "name": "Alison Wang", "email": "b18965@freescale.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1407998707-9632-12-git-send-email-b18965@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/379857/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/379857/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 50F0914009B\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 14 Aug 2014 17:37:25 +1000 (EST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 8F9CDA73F8;\n\tThu, 14 Aug 2014 09:37:14 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id AL-iNTd73CJG; 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Thu, 14 Aug 2014 00:34:44 -0700" ], "X-Virus-Scanned": [ "Debian amavisd-new at theia.denx.de", "Debian amavisd-new at theia.denx.de" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Alison Wang <b18965@freescale.com>", "To": "<yorksun@freescale.com>, <u-boot@lists.denx.de>", "Date": "Thu, 14 Aug 2014 14:45:00 +0800", "Message-ID": "<1407998707-9632-12-git-send-email-b18965@freescale.com>", "X-Mailer": "git-send-email 1.8.0", "In-Reply-To": "<1407998707-9632-1-git-send-email-b18965@freescale.com>", "References": "<1407998707-9632-1-git-send-email-b18965@freescale.com>", "X-EOPAttributedMessage": "0", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI;\n\tEFV:NLI; SFV:NSPM; \n\tSFS:(6009001)(199003)(54534003)(189002)(47776003)(97736001)(50226001)(77982001)(229853001)(95666004)(4396001)(575784001)(107046002)(21056001)(36756003)(105606002)(50466002)(104166001)(83072002)(106466001)(89996001)(26826002)(85852003)(104016003)(44976005)(99396002)(79102001)(76482001)(88136002)(92566001)(92726001)(87936001)(87286001)(80022001)(81342001)(85306004)(68736004)(19580395003)(74662001)(19580405001)(64706001)(77156001)(93916002)(6806004)(20776003)(76176999)(102836001)(33646002)(46102001)(62966002)(83322001)(31966008)(48376002)(81542001)(84676001)(74502001)(50986999)(42262002);\n\tDIR:OUT; SFP:; SCL:1; SRVR:BL2PR03MB372;\n\tH:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm;\n\tPTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; ", "MIME-Version": "1.0", "X-Microsoft-Antispam": "BCL:0;PCL:0;RULEID:;UriScan:;", "X-Forefront-PRVS": "03030B9493", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=alison.wang@freescale.com; ", "X-OriginatorOrg": "freescale.com", "Subject": "[U-Boot] [PATCH v4 11/18] arm: ls102xa: Add basic support for\n\tLS1021AQDS board", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.11", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "From: Wang Huan <b18965@freescale.com>\n\nLS102xA is an ARMv7 implementation. This patch is to add\nbasic support for LS1021AQDS board.\n One DDR controller\n DUART1 is used as the console\n\nFor the detail board information, please refer to README.\n\nSigned-off-by: Alison Wang <alison.wang@freescale.com>\nSigned-off-by: Jason Jin <jason.jin@freescale.com>\nSigned-off-by: York Sun <yorksun@freescale.com>\nSigned-off-by: Yuan Yao <yao.yuan@freescale.com>\nSigned-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>\n---\nChange log:\n v4: Add more commit messages.\n v3: Fix checkpatch error.\n Update to Kconfig. \n v2: Remove ethaddr/ipaddr setting.\n Add board maintainer.\n Add serdes and multiple ethernet controllers support.\n\n arch/arm/Kconfig | 4 +\n board/freescale/ls1021aqds/Kconfig | 23 ++\n board/freescale/ls1021aqds/MAINTAINERS | 6 +\n board/freescale/ls1021aqds/Makefile | 9 +\n board/freescale/ls1021aqds/README | 112 +++++++\n board/freescale/ls1021aqds/ddr.c | 166 ++++++++++\n board/freescale/ls1021aqds/ddr.h | 64 ++++\n board/freescale/ls1021aqds/eth.c | 129 ++++++++\n board/freescale/ls1021aqds/ls1021aqds.c | 248 +++++++++++++++\n board/freescale/ls1021aqds/ls1021aqds_qixis.h | 35 +++\n configs/ls1021aqds_nor_defconfig | 2 +\n include/configs/ls1021aqds.h | 424 ++++++++++++++++++++++++++\n 12 files changed, 1222 insertions(+)\n create mode 100644 board/freescale/ls1021aqds/Kconfig\n create mode 100644 board/freescale/ls1021aqds/MAINTAINERS\n create mode 100644 board/freescale/ls1021aqds/Makefile\n create mode 100644 board/freescale/ls1021aqds/README\n create mode 100644 board/freescale/ls1021aqds/ddr.c\n create mode 100644 board/freescale/ls1021aqds/ddr.h\n create mode 100644 board/freescale/ls1021aqds/eth.c\n create mode 100644 board/freescale/ls1021aqds/ls1021aqds.c\n create mode 100644 board/freescale/ls1021aqds/ls1021aqds_qixis.h\n create mode 100644 configs/ls1021aqds_nor_defconfig\n create mode 100644 include/configs/ls1021aqds.h", "diff": "diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\nindex e385eda..62b3cc8 100644\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -731,6 +731,9 @@ config TARGET_LS2085A_EMU\n config TARGET_LS2085A_SIMU\n \tbool \"Support ls2085a_simu\"\n \n+config TARGET_LS1021AQDS\n+\tbool \"Support ls1021aqds_nor\"\n+\n config TARGET_BALLOON3\n \tbool \"Support balloon3\"\n \n@@ -865,6 +868,7 @@ source \"board/eukrea/cpu9260/Kconfig\"\n source \"board/eukrea/cpuat91/Kconfig\"\n source \"board/faraday/a320evb/Kconfig\"\n source \"board/freescale/ls2085a/Kconfig\"\n+source \"board/freescale/ls1021aqds/Kconfig\"\n source \"board/freescale/mx23evk/Kconfig\"\n source \"board/freescale/mx25pdk/Kconfig\"\n source \"board/freescale/mx28evk/Kconfig\"\ndiff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig\nnew file mode 100644\nindex 0000000..c28bd2b\n--- /dev/null\n+++ b/board/freescale/ls1021aqds/Kconfig\n@@ -0,0 +1,23 @@\n+if TARGET_LS1021AQDS\n+\n+config SYS_CPU\n+\tstring\n+\tdefault \"armv7\"\n+\n+config SYS_BOARD\n+\tstring\n+\tdefault \"ls1021aqds\"\n+\n+config SYS_VENDOR\n+\tstring\n+\tdefault \"freescale\"\n+\n+config SYS_SOC\n+\tstring\n+\tdefault \"ls102xa\"\n+\n+config SYS_CONFIG_NAME\n+\tstring\n+\tdefault \"ls1021aqds\"\n+\n+endif\ndiff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS\nnew file mode 100644\nindex 0000000..021d82b\n--- /dev/null\n+++ b/board/freescale/ls1021aqds/MAINTAINERS\n@@ -0,0 +1,6 @@\n+LS1021AQDS BOARD\n+M:\tAlison Wang <alison.wang@freescale.com>\n+S:\tMaintained\n+F:\tboard/freescale/ls1021aqds/\n+F:\tinclude/configs/ls1021aqds.h\n+F:\tconfigs/ls1021aqds_nor_defconfig\ndiff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile\nnew file mode 100644\nindex 0000000..3b6903c\n--- /dev/null\n+++ b/board/freescale/ls1021aqds/Makefile\n@@ -0,0 +1,9 @@\n+#\n+# Copyright 2014 Freescale Semiconductor, Inc.\n+#\n+# SPDX-License-Identifier: GPL-2.0+\n+#\n+\n+obj-y += ls1021aqds.o\n+obj-y += ddr.o\n+obj-y += eth.o\ndiff --git a/board/freescale/ls1021aqds/README b/board/freescale/ls1021aqds/README\nnew file mode 100644\nindex 0000000..c561776\n--- /dev/null\n+++ b/board/freescale/ls1021aqds/README\n@@ -0,0 +1,112 @@\n+Overview\n+--------\n+The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC.\n+\n+LS1021A SoC Overview\n+------------------\n+The QorIQ LS1 family, which includes the LS1021A communications processor,\n+is built on Layerscape architecture, the industry's first software-aware,\n+core-agnostic networking architecture to offer unprecedented efficiency\n+and scale.\n+\n+A member of the value-performance tier, the QorIQ LS1021A processor provides\n+extensive integration and power efficiency for fanless, small form factor\n+enterprise networking applications. Incorporating dual ARM Cortex-A7 cores\n+running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark\n+performance of over 6,000, as well as virtualization support, advanced\n+security features and the broadest array of high-speed interconnects and\n+optimized peripheral features ever offered in a sub-3 W processor.\n+\n+The QorIQ LS1021A processor features an integrated LCD controller,\n+CAN controller for implementing industrial protocols, DDR3L/4 running\n+up to 1600 MHz, integrated security engine and QUICC Engine, and ECC\n+protection on both L1 and L2 caches. The LS1021A processor is pin- and\n+software-compatible with the QorIQ LS1020A and LS1022A processors.\n+\n+The LS1021A SoC includes the following function and features:\n+\n+ - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture\n+ - Dual high-preformance ARM Cortex-A7 cores, each core includes:\n+ - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection)\n+ - 512 Kbyte shared coherent L2 Cache (with ECC protection)\n+ - NEON Co-processor (per core)\n+ - 40-bit physical addressing\n+ - Vector floating-point support\n+ - ARM Core-Link CCI-400 Cache Coherent Interconnect\n+ - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration\n+ supporting speeds up to 1600Mtps\n+ - ECC and interleaving support\n+ - VeTSEC Ethernet complex\n+ - Up to 3x virtualized 10/100/1000 Ethernet controllers\n+ - MII, RMII, RGMII, and SGMII support\n+ - QoS, lossless flow control, and IEEE 1588 support\n+ - 4-lane 6GHz SerDes\n+ - High speed interconnect (4 SerDes lanes with are muxed for these protocol)\n+ - Two PCI Express Gen2 controllers running at up to 5 GHz\n+ - One Serial ATA 3.0 supporting 6 GT/s operation\n+ - Two SGMII interfaces supporting 1000 Mbps\n+ - Additional peripheral interfaces\n+ - One high-speed USB 3.0 controller with integrated PHY and one high-speed\n+ USB 2.00 controller with ULPI\n+ - Integrated flash controller (IFC) with 16-bit interface\n+ - Quad SPI NOR Flash\n+ - One enhanced Secure digital host controller\n+ - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface)\n+ - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power\n+ UARTs\n+ - Three I2C controllers\n+ - Eight FlexTimers four supporting PWM and four FlexCAN ports\n+ - Four GPIO controllers supporting up to 109 general purpose I/O signals\n+ - Integrated advanced audio block:\n+ - Four synchronous audio interfaces (SAI)\n+ - Sony/Philips Digital Interconnect Format (SPDIF)\n+ - Asynchronous Sample Rate Converter (ASRC)\n+ - Hardware based crypto offload engine\n+ - IPSec forwarding at up to 1Gbps\n+ - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported\n+ - Public key hardware accelerator\n+ - True Random Number Generator (NIST Certified)\n+ - Advanced Encryption Standard Accelerators (AESA)\n+ - Data Encryption Standard Accelerators\n+ - QUICC Engine ULite block\n+ - Two universal communication controllers (TDM and HDLC) supporting 64\n+ multichannels, each running at 64 Kbps\n+ - Support for 256 channels of HDLC\n+ - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported\n+\n+LS1021AQDS board Overview\n+-------------------------\n+ - DDR Controller\n+ - Supports rates of up to 1600 MHz data-rate\n+ - Supports one DDR3LP UDIMM, of single-, dual- types.\n+ - IFC/Local Bus\n+ - NAND flash: 512M 8-bit NAND flash\n+ - NOR: 128MB 16-bit NOR Flash\n+ - Ethernet\n+ - Three on-board RGMII 10/100/1G ethernet ports.\n+ - FPGA\n+ - Clocks\n+ - System and DDR clock (SYSCLK, DDRCLK)\n+ - SERDES clocks\n+ - Power Supplies\n+ - SDHC\n+ - SDHC/SDXC connector\n+ - Other IO\n+ - Two Serial ports\n+ - Three I2C ports\n+\n+Memory map\n+-----------\n+The addresses in brackets are physical addresses.\n+\n+Start Address\tEnd Address\tDescription\t\t\tSize\n+0x00_0000_0000\t0x00_000F_FFFF\tSecure Boot ROM\t\t\t1MB\n+0x00_0100_0000\t0x00_0FFF_FFFF\tCCSRBAR\t\t\t\t240MB\n+0x00_1000_0000\t0x00_1000_FFFF\tOCRAM0\t\t\t\t64KB\n+0x00_1001_0000\t0x00_1001_FFFF\tOCRAM1\t\t\t\t64KB\n+0x00_2000_0000\t0x00_20FF_FFFF\tDCSR\t\t\t\t16MB\n+0x00_4000_0000\t0x00_5FFF_FFFF\tQSPI\t\t\t\t512MB\n+0x00_6000_0000\t0x00_67FF_FFFF\tIFC - NOR Flash\t\t\t128MB\n+0x00_7E80_0000\t0x00_7E80_FFFF\tIFC - NAND Flash\t\t64KB\n+0x00_7FB0_0000\t0x00_7FB0_0FFF\tIFC - FPGA\t\t\t4KB\n+0x00_8000_0000\t0x00_FFFF_FFFF\tDRAM1\t\t\t\t2GB\ndiff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c\nnew file mode 100644\nindex 0000000..f07f15c\n--- /dev/null\n+++ b/board/freescale/ls1021aqds/ddr.c\n@@ -0,0 +1,166 @@\n+/*\n+ * Copyright 2014 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <fsl_ddr_sdram.h>\n+#include <fsl_ddr_dimm_params.h>\n+#include \"ddr.h\"\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+void fsl_ddr_board_options(memctl_options_t *popts,\n+\t\t\t dimm_params_t *pdimm,\n+\t\t\t unsigned int ctrl_num)\n+{\n+\tconst struct board_specific_parameters *pbsp, *pbsp_highest = NULL;\n+\tulong ddr_freq;\n+\n+\tif (ctrl_num > 3) {\n+\t\tprintf(\"Not supported controller number %d\\n\", ctrl_num);\n+\t\treturn;\n+\t}\n+\tif (!pdimm->n_ranks)\n+\t\treturn;\n+\n+\t/*\n+\t * we use identical timing for all slots. If needed, change the code\n+\t * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];\n+\t */\n+\tif (popts->registered_dimm_en)\n+\t\tpbsp = rdimms[0];\n+\telse\n+\t\tpbsp = udimms[0];\n+\n+\t/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr\n+\t * freqency and n_banks specified in board_specific_parameters table.\n+\t */\n+\tddr_freq = get_ddr_freq(0) / 1000000;\n+\twhile (pbsp->datarate_mhz_high) {\n+\t\tif (pbsp->n_ranks == pdimm->n_ranks) {\n+\t\t\tif (ddr_freq <= pbsp->datarate_mhz_high) {\n+\t\t\t\tpopts->clk_adjust = pbsp->clk_adjust;\n+\t\t\t\tpopts->wrlvl_start = pbsp->wrlvl_start;\n+\t\t\t\tpopts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;\n+\t\t\t\tpopts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;\n+\t\t\t\tpopts->cpo_override = pbsp->cpo_override;\n+\t\t\t\tpopts->write_data_delay =\n+\t\t\t\t\tpbsp->write_data_delay;\n+\t\t\t\tgoto found;\n+\t\t\t}\n+\t\t\tpbsp_highest = pbsp;\n+\t\t}\n+\t\tpbsp++;\n+\t}\n+\n+\tif (pbsp_highest) {\n+\t\tprintf(\"Error: board specific timing not found for %lu MT/s\\n\",\n+\t\t ddr_freq);\n+\t\tprintf(\"Trying to use the highest speed (%u) parameters\\n\",\n+\t\t pbsp_highest->datarate_mhz_high);\n+\t\tpopts->clk_adjust = pbsp_highest->clk_adjust;\n+\t\tpopts->wrlvl_start = pbsp_highest->wrlvl_start;\n+\t\tpopts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;\n+\t\tpopts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;\n+\t} else {\n+\t\tpanic(\"DIMM is not supported by this board\");\n+\t}\n+found:\n+\tdebug(\"Found timing match: n_ranks %d, data rate %d, rank_gb %d\\n\",\n+\t pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);\n+\n+\t/* force DDR bus width to 32 bits */\n+\tpopts->data_bus_width = 1;\n+\tpopts->otf_burst_chop_en = 0;\n+\tpopts->burst_length = DDR_BL8;\n+\n+\t/*\n+\t * Factors to consider for half-strength driver enable:\n+\t *\t- number of DIMMs installed\n+\t */\n+\tpopts->half_strength_driver_enable = 1;\n+\t/*\n+\t * Write leveling override\n+\t */\n+\tpopts->wrlvl_override = 1;\n+\tpopts->wrlvl_sample = 0xf;\n+\tpopts->cswl_override = DDR_CSWL_CS0;\n+\n+\t/*\n+\t * Rtt and Rtt_WR override\n+\t */\n+\tpopts->rtt_override = 0;\n+\n+\t/* Enable ZQ calibration */\n+\tpopts->zq_en = 1;\n+\n+\t/* DHC_EN =1, ODT = 75 Ohm */\n+\tpopts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);\n+\tpopts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);\n+}\n+\n+#ifdef CONFIG_SYS_DDR_RAW_TIMING\n+dimm_params_t ddr_raw_timing = {\n+\t.n_ranks = 1,\n+\t.rank_density = 1073741824u,\n+\t.capacity = 1073741824u,\n+\t.primary_sdram_width = 32,\n+\t.ec_sdram_width = 0,\n+\t.registered_dimm = 0,\n+\t.mirrored_dimm = 0,\n+\t.n_row_addr = 15,\n+\t.n_col_addr = 10,\n+\t.n_banks_per_sdram_device = 8,\n+\t.edc_config = 0,\n+\t.burst_lengths_bitmask = 0x0c,\n+\n+\t.tckmin_x_ps = 1071,\n+\t.caslat_x = 0xfe << 4,\t/* 5,6,7,8 */\n+\t.taa_ps = 13125,\n+\t.twr_ps = 15000,\n+\t.trcd_ps = 13125,\n+\t.trrd_ps = 7500,\n+\t.trp_ps = 13125,\n+\t.tras_ps = 37500,\n+\t.trc_ps = 50625,\n+\t.trfc_ps = 160000,\n+\t.twtr_ps = 7500,\n+\t.trtp_ps = 7500,\n+\t.refresh_rate_ps = 7800000,\n+\t.tfaw_ps = 37500,\n+};\n+\n+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,\n+\t\t\t unsigned int controller_number,\n+\t\t\t unsigned int dimm_number)\n+{\n+\tstatic const char dimm_model[] = \"Fixed DDR on board\";\n+\n+\tif (((controller_number == 0) && (dimm_number == 0)) ||\n+\t ((controller_number == 1) && (dimm_number == 0))) {\n+\t\tmemcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));\n+\t\tmemset(pdimm->mpart, 0, sizeof(pdimm->mpart));\n+\t\tmemcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);\n+\t}\n+\n+\treturn 0;\n+}\n+#endif\n+\n+phys_size_t initdram(int board_type)\n+{\n+\tphys_size_t dram_size;\n+\n+\tputs(\"Initializing DDR....using SPD\\n\");\n+\tdram_size = fsl_ddr_sdram();\n+\n+\treturn dram_size;\n+}\n+\n+void dram_init_banksize(void)\n+{\n+\tgd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;\n+\tgd->bd->bi_dram[0].size = gd->ram_size;\n+}\ndiff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h\nnew file mode 100644\nindex 0000000..814d210\n--- /dev/null\n+++ b/board/freescale/ls1021aqds/ddr.h\n@@ -0,0 +1,64 @@\n+/*\n+ * Copyright 2014 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __DDR_H__\n+#define __DDR_H__\n+struct board_specific_parameters {\n+\tu32 n_ranks;\n+\tu32 datarate_mhz_high;\n+\tu32 rank_gb;\n+\tu32 clk_adjust;\n+\tu32 wrlvl_start;\n+\tu32 wrlvl_ctl_2;\n+\tu32 wrlvl_ctl_3;\n+\tu32 cpo_override;\n+\tu32 write_data_delay;\n+\tu32 force_2t;\n+};\n+\n+/*\n+ * These tables contain all valid speeds we want to override with board\n+ * specific parameters. datarate_mhz_high values need to be in ascending order\n+ * for each n_ranks group.\n+ */\n+static const struct board_specific_parameters rdimm0[] = {\n+\t/*\n+\t * memory controller 0\n+\t * num| hi| rank| clk| wrlvl | wrlvl | wrlvl\n+\t * ranks| mhz| GB |adjst| start | ctl2 | ctl3\n+\t */\n+\t{2, 2140, 0, 4, 4, 0x0, 0x0},\n+\t{1, 2140, 0, 6, 4, 0x0, 0x0},\n+\t{}\n+};\n+\n+static const struct board_specific_parameters udimm0[] = {\n+\t/*\n+\t * memory controller 0\n+\t * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T\n+\t * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |\n+\t */\n+\t{1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},\n+\t{1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},\n+\t{1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},\n+\t{1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},\n+\t{2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},\n+\t{2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},\n+\t{2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},\n+\t{2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},\n+\t{2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},\n+\t{}\n+};\n+\n+static const struct board_specific_parameters *udimms[] = {\n+\tudimm0,\n+};\n+\n+static const struct board_specific_parameters *rdimms[] = {\n+\trdimm0,\n+};\n+\n+#endif\ndiff --git a/board/freescale/ls1021aqds/eth.c b/board/freescale/ls1021aqds/eth.c\nnew file mode 100644\nindex 0000000..6e81d7c\n--- /dev/null\n+++ b/board/freescale/ls1021aqds/eth.c\n@@ -0,0 +1,129 @@\n+/*\n+ * Copyright 2014 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+/*\n+ * The RGMII PHYs are provided by the there on-board PHY connected\n+ * to eTSEC instances 0, 1 and 2. The SGMII PHYs are provided by\n+ * the standard four-port SGMII riser card (VSC).\n+ */\n+\n+#include <common.h>\n+#include <netdev.h>\n+#include <asm/io.h>\n+#include <asm/arch/fsl_serdes.h>\n+#include <fsl_mdio.h>\n+#include <tsec.h>\n+\n+#include \"../common/sgmii_riser.h\"\n+#include \"../common/qixis.h\"\n+\n+#define EMI1_MASK\t0x1f\n+#define EMI1_RGMII0\t1\n+#define EMI1_RGMII1\t2\n+#define EMI1_RGMII2\t3\n+#define EMI1_SGMII1\t0x1c\n+#define EMI1_SGMII2\t0x1d\n+\n+static void ls1021a_qds_mux_mdio(int addr)\n+{\n+\tu8 brdcfg4;\n+\n+\tbrdcfg4 = QIXIS_READ(brdcfg[4]);\n+\tbrdcfg4 &= EMI1_MASK;\n+\n+\tswitch (addr) {\n+\tcase EMI1_RGMII0:\n+\t\tbrdcfg4 |= 0;\n+\t\tbreak;\n+\tcase EMI1_RGMII1:\n+\t\tbrdcfg4 |= 0x20;\n+\t\tbreak;\n+\tcase EMI1_RGMII2:\n+\t\tbrdcfg4 |= 0x40;\n+\t\tbreak;\n+\tcase EMI1_SGMII1:\n+\t\tbrdcfg4 |= 0x60;\n+\t\tbreak;\n+\tcase EMI1_SGMII2:\n+\t\tbrdcfg4 |= 0x80;\n+\t\tbreak;\n+\tdefault:\n+\t\tbrdcfg4 |= 0xa0;\n+\t\tbreak;\n+\t}\n+\n+\tQIXIS_WRITE(brdcfg[4], brdcfg4);\n+}\n+\n+static int ls1021a_qds_mdio_read(struct mii_dev *bus, int addr, int dev_addr,\n+\t\t\t\t int regnum)\n+{\n+\tstruct tsec_mii_mng __iomem *phyregs =\n+\t\t(struct tsec_mii_mng __iomem *)bus->priv;\n+\n+\tls1021a_qds_mux_mdio(addr);\n+\n+\treturn tsec_local_mdio_read(phyregs, addr, dev_addr, regnum);\n+}\n+\n+static int ls1021a_qds_mdio_write(struct mii_dev *bus, int addr, int dev_addr,\n+\t\t\t\t int regnum, u16 value)\n+{\n+\tstruct tsec_mii_mng __iomem *phyregs =\n+\t\t(struct tsec_mii_mng __iomem *)bus->priv;\n+\n+\tls1021a_qds_mux_mdio(addr);\n+\n+\ttsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value);\n+\n+\treturn 0;\n+}\n+\n+int board_eth_init(bd_t *bis)\n+{\n+\tstruct fsl_pq_mdio_info mdio_info;\n+\tstruct tsec_info_struct tsec_info[4];\n+\tint num = 0;\n+\n+#ifdef CONFIG_TSEC1\n+\tSET_STD_TSEC_INFO(tsec_info[num], 1);\n+\tif (is_serdes_configured(SGMII_TSEC1)) {\n+\t\tputs(\"eTSEC1 is in sgmii mode\\n\");\n+\t\ttsec_info[num].flags |= TSEC_SGMII;\n+\t}\n+\tnum++;\n+#endif\n+#ifdef CONFIG_TSEC2\n+\tSET_STD_TSEC_INFO(tsec_info[num], 2);\n+\tif (is_serdes_configured(SGMII_TSEC2)) {\n+\t\tputs(\"eTSEC2 is in sgmii mode\\n\");\n+\t\ttsec_info[num].flags |= TSEC_SGMII;\n+\t}\n+\tnum++;\n+#endif\n+#ifdef CONFIG_TSEC3\n+\tSET_STD_TSEC_INFO(tsec_info[num], 3);\n+\tnum++;\n+#endif\n+\tif (!num) {\n+\t\tprintf(\"No TSECs initialized\\n\");\n+\t\treturn 0;\n+\t}\n+\n+#ifdef CONFIG_FSL_SGMII_RISER\n+\tfsl_sgmii_riser_init(tsec_info, num);\n+#endif\n+\n+\tmdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;\n+\tmdio_info.name = DEFAULT_MII_NAME;\n+\tmdio_info.priv_mdio_read = ls1021a_qds_mdio_read;\n+\tmdio_info.priv_mdio_write = ls1021a_qds_mdio_write;\n+\tfsl_pq_mdio_init(bis, &mdio_info);\n+\n+\ttsec_eth_init(bis, tsec_info, num);\n+\n+\treturn pci_eth_init(bis);\n+}\ndiff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c\nnew file mode 100644\nindex 0000000..e35d19a\n--- /dev/null\n+++ b/board/freescale/ls1021aqds/ls1021aqds.c\n@@ -0,0 +1,248 @@\n+/*\n+ * Copyright 2014 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <i2c.h>\n+#include <asm/io.h>\n+#include <asm/arch/immap_ls102xa.h>\n+#include <asm/arch/clock.h>\n+#include <asm/arch/fsl_serdes.h>\n+#include <mmc.h>\n+#include <fsl_esdhc.h>\n+#include <fsl_ifc.h>\n+\n+#include \"../common/qixis.h\"\n+#include \"ls1021aqds_qixis.h\"\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+enum {\n+\tMUX_TYPE_SD_PCI4,\n+\tMUX_TYPE_SD_PC_SA_SG_SG,\n+\tMUX_TYPE_SD_PC_SA_PC_SG,\n+\tMUX_TYPE_SD_PC_SG_SG,\n+};\n+\n+int checkboard(void)\n+{\n+\tchar buf[64];\n+\tu8 sw;\n+\n+\tputs(\"Board: LS1021AQDS\\n\");\n+\n+\tsw = QIXIS_READ(brdcfg[0]);\n+\tsw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;\n+\n+\tif (sw < 0x8)\n+\t\tprintf(\"vBank: %d\\n\", sw);\n+\telse if (sw == 0x8)\n+\t\tputs(\"PromJet\\n\");\n+\telse if (sw == 0x9)\n+\t\tputs(\"NAND\\n\");\n+\telse if (sw == 0x15)\n+\t\tprintf(\"IFCCard\\n\");\n+\telse\n+\t\tprintf(\"invalid setting of SW%u\\n\", QIXIS_LBMAP_SWITCH);\n+\n+\tprintf(\"Sys ID:0x%02x, Sys Ver: 0x%02x\\n\",\n+\t QIXIS_READ(id), QIXIS_READ(arch));\n+\n+\tprintf(\"FPGA: v%d (%s), build %d\\n\",\n+\t (int)QIXIS_READ(scver), qixis_read_tag(buf),\n+\t (int)qixis_read_minor());\n+\n+\treturn 0;\n+}\n+\n+unsigned long get_board_sys_clk(void)\n+{\n+\tu8 sysclk_conf = QIXIS_READ(brdcfg[1]);\n+\n+\tswitch (sysclk_conf & 0x0f) {\n+\tcase QIXIS_SYSCLK_64:\n+\t\treturn 64000000;\n+\tcase QIXIS_SYSCLK_83:\n+\t\treturn 83333333;\n+\tcase QIXIS_SYSCLK_100:\n+\t\treturn 100000000;\n+\tcase QIXIS_SYSCLK_125:\n+\t\treturn 125000000;\n+\tcase QIXIS_SYSCLK_133:\n+\t\treturn 133333333;\n+\tcase QIXIS_SYSCLK_150:\n+\t\treturn 150000000;\n+\tcase QIXIS_SYSCLK_160:\n+\t\treturn 160000000;\n+\tcase QIXIS_SYSCLK_166:\n+\t\treturn 166666666;\n+\t}\n+\treturn 66666666;\n+}\n+\n+unsigned long get_board_ddr_clk(void)\n+{\n+\tu8 ddrclk_conf = QIXIS_READ(brdcfg[1]);\n+\n+\tswitch ((ddrclk_conf & 0x30) >> 4) {\n+\tcase QIXIS_DDRCLK_100:\n+\t\treturn 100000000;\n+\tcase QIXIS_DDRCLK_125:\n+\t\treturn 125000000;\n+\tcase QIXIS_DDRCLK_133:\n+\t\treturn 133333333;\n+\t}\n+\treturn 66666666;\n+}\n+\n+int dram_init(void)\n+{\n+\tgd->ram_size = initdram(0);\n+\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_FSL_ESDHC\n+struct fsl_esdhc_cfg esdhc_cfg[1] = {\n+\t{CONFIG_SYS_FSL_ESDHC_ADDR},\n+};\n+\n+int board_mmc_init(bd_t *bis)\n+{\n+\tesdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);\n+\n+\treturn fsl_esdhc_initialize(bis, &esdhc_cfg[0]);\n+}\n+#endif\n+\n+int select_i2c_ch_pca9547(u8 ch)\n+{\n+\tint ret;\n+\n+\tret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);\n+\tif (ret) {\n+\t\tputs(\"PCA: failed to select proper channel\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int board_early_init_f(void)\n+{\n+\tstruct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;\n+\tstruct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;\n+\n+#ifdef CONFIG_TSEC_ENET\n+\tout_be32(&scfg->scfgrevcr, 0xffffffff);\n+\tout_be32(&scfg->etsecdmamcr, 0xf8001a0f);\n+\tout_be32(&scfg->scfgrevcr, 0x00000000);\n+#endif\n+\n+#ifdef CONFIG_FSL_IFC\n+\tinit_early_memctl_regs();\n+#endif\n+\n+\tout_le32(&cci->ctrl_ord, 0x00000008);\n+\n+\treturn 0;\n+}\n+\n+int config_board_mux(int ctrl_type)\n+{\n+\tu8 reg12;\n+\n+\treg12 = QIXIS_READ(brdcfg[12]);\n+\n+\tswitch (ctrl_type) {\n+\tcase MUX_TYPE_SD_PCI4:\n+\t\treg12 = 0x38;\n+\t\tbreak;\n+\tcase MUX_TYPE_SD_PC_SA_SG_SG:\n+\t\treg12 = 0x01;\n+\t\tbreak;\n+\tcase MUX_TYPE_SD_PC_SA_PC_SG:\n+\t\treg12 = 0x01;\n+\t\tbreak;\n+\tcase MUX_TYPE_SD_PC_SG_SG:\n+\t\treg12 = 0x21;\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"Wrong mux interface type\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tQIXIS_WRITE(brdcfg[12], reg12);\n+\n+\treturn 0;\n+}\n+\n+int config_serdes_mux(void)\n+{\n+\tstruct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;\n+\tu32 cfg;\n+\n+\tcfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;\n+\tcfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;\n+\n+\tswitch (cfg) {\n+\tcase 0x0:\n+\t\tconfig_board_mux(MUX_TYPE_SD_PCI4);\n+\t\tbreak;\n+\tcase 0x30:\n+\t\tconfig_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);\n+\t\tbreak;\n+\tcase 0x60:\n+\t\tconfig_board_mux(MUX_TYPE_SD_PC_SG_SG);\n+\t\tbreak;\n+\tcase 0x70:\n+\t\tconfig_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"SRDS1 prtcl:0x%x\\n\", cfg);\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int board_init(void)\n+{\n+\tstruct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;\n+\n+\tout_le32(&cci->ctrl_ord, 0);\n+\n+\tselect_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);\n+\n+#ifndef CONFIG_SYS_FSL_NO_SERDES\n+\tfsl_serdes_init();\n+\tconfig_serdes_mux();\n+#endif\n+\treturn 0;\n+}\n+\n+void ft_board_setup(void *blob, bd_t *bd)\n+{\n+\tft_cpu_setup(blob, bd);\n+}\n+\n+u8 flash_read8(void *addr)\n+{\n+\treturn __raw_readb(addr + 1);\n+}\n+\n+void flash_write16(u16 val, void *addr)\n+{\n+\tu16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));\n+\n+\t__raw_writew(shftval, addr);\n+}\n+\n+u16 flash_read16(void *addr)\n+{\n+\tu16 val = __raw_readw(addr);\n+\n+\treturn (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);\n+}\ndiff --git a/board/freescale/ls1021aqds/ls1021aqds_qixis.h b/board/freescale/ls1021aqds/ls1021aqds_qixis.h\nnew file mode 100644\nindex 0000000..09b3be2\n--- /dev/null\n+++ b/board/freescale/ls1021aqds/ls1021aqds_qixis.h\n@@ -0,0 +1,35 @@\n+/*\n+ * Copyright 2014 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LS1021AQDS_QIXIS_H__\n+#define __LS1021AQDS_QIXIS_H__\n+\n+/* Definitions of QIXIS Registers for LS1021AQDS */\n+\n+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */\n+#define BRDCFG4_EMISEL_MASK\t\t0xe0\n+#define BRDCFG4_EMISEL_SHIFT\t\t5\n+\n+/* SYSCLK */\n+#define QIXIS_SYSCLK_66\t\t\t0x0\n+#define QIXIS_SYSCLK_83\t\t\t0x1\n+#define QIXIS_SYSCLK_100\t\t0x2\n+#define QIXIS_SYSCLK_125\t\t0x3\n+#define QIXIS_SYSCLK_133\t\t0x4\n+#define QIXIS_SYSCLK_150\t\t0x5\n+#define QIXIS_SYSCLK_160\t\t0x6\n+#define QIXIS_SYSCLK_166\t\t0x7\n+#define QIXIS_SYSCLK_64\t\t\t0x8\n+\n+/* DDRCLK */\n+#define QIXIS_DDRCLK_66\t\t\t0x0\n+#define QIXIS_DDRCLK_100\t\t0x1\n+#define QIXIS_DDRCLK_125\t\t0x2\n+#define QIXIS_DDRCLK_133\t\t0x3\n+\n+#define QIXIS_SRDS1CLK_100\t\t0x0\n+\n+#endif\ndiff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig\nnew file mode 100644\nindex 0000000..9e42d61\n--- /dev/null\n+++ b/configs/ls1021aqds_nor_defconfig\n@@ -0,0 +1,2 @@\n+CONFIG_ARM=y\n+CONFIG_TARGET_LS1021AQDS=y\ndiff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h\nnew file mode 100644\nindex 0000000..856fdfc\n--- /dev/null\n+++ b/include/configs/ls1021aqds.h\n@@ -0,0 +1,424 @@\n+/*\n+ * Copyright 2014 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#include <config_cmd_default.h>\n+\n+#define CONFIG_LS102xA\n+\n+#define CONFIG_SYS_GENERIC_BOARD\n+\n+#define CONFIG_DISPLAY_CPUINFO\n+#define CONFIG_DISPLAY_BOARDINFO\n+\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_BOARD_EARLY_INIT_F\n+\n+/*\n+ * Size of malloc() pool\n+ */\n+#define CONFIG_SYS_MALLOC_LEN\t\t(CONFIG_ENV_SIZE + 16 * 1024 * 1024)\n+\n+#define OCRAM_BASE_ADDR\t\t\t0x10000000\n+#define OCRAM_SIZE\t\t\t0x00020000\n+\n+#define CONFIG_SYS_INIT_RAM_ADDR\tOCRAM_BASE_ADDR\n+#define CONFIG_SYS_INIT_RAM_SIZE\tOCRAM_SIZE\n+\n+/*\n+ * Generic Timer Definitions\n+ */\n+#define GENERIC_TIMER_CLK\t\t12500000\n+\n+#ifndef __ASSEMBLY__\n+unsigned long get_board_sys_clk(void);\n+unsigned long get_board_ddr_clk(void);\n+#endif\n+\n+#define CONFIG_SYS_CLK_FREQ\t\tget_board_sys_clk()\n+#define CONFIG_DDR_CLK_FREQ\t\tget_board_ddr_clk()\n+\n+#ifndef CONFIG_SYS_TEXT_BASE\n+#define CONFIG_SYS_TEXT_BASE\t\t0x67f80000\n+#endif\n+\n+#define CONFIG_NR_DRAM_BANKS\t\t1\n+\n+#define CONFIG_DDR_SPD\n+#define SPD_EEPROM_ADDRESS\t\t0x51\n+#define CONFIG_SYS_SPD_BUS_NUM\t\t0\n+#define CONFIG_SYS_DDR_RAW_TIMING\n+\n+#define CONFIG_FSL_DDR_INTERACTIVE\t/* Interactive debugging */\n+#define CONFIG_SYS_FSL_DDR3\t\t/* Use DDR3 memory */\n+#define CONFIG_DIMM_SLOTS_PER_CTLR\t1\n+#define CONFIG_CHIP_SELECTS_PER_CTRL\t4\n+\n+#define CONFIG_SYS_DDR_SDRAM_BASE\t0x80000000UL\n+#define CONFIG_SYS_SDRAM_BASE\t\tCONFIG_SYS_DDR_SDRAM_BASE\n+\n+#define CONFIG_DDR_ECC\n+#ifdef CONFIG_DDR_ECC\n+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER\n+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef\n+#endif\n+\n+#define CONFIG_SYS_HAS_SERDES\n+\n+/*\n+ * IFC Definitions\n+ */\n+#define CONFIG_FSL_IFC\n+#define CONFIG_SYS_FLASH_BASE\t\t0x60000000\n+#define CONFIG_SYS_FLASH_BASE_PHYS\tCONFIG_SYS_FLASH_BASE\n+\n+#define CONFIG_SYS_NOR0_CSPR_EXT\t(0x0)\n+#define CONFIG_SYS_NOR0_CSPR\t(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \\\n+\t\t\t\tCSPR_PORT_SIZE_16 | \\\n+\t\t\t\tCSPR_MSEL_NOR | \\\n+\t\t\t\tCSPR_V)\n+#define CONFIG_SYS_NOR1_CSPR_EXT\t(0x0)\n+#define CONFIG_SYS_NOR1_CSPR\t(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \\\n+\t\t\t\t+ 0x8000000) | \\\n+\t\t\t\tCSPR_PORT_SIZE_16 | \\\n+\t\t\t\tCSPR_MSEL_NOR | \\\n+\t\t\t\tCSPR_V)\n+#define CONFIG_SYS_NOR_AMASK\t\tIFC_AMASK(128 * 1024 * 1024)\n+\n+#define CONFIG_SYS_NOR_CSOR\t\t(CSOR_NOR_ADM_SHIFT(4) | \\\n+\t\t\t\t\tCSOR_NOR_TRHZ_80)\n+#define CONFIG_SYS_NOR_FTIM0\t\t(FTIM0_NOR_TACSE(0x4) | \\\n+\t\t\t\t\tFTIM0_NOR_TEADC(0x5) | \\\n+\t\t\t\t\tFTIM0_NOR_TEAHC(0x5))\n+#define CONFIG_SYS_NOR_FTIM1\t\t(FTIM1_NOR_TACO(0x35) | \\\n+\t\t\t\t\tFTIM1_NOR_TRAD_NOR(0x1a) | \\\n+\t\t\t\t\tFTIM1_NOR_TSEQRAD_NOR(0x13))\n+#define CONFIG_SYS_NOR_FTIM2\t\t(FTIM2_NOR_TCS(0x4) | \\\n+\t\t\t\t\tFTIM2_NOR_TCH(0x4) | \\\n+\t\t\t\t\tFTIM2_NOR_TWPH(0xe) | \\\n+\t\t\t\t\tFTIM2_NOR_TWP(0x1c))\n+#define CONFIG_SYS_NOR_FTIM3\t\t0\n+\n+#define CONFIG_FLASH_CFI_DRIVER\n+#define CONFIG_SYS_FLASH_CFI\n+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE\n+#define CONFIG_SYS_FLASH_QUIET_TEST\n+#define CONFIG_FLASH_SHOW_PROGRESS\t45\n+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS\n+\n+#define CONFIG_SYS_MAX_FLASH_BANKS\t2\t/* number of banks */\n+#define CONFIG_SYS_MAX_FLASH_SECT\t1024\t/* sectors per device */\n+#define CONFIG_SYS_FLASH_ERASE_TOUT\t60000\t/* Flash Erase Timeout (ms) */\n+#define CONFIG_SYS_FLASH_WRITE_TOUT\t500\t/* Flash Write Timeout (ms) */\n+\n+#define CONFIG_SYS_FLASH_EMPTY_INFO\n+#define CONFIG_SYS_FLASH_BANKS_LIST\t{CONFIG_SYS_FLASH_BASE_PHYS, \\\n+\t\t\t\t\tCONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}\n+\n+/*\n+ * NAND Flash Definitions\n+ */\n+#define CONFIG_NAND_FSL_IFC\n+\n+#define CONFIG_SYS_NAND_BASE\t\t0x7e800000\n+#define CONFIG_SYS_NAND_BASE_PHYS\tCONFIG_SYS_NAND_BASE\n+\n+#define CONFIG_SYS_NAND_CSPR_EXT\t(0x0)\n+\n+#define CONFIG_SYS_NAND_CSPR\t(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \\\n+\t\t\t\t| CSPR_PORT_SIZE_8\t\\\n+\t\t\t\t| CSPR_MSEL_NAND\t\\\n+\t\t\t\t| CSPR_V)\n+#define CONFIG_SYS_NAND_AMASK\tIFC_AMASK(64*1024)\n+#define CONFIG_SYS_NAND_CSOR\t(CSOR_NAND_ECC_ENC_EN\t/* ECC on encode */ \\\n+\t\t\t\t| CSOR_NAND_ECC_DEC_EN\t/* ECC on decode */ \\\n+\t\t\t\t| CSOR_NAND_ECC_MODE_4\t/* 4-bit ECC */ \\\n+\t\t\t\t| CSOR_NAND_RAL_3\t/* RAL = 3 Bytes */ \\\n+\t\t\t\t| CSOR_NAND_PGS_2K\t/* Page Size = 2K */ \\\n+\t\t\t\t| CSOR_NAND_SPRZ_64\t/* Spare size = 64 */ \\\n+\t\t\t\t| CSOR_NAND_PB(64))\t/* 64 Pages Per Block */\n+\n+#define CONFIG_SYS_NAND_ONFI_DETECTION\n+\n+#define CONFIG_SYS_NAND_FTIM0\t\t(FTIM0_NAND_TCCST(0x7) | \\\n+\t\t\t\t\tFTIM0_NAND_TWP(0x18) | \\\n+\t\t\t\t\tFTIM0_NAND_TWCHT(0x7) | \\\n+\t\t\t\t\tFTIM0_NAND_TWH(0xa))\n+#define CONFIG_SYS_NAND_FTIM1\t\t(FTIM1_NAND_TADLE(0x32) | \\\n+\t\t\t\t\tFTIM1_NAND_TWBE(0x39) | \\\n+\t\t\t\t\tFTIM1_NAND_TRR(0xe) | \\\n+\t\t\t\t\tFTIM1_NAND_TRP(0x18))\n+#define CONFIG_SYS_NAND_FTIM2\t\t(FTIM2_NAND_TRAD(0xf) | \\\n+\t\t\t\t\tFTIM2_NAND_TREH(0xa) | \\\n+\t\t\t\t\tFTIM2_NAND_TWHRE(0x1e))\n+#define CONFIG_SYS_NAND_FTIM3 0x0\n+\n+#define CONFIG_SYS_NAND_BASE_LIST\t{ CONFIG_SYS_NAND_BASE }\n+#define CONFIG_SYS_MAX_NAND_DEVICE\t1\n+#define CONFIG_MTD_NAND_VERIFY_WRITE\n+#define CONFIG_CMD_NAND\n+\n+#define CONFIG_SYS_NAND_BLOCK_SIZE\t(128 * 1024)\n+\n+/*\n+ * QIXIS Definitions\n+ */\n+#define CONFIG_FSL_QIXIS\n+\n+#ifdef CONFIG_FSL_QIXIS\n+#define QIXIS_BASE\t\t\t0x7fb00000\n+#define QIXIS_BASE_PHYS\t\t\tQIXIS_BASE\n+#define CONFIG_SYS_I2C_FPGA_ADDR\t0x66\n+#define QIXIS_LBMAP_SWITCH\t\t6\n+#define QIXIS_LBMAP_MASK\t\t0x0f\n+#define QIXIS_LBMAP_SHIFT\t\t0\n+#define QIXIS_LBMAP_DFLTBANK\t\t0x00\n+#define QIXIS_LBMAP_ALTBANK\t\t0x04\n+#define QIXIS_RST_CTL_RESET\t\t0x44\n+#define QIXIS_RCFG_CTL_RECONFIG_IDLE\t0x20\n+#define QIXIS_RCFG_CTL_RECONFIG_START\t0x21\n+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE\t0x08\n+\n+#define CONFIG_SYS_FPGA_CSPR_EXT\t(0x0)\n+#define CONFIG_SYS_FPGA_CSPR\t\t(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \\\n+\t\t\t\t\tCSPR_PORT_SIZE_8 | \\\n+\t\t\t\t\tCSPR_MSEL_GPCM | \\\n+\t\t\t\t\tCSPR_V)\n+#define CONFIG_SYS_FPGA_AMASK\t\tIFC_AMASK(64 * 1024)\n+#define CONFIG_SYS_FPGA_CSOR\t\t(CSOR_NOR_ADM_SHIFT(4) | \\\n+\t\t\t\t\tCSOR_NOR_NOR_MODE_AVD_NOR | \\\n+\t\t\t\t\tCSOR_NOR_TRHZ_80)\n+\n+/*\n+ * QIXIS Timing parameters for IFC GPCM\n+ */\n+#define CONFIG_SYS_FPGA_FTIM0\t\t(FTIM0_GPCM_TACSE(0xe) | \\\n+\t\t\t\t\tFTIM0_GPCM_TEADC(0xe) | \\\n+\t\t\t\t\tFTIM0_GPCM_TEAHC(0xe))\n+#define CONFIG_SYS_FPGA_FTIM1\t\t(FTIM1_GPCM_TACO(0xe) | \\\n+\t\t\t\t\tFTIM1_GPCM_TRAD(0x1f))\n+#define CONFIG_SYS_FPGA_FTIM2\t\t(FTIM2_GPCM_TCS(0xe) | \\\n+\t\t\t\t\tFTIM2_GPCM_TCH(0xe) | \\\n+\t\t\t\t\tFTIM2_GPCM_TWP(0xf0))\n+#define CONFIG_SYS_FPGA_FTIM3\t\t0x0\n+#endif\n+\n+#if defined(CONFIG_NAND)\n+#define CONFIG_SYS_CSPR0_EXT\t\tCONFIG_SYS_NAND_CSPR_EXT\n+#define CONFIG_SYS_CSPR0\t\tCONFIG_SYS_NAND_CSPR\n+#define CONFIG_SYS_AMASK0\t\tCONFIG_SYS_NAND_AMASK\n+#define CONFIG_SYS_CSOR0\t\tCONFIG_SYS_NAND_CSOR\n+#define CONFIG_SYS_CS0_FTIM0\t\tCONFIG_SYS_NAND_FTIM0\n+#define CONFIG_SYS_CS0_FTIM1\t\tCONFIG_SYS_NAND_FTIM1\n+#define CONFIG_SYS_CS0_FTIM2\t\tCONFIG_SYS_NAND_FTIM2\n+#define CONFIG_SYS_CS0_FTIM3\t\tCONFIG_SYS_NAND_FTIM3\n+#define CONFIG_SYS_CSPR1_EXT\t\tCONFIG_SYS_NOR0_CSPR_EXT\n+#define CONFIG_SYS_CSPR1\t\tCONFIG_SYS_NOR0_CSPR\n+#define CONFIG_SYS_AMASK1\t\tCONFIG_SYS_NOR_AMASK\n+#define CONFIG_SYS_CSOR1\t\tCONFIG_SYS_NOR_CSOR\n+#define CONFIG_SYS_CS1_FTIM0\t\tCONFIG_SYS_NOR_FTIM0\n+#define CONFIG_SYS_CS1_FTIM1\t\tCONFIG_SYS_NOR_FTIM1\n+#define CONFIG_SYS_CS1_FTIM2\t\tCONFIG_SYS_NOR_FTIM2\n+#define CONFIG_SYS_CS1_FTIM3\t\tCONFIG_SYS_NOR_FTIM3\n+#define CONFIG_SYS_CSPR2_EXT\t\tCONFIG_SYS_NOR1_CSPR_EXT\n+#define CONFIG_SYS_CSPR2\t\tCONFIG_SYS_NOR1_CSPR\n+#define CONFIG_SYS_AMASK2\t\tCONFIG_SYS_NOR_AMASK\n+#define CONFIG_SYS_CSOR2\t\tCONFIG_SYS_NOR_CSOR\n+#define CONFIG_SYS_CS2_FTIM0\t\tCONFIG_SYS_NOR_FTIM0\n+#define CONFIG_SYS_CS2_FTIM1\t\tCONFIG_SYS_NOR_FTIM1\n+#define CONFIG_SYS_CS2_FTIM2\t\tCONFIG_SYS_NOR_FTIM2\n+#define CONFIG_SYS_CS2_FTIM3\t\tCONFIG_SYS_NOR_FTIM3\n+#define CONFIG_SYS_CSPR3_EXT\t\tCONFIG_SYS_FPGA_CSPR_EXT\n+#define CONFIG_SYS_CSPR3\t\tCONFIG_SYS_FPGA_CSPR\n+#define CONFIG_SYS_AMASK3\t\tCONFIG_SYS_FPGA_AMASK\n+#define CONFIG_SYS_CSOR3\t\tCONFIG_SYS_FPGA_CSOR\n+#define CONFIG_SYS_CS3_FTIM0\t\tCONFIG_SYS_FPGA_FTIM0\n+#define CONFIG_SYS_CS3_FTIM1\t\tCONFIG_SYS_FPGA_FTIM1\n+#define CONFIG_SYS_CS3_FTIM2\t\tCONFIG_SYS_FPGA_FTIM2\n+#define CONFIG_SYS_CS3_FTIM3\t\tCONFIG_SYS_FPGA_FTIM3\n+#else\n+#define CONFIG_SYS_CSPR0_EXT\t\tCONFIG_SYS_NOR0_CSPR_EXT\n+#define CONFIG_SYS_CSPR0\t\tCONFIG_SYS_NOR0_CSPR\n+#define CONFIG_SYS_AMASK0\t\tCONFIG_SYS_NOR_AMASK\n+#define CONFIG_SYS_CSOR0\t\tCONFIG_SYS_NOR_CSOR\n+#define CONFIG_SYS_CS0_FTIM0\t\tCONFIG_SYS_NOR_FTIM0\n+#define CONFIG_SYS_CS0_FTIM1\t\tCONFIG_SYS_NOR_FTIM1\n+#define CONFIG_SYS_CS0_FTIM2\t\tCONFIG_SYS_NOR_FTIM2\n+#define CONFIG_SYS_CS0_FTIM3\t\tCONFIG_SYS_NOR_FTIM3\n+#define CONFIG_SYS_CSPR1_EXT\t\tCONFIG_SYS_NOR1_CSPR_EXT\n+#define CONFIG_SYS_CSPR1\t\tCONFIG_SYS_NOR1_CSPR\n+#define CONFIG_SYS_AMASK1\t\tCONFIG_SYS_NOR_AMASK\n+#define CONFIG_SYS_CSOR1\t\tCONFIG_SYS_NOR_CSOR\n+#define CONFIG_SYS_CS1_FTIM0\t\tCONFIG_SYS_NOR_FTIM0\n+#define CONFIG_SYS_CS1_FTIM1\t\tCONFIG_SYS_NOR_FTIM1\n+#define CONFIG_SYS_CS1_FTIM2\t\tCONFIG_SYS_NOR_FTIM2\n+#define CONFIG_SYS_CS1_FTIM3\t\tCONFIG_SYS_NOR_FTIM3\n+#define CONFIG_SYS_CSPR2_EXT\t\tCONFIG_SYS_NAND_CSPR_EXT\n+#define CONFIG_SYS_CSPR2\t\tCONFIG_SYS_NAND_CSPR\n+#define CONFIG_SYS_AMASK2\t\tCONFIG_SYS_NAND_AMASK\n+#define CONFIG_SYS_CSOR2\t\tCONFIG_SYS_NAND_CSOR\n+#define CONFIG_SYS_CS2_FTIM0\t\tCONFIG_SYS_NAND_FTIM0\n+#define CONFIG_SYS_CS2_FTIM1\t\tCONFIG_SYS_NAND_FTIM1\n+#define CONFIG_SYS_CS2_FTIM2\t\tCONFIG_SYS_NAND_FTIM2\n+#define CONFIG_SYS_CS2_FTIM3\t\tCONFIG_SYS_NAND_FTIM3\n+#define CONFIG_SYS_CSPR3_EXT\t\tCONFIG_SYS_FPGA_CSPR_EXT\n+#define CONFIG_SYS_CSPR3\t\tCONFIG_SYS_FPGA_CSPR\n+#define CONFIG_SYS_AMASK3\t\tCONFIG_SYS_FPGA_AMASK\n+#define CONFIG_SYS_CSOR3\t\tCONFIG_SYS_FPGA_CSOR\n+#define CONFIG_SYS_CS3_FTIM0\t\tCONFIG_SYS_FPGA_FTIM0\n+#define CONFIG_SYS_CS3_FTIM1\t\tCONFIG_SYS_FPGA_FTIM1\n+#define CONFIG_SYS_CS3_FTIM2\t\tCONFIG_SYS_FPGA_FTIM2\n+#define CONFIG_SYS_CS3_FTIM3\t\tCONFIG_SYS_FPGA_FTIM3\n+#endif\n+\n+/*\n+ * Serial Port\n+ */\n+#define CONFIG_CONS_INDEX\t\t1\n+#define CONFIG_SYS_NS16550\n+#define CONFIG_SYS_NS16550_SERIAL\n+#define CONFIG_SYS_NS16550_REG_SIZE\t1\n+#define CONFIG_SYS_NS16550_CLK\t\tget_serial_clock()\n+\n+#define CONFIG_BAUDRATE\t\t\t115200\n+\n+/*\n+ * I2C\n+ */\n+#define CONFIG_CMD_I2C\n+#define CONFIG_SYS_I2C\n+#define CONFIG_SYS_I2C_MXC\n+\n+/*\n+ * I2C bus multiplexer\n+ */\n+#define I2C_MUX_PCA_ADDR_PRI\t\t0x77\n+#define I2C_MUX_CH_DEFAULT\t\t0x8\n+\n+/*\n+ * MMC\n+ */\n+#define CONFIG_MMC\n+#define CONFIG_CMD_MMC\n+#define CONFIG_FSL_ESDHC\n+#define CONFIG_GENERIC_MMC\n+\n+/*\n+ * eTSEC\n+ */\n+#define CONFIG_TSEC_ENET\n+\n+#ifdef CONFIG_TSEC_ENET\n+#define CONFIG_MII\n+#define CONFIG_MII_DEFAULT_TSEC\t\t3\n+#define CONFIG_TSEC1\t\t\t1\n+#define CONFIG_TSEC1_NAME\t\t\"eTSEC1\"\n+#define CONFIG_TSEC2\t\t\t1\n+#define CONFIG_TSEC2_NAME\t\t\"eTSEC2\"\n+#define CONFIG_TSEC3\t\t\t1\n+#define CONFIG_TSEC3_NAME\t\t\"eTSEC3\"\n+\n+#define TSEC1_PHY_ADDR\t\t\t1\n+#define TSEC2_PHY_ADDR\t\t\t2\n+#define TSEC3_PHY_ADDR\t\t\t3\n+\n+#define TSEC1_FLAGS\t\t\t(TSEC_GIGABIT | TSEC_REDUCED)\n+#define TSEC2_FLAGS\t\t\t(TSEC_GIGABIT | TSEC_REDUCED)\n+#define TSEC3_FLAGS\t\t\t(TSEC_GIGABIT | TSEC_REDUCED)\n+\n+#define TSEC1_PHYIDX\t\t\t0\n+#define TSEC2_PHYIDX\t\t\t0\n+#define TSEC3_PHYIDX\t\t\t0\n+\n+#define CONFIG_ETHPRIME\t\t\t\"eTSEC1\"\n+\n+#define CONFIG_PHY_GIGE\n+#define CONFIG_PHYLIB\n+#define CONFIG_PHY_REALTEK\n+\n+#define CONFIG_HAS_ETH0\n+#define CONFIG_HAS_ETH1\n+#define CONFIG_HAS_ETH2\n+\n+#define CONFIG_FSL_SGMII_RISER\t\t1\n+#define SGMII_RISER_PHY_OFFSET\t\t0x1b\n+\n+#ifdef CONFIG_FSL_SGMII_RISER\n+#define CONFIG_SYS_TBIPA_VALUE\t\t8\n+#endif\n+\n+#endif\n+#define CONFIG_CMD_PING\n+#define CONFIG_CMD_DHCP\n+#define CONFIG_CMD_MII\n+#define CONFIG_CMD_NET\n+\n+#define CONFIG_CMDLINE_TAG\n+#define CONFIG_CMDLINE_EDITING\n+#undef CONFIG_CMD_IMLS\n+\n+#define CONFIG_HWCONFIG\n+#define HWCONFIG_BUFFER_SIZE\t\t128\n+\n+#define CONFIG_BOOTDELAY\t\t3\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\t\"bootargs=root=/dev/ram0 rw console=ttyS0,115200\\0\" \\\n+\t\"fdt_high=0xcfffffff\\0\"\t\t\\\n+\t\"initrd_high=0xcfffffff\\0\" \\\n+\t\"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\\0\"\n+\n+/*\n+ * Miscellaneous configurable options\n+ */\n+#define CONFIG_SYS_LONGHELP\t\t/* undef to save memory */\n+#define CONFIG_SYS_HUSH_PARSER\t\t/* use \"hush\" command parser */\n+#define CONFIG_SYS_PROMPT_HUSH_PS2\t\"> \"\n+#define CONFIG_SYS_PROMPT\t\t\"=> \"\n+#define CONFIG_AUTO_COMPLETE\n+#define CONFIG_SYS_CBSIZE\t\t256\t/* Console I/O Buffer Size */\n+#define CONFIG_SYS_PBSIZE\t\t\\\n+\t\t(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)\n+#define CONFIG_SYS_MAXARGS\t\t16\t/* max number of command args */\n+#define CONFIG_SYS_BARGSIZE\t\tCONFIG_SYS_CBSIZE\n+\n+#define CONFIG_CMD_MEMTEST\n+#define CONFIG_SYS_MEMTEST_START\t0x80000000\n+#define CONFIG_SYS_MEMTEST_END\t\t0x9fffffff\n+\n+#define CONFIG_SYS_LOAD_ADDR\t\t0x82000000\n+#define CONFIG_SYS_HZ\t\t\t1000\n+\n+/*\n+ * Stack sizes\n+ * The stack sizes are set up in start.S using the settings below\n+ */\n+#define CONFIG_STACKSIZE\t\t(30 * 1024)\n+\n+#define CONFIG_SYS_INIT_SP_OFFSET \\\n+\t(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)\n+#define CONFIG_SYS_INIT_SP_ADDR \\\n+\t(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)\n+\n+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */\n+\n+/*\n+ * Environment\n+ */\n+#define CONFIG_ENV_OVERWRITE\n+\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_ADDR\t\t(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)\n+#define CONFIG_ENV_SIZE\t\t\t0x2000\n+#define CONFIG_ENV_SECT_SIZE\t\t0x20000 /* 128K (one sector) */\n+\n+#define CONFIG_OF_LIBFDT\n+#define CONFIG_OF_BOARD_SETUP\n+#define CONFIG_CMD_BOOTZ\n+\n+#endif\n", "prefixes": [ "U-Boot", "v4", "11/18" ] }