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GET /api/patches/379799/?format=api
{ "id": 379799, "url": "http://patchwork.ozlabs.org/api/patches/379799/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1407984294-346-13-git-send-email-b18965@freescale.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1407984294-346-13-git-send-email-b18965@freescale.com>", "list_archive_url": null, "date": "2014-08-14T02:44:48", "name": "[U-Boot,v3,12/18] arm: ls102xa: Add basic support for LS1021ATWR board", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "cc6714234088d80c4b1829eadb7ade40eb112d86", "submitter": { "id": 13010, "url": "http://patchwork.ozlabs.org/api/people/13010/?format=api", "name": "Alison Wang", "email": "b18965@freescale.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1407984294-346-13-git-send-email-b18965@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/379799/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/379799/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 7E92D14008B\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 14 Aug 2014 13:37:05 +1000 (EST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id DE9304A056;\n\tThu, 14 Aug 2014 05:36:57 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id RiTcrpQD0mfL; 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Thu, 14 Aug 2014\n\t03:34:38 +0000", "from rock.ap.freescale.net (rock.ap.freescale.net [10.193.20.106])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\ts7E3Y70l001619; Wed, 13 Aug 2014 20:34:36 -0700" ], "X-Virus-Scanned": [ "Debian amavisd-new at theia.denx.de", "Debian amavisd-new at theia.denx.de" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Alison Wang <b18965@freescale.com>", "To": "<yorksun@freescale.com>, <u-boot@lists.denx.de>", "Date": "Thu, 14 Aug 2014 10:44:48 +0800", "Message-ID": "<1407984294-346-13-git-send-email-b18965@freescale.com>", "X-Mailer": "git-send-email 1.8.0", "In-Reply-To": "<1407984294-346-1-git-send-email-b18965@freescale.com>", "References": "<1407984294-346-1-git-send-email-b18965@freescale.com>", "X-EOPAttributedMessage": "0", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI;\n\tEFV:NLI; SFV:NSPM; \n\tSFS:(6009001)(199003)(54534003)(189002)(77982001)(88136002)(21056001)(4396001)(87936001)(50226001)(83072002)(107046002)(36756003)(62966002)(106466001)(95666004)(84676001)(105606002)(79102001)(104166001)(104016003)(85306004)(77156001)(50466002)(74502001)(229853001)(74662001)(64706001)(31966008)(20776003)(47776003)(19580395003)(575784001)(76482001)(46102001)(6806004)(83322001)(19580405001)(80022001)(102836001)(44976005)(26826002)(87286001)(48376002)(68736004)(81542001)(97736001)(93916002)(99396002)(81342001)(89996001)(85852003)(92566001)(50986999)(92726001)(76176999)(33646002)(42262002);\n\tDIR:OUT; SFP:; SCL:1; SRVR:BY2PR03MB380;\n\tH:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm;\n\tPTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; ", "MIME-Version": "1.0", "X-Microsoft-Antispam": "BCL:0;PCL:0;RULEID:;UriScan:;", "X-Forefront-PRVS": "03030B9493", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=alison.wang@freescale.com; ", "X-OriginatorOrg": "freescale.com", "Subject": "[U-Boot] [PATCH v3 12/18] arm: ls102xa: Add basic support for\n\tLS1021ATWR board", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.11", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "From: Wang Huan <b18965@freescale.com>\n\nThis patch is to add basic support for LS1021ATWR board.\nFor the detail board information, please refer to README.\n\nSigned-off-by: Chen Lu <chen.lu@freescale.com>\nSigned-off-by: Yuan Yao <yao.yuan@freescale.com>\nSigned-off-by: Alison Wang <alison.wang@freescale.com>\n---\nChange log:\n v3: Fix checkpatch error.\n Update to Kconfig. \n v2: New file.\n\n arch/arm/Kconfig | 4 +\n board/freescale/ls1021atwr/Kconfig | 23 ++\n board/freescale/ls1021atwr/MAINTAINERS | 6 +\n board/freescale/ls1021atwr/Makefile | 7 +\n board/freescale/ls1021atwr/README | 109 +++++++\n board/freescale/ls1021atwr/ls1021atwr.c | 494 ++++++++++++++++++++++++++++++++\n configs/ls1021atwr_nor_defconfig | 2 +\n include/configs/ls1021atwr.h | 284 ++++++++++++++++++\n 8 files changed, 929 insertions(+)\n create mode 100644 board/freescale/ls1021atwr/Kconfig\n create mode 100644 board/freescale/ls1021atwr/MAINTAINERS\n create mode 100644 board/freescale/ls1021atwr/Makefile\n create mode 100644 board/freescale/ls1021atwr/README\n create mode 100644 board/freescale/ls1021atwr/ls1021atwr.c\n create mode 100644 configs/ls1021atwr_nor_defconfig\n create mode 100644 include/configs/ls1021atwr.h", "diff": "diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\nindex 62b3cc8..d207db7 100644\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -734,6 +734,9 @@ config TARGET_LS2085A_SIMU\n config TARGET_LS1021AQDS\n \tbool \"Support ls1021aqds_nor\"\n \n+config TARGET_LS1021ATWR\n+\tbool \"Support ls1021atwr_nor\"\n+\n config TARGET_BALLOON3\n \tbool \"Support balloon3\"\n \n@@ -869,6 +872,7 @@ source \"board/eukrea/cpuat91/Kconfig\"\n source \"board/faraday/a320evb/Kconfig\"\n source \"board/freescale/ls2085a/Kconfig\"\n source \"board/freescale/ls1021aqds/Kconfig\"\n+source \"board/freescale/ls1021atwr/Kconfig\"\n source \"board/freescale/mx23evk/Kconfig\"\n source \"board/freescale/mx25pdk/Kconfig\"\n source \"board/freescale/mx28evk/Kconfig\"\ndiff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig\nnew file mode 100644\nindex 0000000..057808d\n--- /dev/null\n+++ b/board/freescale/ls1021atwr/Kconfig\n@@ -0,0 +1,23 @@\n+if TARGET_LS1021ATWR\n+\n+config SYS_CPU\n+\tstring\n+\tdefault \"armv7\"\n+\n+config SYS_BOARD\n+\tstring\n+\tdefault \"ls1021atwr\"\n+\n+config SYS_VENDOR\n+\tstring\n+\tdefault \"freescale\"\n+\n+config SYS_SOC\n+\tstring\n+\tdefault \"ls102xa\"\n+\n+config SYS_CONFIG_NAME\n+\tstring\n+\tdefault \"ls1021atwr\"\n+\n+endif\ndiff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS\nnew file mode 100644\nindex 0000000..4e5bc15\n--- /dev/null\n+++ b/board/freescale/ls1021atwr/MAINTAINERS\n@@ -0,0 +1,6 @@\n+LS1021ATWR BOARD\n+M:\tAlison Wang <alison.wang@freescale.com>\n+S:\tMaintained\n+F:\tboard/freescale/ls1021atwr/\n+F:\tinclude/configs/ls1021atwr.h\n+F:\tconfigs/ls1021atwr_nor_defconfig\ndiff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile\nnew file mode 100644\nindex 0000000..b5df668\n--- /dev/null\n+++ b/board/freescale/ls1021atwr/Makefile\n@@ -0,0 +1,7 @@\n+#\n+# Copyright 2014 Freescale Semiconductor, Inc.\n+#\n+# SPDX-License-Identifier: GPL-2.0+\n+#\n+\n+obj-y += ls1021atwr.o\ndiff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README\nnew file mode 100644\nindex 0000000..d2821cb\n--- /dev/null\n+++ b/board/freescale/ls1021atwr/README\n@@ -0,0 +1,109 @@\n+Overview\n+--------\n+The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC.\n+\n+LS1021A SoC Overview\n+------------------\n+The QorIQ LS1 family, which includes the LS1021A communications processor,\n+is built on Layerscape architecture, the industry's first software-aware,\n+core-agnostic networking architecture to offer unprecedented efficiency\n+and scale.\n+\n+A member of the value-performance tier, the QorIQ LS1021A processor provides\n+extensive integration and power efficiency for fanless, small form factor\n+enterprise networking applications. Incorporating dual ARM Cortex-A7 cores\n+running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark\n+performance of over 6,000, as well as virtualization support, advanced\n+security features and the broadest array of high-speed interconnects and\n+optimized peripheral features ever offered in a sub-3 W processor.\n+\n+The QorIQ LS1021A processor features an integrated LCD controller,\n+CAN controller for implementing industrial protocols, DDR3L/4 running\n+up to 1600 MHz, integrated security engine and QUICC Engine, and ECC\n+protection on both L1 and L2 caches. The LS1021A processor is pin- and\n+software-compatible with the QorIQ LS1020A and LS1022A processors.\n+\n+The LS1021A SoC includes the following function and features:\n+\n+ - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture\n+ - Dual high-preformance ARM Cortex-A7 cores, each core includes:\n+ - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection)\n+ - 512 Kbyte shared coherent L2 Cache (with ECC protection)\n+ - NEON Co-processor (per core)\n+ - 40-bit physical addressing\n+ - Vector floating-point support\n+ - ARM Core-Link CCI-400 Cache Coherent Interconnect\n+ - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration\n+ supporting speeds up to 1600Mtps\n+ - ECC and interleaving support\n+ - VeTSEC Ethernet complex\n+ - Up to 3x virtualized 10/100/1000 Ethernet controllers\n+ - MII, RMII, RGMII, and SGMII support\n+ - QoS, lossless flow control, and IEEE 1588 support\n+ - 4-lane 6GHz SerDes\n+ - High speed interconnect (4 SerDes lanes with are muxed for these protocol)\n+ - Two PCI Express Gen2 controllers running at up to 5 GHz\n+ - One Serial ATA 3.0 supporting 6 GT/s operation\n+ - Two SGMII interfaces supporting 1000 Mbps\n+ - Additional peripheral interfaces\n+ - One high-speed USB 3.0 controller with integrated PHY and one high-speed\n+ USB 2.00 controller with ULPI\n+ - Integrated flash controller (IFC) with 16-bit interface\n+ - Quad SPI NOR Flash\n+ - One enhanced Secure digital host controller\n+ - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface)\n+ - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power\n+ UARTs\n+ - Three I2C controllers\n+ - Eight FlexTimers four supporting PWM and four FlexCAN ports\n+ - Four GPIO controllers supporting up to 109 general purpose I/O signals\n+ - Integrated advanced audio block:\n+ - Four synchronous audio interfaces (SAI)\n+ - Sony/Philips Digital Interconnect Format (SPDIF)\n+ - Asynchronous Sample Rate Converter (ASRC)\n+ - Hardware based crypto offload engine\n+ - IPSec forwarding at up to 1Gbps\n+ - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported\n+ - Public key hardware accelerator\n+ - True Random Number Generator (NIST Certified)\n+ - Advanced Encryption Standard Accelerators (AESA)\n+ - Data Encryption Standard Accelerators\n+ - QUICC Engine ULite block\n+ - Two universal communication controllers (TDM and HDLC) supporting 64\n+ multichannels, each running at 64 Kbps\n+ - Support for 256 channels of HDLC\n+ - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported\n+\n+LS1021ATWR board Overview\n+-------------------------\n+ - DDR Controller\n+ - Supports rates of up to 1600 MHz data-rate\n+ - Supports one DDR3LP SDRAM.\n+ - IFC/Local Bus\n+ - NOR: 128MB 16-bit NOR Flash\n+ - Ethernet\n+ - Three on-board RGMII 10/100/1G ethernet ports.\n+ - CPLD\n+ - Clocks\n+ - System and DDR clock (SYSCLK, DDRCLK)\n+ - SERDES clocks\n+ - Power Supplies\n+ - SDHC\n+ - SDHC/SDXC connector\n+ - Other IO\n+ - One Serial port\n+ - Three I2C ports\n+\n+Memory map\n+-----------\n+The addresses in brackets are physical addresses.\n+\n+Start Address\tEnd Address\tDescription\t\t\tSize\n+0x00_0000_0000\t0x00_000F_FFFF\tSecure Boot ROM\t\t\t1MB\n+0x00_0100_0000\t0x00_0FFF_FFFF\tCCSRBAR\t\t\t\t240MB\n+0x00_1000_0000\t0x00_1000_FFFF\tOCRAM0\t\t\t\t64KB\n+0x00_1001_0000\t0x00_1001_FFFF\tOCRAM1\t\t\t\t64KB\n+0x00_2000_0000\t0x00_20FF_FFFF\tDCSR\t\t\t\t16MB\n+0x00_4000_0000\t0x00_5FFF_FFFF\tQSPI\t\t\t\t512MB\n+0x00_6000_0000\t0x00_67FF_FFFF\tIFC - NOR Flash\t\t\t128MB\n+0x00_8000_0000\t0x00_FFFF_FFFF\tDRAM1\t\t\t\t2GB\ndiff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c\nnew file mode 100644\nindex 0000000..7fdcbcd\n--- /dev/null\n+++ b/board/freescale/ls1021atwr/ls1021atwr.c\n@@ -0,0 +1,494 @@\n+/*\n+ * Copyright 2014 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <i2c.h>\n+#include <asm/io.h>\n+#include <asm/arch/immap_ls102xa.h>\n+#include <asm/arch/clock.h>\n+#include <asm/arch/fsl_serdes.h>\n+#include <mmc.h>\n+#include <fsl_esdhc.h>\n+#include <fsl_ifc.h>\n+#include <netdev.h>\n+#include <fsl_mdio.h>\n+#include <tsec.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+#define VERSION_MASK\t\t0x00FF\n+#define BANK_MASK\t\t0x0001\n+#define CONFIG_RESET\t\t0x1\n+#define INIT_RESET\t\t0x1\n+\n+#define CPLD_SET_MUX_SERDES\t0x20\n+#define CPLD_SET_BOOT_BANK\t0x40\n+\n+#define BOOT_FROM_UPPER_BANK\t0x0\n+#define BOOT_FROM_LOWER_BANK\t0x1\n+\n+#define LANEB_SATA\t\t(0x01)\n+#define LANEB_SGMII1\t\t(0x02)\n+#define LANEC_SGMII1\t\t(0x04)\n+#define LANEC_PCIEX1\t\t(0x08)\n+#define LANED_PCIEX2\t\t(0x10)\n+#define LANED_SGMII2\t\t(0x20)\n+\n+#define MASK_LANE_B\t\t0x1\n+#define MASK_LANE_C\t\t0x2\n+#define MASK_LANE_D\t\t0x4\n+#define MASK_SGMII\t\t0x8\n+\n+#define KEEP_STATUS\t\t0x0\n+#define NEED_RESET\t\t0x1\n+\n+struct cpld_data {\n+\tu8 cpld_ver;\t\t/* cpld revision */\n+\tu8 cpld_ver_sub;\t/* cpld sub revision */\n+\tu8 pcba_ver;\t\t/* pcb revision number */\n+\tu8 system_rst;\t\t/* reset system by cpld */\n+\tu8 soft_mux_on;\t\t/* CPLD override physical switches Enable */\n+\tu8 cfg_rcw_src1;\t/* Reset config word 1 */\n+\tu8 cfg_rcw_src2;\t/* Reset config word 2 */\n+\tu8 vbank;\t\t/* Flash bank selection Control */\n+\tu8 gpio;\t\t/* GPIO for TWR-ELEV */\n+\tu8 i2c3_ifc_mux;\n+\tu8 mux_spi2;\n+\tu8 can3_usb2_mux;\t/* CAN3 and USB2 Selection */\n+\tu8 qe_lcd_mux;\t\t/* QE and LCD Selection */\n+\tu8 serdes_mux;\t\t/* Multiplexed pins for SerDes Lanes */\n+\tu8 global_rst;\t\t/* reset with init CPLD reg to default */\n+\tu8 rev1;\t\t/* Reserved */\n+\tu8 rev2;\t\t/* Reserved */\n+};\n+\n+static void convert_serdes_mux(int type, int need_reset);\n+\n+void cpld_show(void)\n+{\n+\tstruct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);\n+\n+\tprintf(\"CPLD: V%x.%x\\nPCBA: V%x.0\\nVBank: %d\\n\",\n+\t in_8(&cpld_data->cpld_ver) & VERSION_MASK,\n+\t in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,\n+\t in_8(&cpld_data->pcba_ver) & VERSION_MASK,\n+\t in_8(&cpld_data->vbank) & BANK_MASK);\n+\n+#ifdef CONFIG_DEBUG\n+\tprintf(\"soft_mux_on =%x\\n\",\n+\t in_8(&cpld_data->soft_mux_on));\n+\tprintf(\"soft_mux_on =%x\\n\",\n+\t in_8(&cpld_data->soft_mux_on));\n+\tprintf(\"cfg_rcw_src1 =%x\\n\",\n+\t in_8(&cpld_data->cfg_rcw_src1));\n+\tprintf(\"cfg_rcw_src2 =%x\\n\",\n+\t in_8(&cpld_data->cfg_rcw_src2));\n+\tprintf(\"vbank =%x\\n\",\n+\t in_8(&cpld_data->vbank));\n+\tprintf(\"gpio =%x\\n\",\n+\t in_8(&cpld_data->gpio));\n+\tprintf(\"i2c3_ifc_mux =%x\\n\",\n+\t in_8(&cpld_data->i2c3_ifc_mux));\n+\tprintf(\"mux_spi2 =%x\\n\",\n+\t in_8(&cpld_data->mux_spi2));\n+\tprintf(\"can3_usb2_mux =%x\\n\",\n+\t in_8(&cpld_data->can3_usb2_mux));\n+\tprintf(\"qe_lcd_mux =%x\\n\",\n+\t in_8(&cpld_data->qe_lcd_mux));\n+\tprintf(\"serdes_mux =%x\\n\",\n+\t in_8(&cpld_data->serdes_mux));\n+#endif\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: LS1021ATWR\\n\");\n+\tcpld_show();\n+\n+\treturn 0;\n+}\n+\n+void ddrmc_init(void)\n+{\n+\tstruct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;\n+\n+\tout_be32(&ddr->sdram_cfg, 0x470c0008);\n+\n+\tout_be32(&ddr->cs0_bnds, 0x008000bf);\n+\tout_be32(&ddr->cs0_config, 0x80014302);\n+\n+\tout_be32(&ddr->timing_cfg_0, 0x50550004);\n+\tout_be32(&ddr->timing_cfg_1, 0xbcb38c56);\n+\tout_be32(&ddr->timing_cfg_2, 0x0040d120);\n+\tout_be32(&ddr->timing_cfg_3, 0x010e1000);\n+\tout_be32(&ddr->timing_cfg_4, 0x00000001);\n+\tout_be32(&ddr->timing_cfg_5, 0x03401400);\n+\n+\tout_be32(&ddr->sdram_cfg_2, 0x00401010);\n+\n+\tout_be32(&ddr->sdram_mode, 0x00061c60);\n+\tout_be32(&ddr->sdram_mode_2, 0x00180000);\n+\n+\tout_be32(&ddr->sdram_interval, 0x18600618);\n+\n+\tout_be32(&ddr->ddr_wrlvl_cntl, 0x8655f605);\n+\n+\tout_be32(&ddr->ddr_wrlvl_cntl_2, 0x05060607);\n+\tout_be32(&ddr->ddr_wrlvl_cntl_3, 0x05050505);\n+\n+\tout_be32(&ddr->ddr_cdr1, 0x80040000);\n+\tout_be32(&ddr->ddr_cdr2, 0x00000001);\n+\n+\tout_be32(&ddr->sdram_clk_cntl, 0x02000000);\n+\tout_be32(&ddr->ddr_zq_cntl, 0x89080600);\n+\n+\tout_be32(&ddr->cs0_config_2, 0x00000000);\n+\tudelay(1);\n+\tout_be32(&ddr->sdram_cfg, 0xc70c0008);\n+}\n+\n+int dram_init(void)\n+{\n+#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))\n+\tddrmc_init();\n+#endif\n+\n+\tgd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_FSL_ESDHC\n+struct fsl_esdhc_cfg esdhc_cfg[1] = {\n+\t{CONFIG_SYS_FSL_ESDHC_ADDR},\n+};\n+\n+int board_mmc_init(bd_t *bis)\n+{\n+\tesdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);\n+\n+\treturn fsl_esdhc_initialize(bis, &esdhc_cfg[0]);\n+}\n+#endif\n+\n+#ifdef CONFIG_TSEC_ENET\n+int board_eth_init(bd_t *bis)\n+{\n+\tstruct fsl_pq_mdio_info mdio_info;\n+\tstruct tsec_info_struct tsec_info[4];\n+\tint num = 0;\n+\n+#ifdef CONFIG_TSEC1\n+\tSET_STD_TSEC_INFO(tsec_info[num], 1);\n+\tif (is_serdes_configured(SGMII_TSEC1)) {\n+\t\tputs(\"eTSEC1 is in sgmii mode.\\n\");\n+\t\ttsec_info[num].flags |= TSEC_SGMII;\n+\t}\n+\tnum++;\n+#endif\n+#ifdef CONFIG_TSEC2\n+\tSET_STD_TSEC_INFO(tsec_info[num], 2);\n+\tif (is_serdes_configured(SGMII_TSEC2)) {\n+\t\tputs(\"eTSEC2 is in sgmii mode.\\n\");\n+\t\ttsec_info[num].flags |= TSEC_SGMII;\n+\t}\n+\tnum++;\n+#endif\n+#ifdef CONFIG_TSEC3\n+\tSET_STD_TSEC_INFO(tsec_info[num], 3);\n+\tnum++;\n+#endif\n+\tif (!num) {\n+\t\tprintf(\"No TSECs initialized\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\tmdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;\n+\tmdio_info.name = DEFAULT_MII_NAME;\n+\tfsl_pq_mdio_init(bis, &mdio_info);\n+\n+\ttsec_eth_init(bis, tsec_info, num);\n+\n+\treturn pci_eth_init(bis);\n+}\n+#endif\n+\n+int config_serdes_mux(void)\n+{\n+\tstruct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\n+\tu32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;\n+\n+\tprotocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;\n+\tswitch (protocol) {\n+\tcase 0x10:\n+\t\tconvert_serdes_mux(LANEB_SATA, KEEP_STATUS);\n+\t\tconvert_serdes_mux(LANED_PCIEX2 |\n+\t\t\t\tLANEC_PCIEX1, KEEP_STATUS);\n+\t\tbreak;\n+\tcase 0x20:\n+\t\tconvert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);\n+\t\tconvert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);\n+\t\tconvert_serdes_mux(LANED_SGMII2, KEEP_STATUS);\n+\t\tbreak;\n+\tcase 0x30:\n+\t\tconvert_serdes_mux(LANEB_SATA, KEEP_STATUS);\n+\t\tconvert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);\n+\t\tconvert_serdes_mux(LANED_SGMII2, KEEP_STATUS);\n+\t\tbreak;\n+\tcase 0x70:\n+\t\tconvert_serdes_mux(LANEB_SATA, KEEP_STATUS);\n+\t\tconvert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);\n+\t\tconvert_serdes_mux(LANED_SGMII2, KEEP_STATUS);\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int board_early_init_f(void)\n+{\n+\tstruct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;\n+\tstruct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;\n+\n+#ifdef CONFIG_TSEC_ENET\n+\tout_be32(&scfg->scfgrevcr, 0xffffffff);\n+\tout_be32(&scfg->etsecdmamcr, 0xf8001a0f);\n+\tout_be32(&scfg->etsecmcr, 0x04000000);\n+\tudelay(10);\n+\tout_be32(&scfg->scfgrevcr, 0x00000000);\n+#endif\n+\n+#ifdef CONFIG_FSL_IFC\n+\tinit_early_memctl_regs();\n+#endif\n+\n+\tout_le32(&cci->ctrl_ord, 0x00000008);\n+\n+\treturn 0;\n+}\n+\n+int board_init(void)\n+{\n+\tstruct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;\n+\n+\tout_le32(&cci->ctrl_ord, 0);\n+\n+\t/* address of boot parameters */\n+\tgd->bd->bi_boot_params = PHYS_SDRAM + 0x100;\n+\n+#ifndef CONFIG_SYS_FSL_NO_SERDES\n+\tfsl_serdes_init();\n+\tconfig_serdes_mux();\n+#endif\n+\n+\treturn 0;\n+}\n+\n+void ft_board_setup(void *blob, bd_t *bd)\n+{\n+\tft_cpu_setup(blob, bd);\n+}\n+\n+u8 flash_read8(void *addr)\n+{\n+\treturn __raw_readb(addr + 1);\n+}\n+\n+void flash_write16(u16 val, void *addr)\n+{\n+\tu16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));\n+\n+\t__raw_writew(shftval, addr);\n+}\n+\n+u16 flash_read16(void *addr)\n+{\n+\tu16 val = __raw_readw(addr);\n+\n+\treturn (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);\n+}\n+\n+static void convert_flash_bank(char bank)\n+{\n+\tstruct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);\n+\n+\tprintf(\"Now switch to boot from flash bank %d.\\n\", bank);\n+\tcpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;\n+\tcpld_data->vbank = bank;\n+\n+\tprintf(\"Reset board to enable configuration.\\n\");\n+\tcpld_data->system_rst = CONFIG_RESET;\n+}\n+\n+static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,\n+\t\t\t char * const argv[])\n+{\n+\tif (argc != 2)\n+\t\treturn CMD_RET_USAGE;\n+\tif (strcmp(argv[1], \"0\") == 0)\n+\t\tconvert_flash_bank(BOOT_FROM_UPPER_BANK);\n+\telse if (strcmp(argv[1], \"1\") == 0)\n+\t\tconvert_flash_bank(BOOT_FROM_LOWER_BANK);\n+\telse\n+\t\treturn CMD_RET_USAGE;\n+\n+\treturn 0;\n+}\n+\n+U_BOOT_CMD(\n+\tboot_bank, 2, 0, flash_bank_cmd,\n+\t\"Flash bank Selection Control\",\n+\t\"bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)\"\n+);\n+\n+static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,\n+\t\t\t char * const argv[])\n+{\n+\tstruct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);\n+\n+\tif (argc > 2)\n+\t\treturn CMD_RET_USAGE;\n+\tif ((argc == 1) || (strcmp(argv[1], \"conf\") == 0))\n+\t\tcpld_data->system_rst = CONFIG_RESET;\n+\telse if (strcmp(argv[1], \"init\") == 0)\n+\t\tcpld_data->global_rst = INIT_RESET;\n+\telse\n+\t\treturn CMD_RET_USAGE;\n+\n+\treturn 0;\n+}\n+\n+U_BOOT_CMD(\n+\tcpld_reset, 2, 0, cpld_reset_cmd,\n+\t\"Reset via CPLD\",\n+\t\"conf\\n\"\n+\t\"\t-reset with current CPLD configuration\\n\"\n+\t\"init\\n\"\n+\t\"\t-reset and initial CPLD configuration with default value\"\n+\n+);\n+\n+static void convert_serdes_mux(int type, int need_reset)\n+{\n+\tchar current_serdes;\n+\tstruct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);\n+\n+\tcurrent_serdes = cpld_data->serdes_mux;\n+\n+\tswitch (type) {\n+\tcase LANEB_SATA:\n+\t\tcurrent_serdes &= ~MASK_LANE_B;\n+\t\tbreak;\n+\tcase LANEB_SGMII1:\n+\t\tcurrent_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);\n+\t\tbreak;\n+\tcase LANEC_SGMII1:\n+\t\tcurrent_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);\n+\t\tbreak;\n+\tcase LANED_SGMII2:\n+\t\tcurrent_serdes |= MASK_LANE_D;\n+\t\tbreak;\n+\tcase LANEC_PCIEX1:\n+\t\tcurrent_serdes |= MASK_LANE_C;\n+\t\tbreak;\n+\tcase (LANED_PCIEX2 | LANEC_PCIEX1):\n+\t\tcurrent_serdes |= MASK_LANE_C;\n+\t\tcurrent_serdes &= ~MASK_LANE_D;\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"CPLD serdes MUX: unsupported MUX type 0x%x\\n\", type);\n+\t\treturn;\n+\t}\n+\n+\tcpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;\n+\tcpld_data->serdes_mux = current_serdes;\n+\n+\tif (need_reset == 1) {\n+\t\tprintf(\"Reset board to enable configuration\\n\");\n+\t\tcpld_data->system_rst = CONFIG_RESET;\n+\t}\n+}\n+\n+void print_serdes_mux(void)\n+{\n+\tchar current_serdes;\n+\tstruct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);\n+\n+\tcurrent_serdes = cpld_data->serdes_mux;\n+\n+\tprintf(\"Serdes Lane B: \");\n+\tif ((current_serdes & MASK_LANE_B) == 0)\n+\t\tprintf(\"SATA,\\n\");\n+\telse\n+\t\tprintf(\"SGMII 1,\\n\");\n+\n+\tprintf(\"Serdes Lane C: \");\n+\tif ((current_serdes & MASK_LANE_C) == 0)\n+\t\tprintf(\"SGMII 1,\\n\");\n+\telse\n+\t\tprintf(\"PCIe,\\n\");\n+\n+\tprintf(\"Serdes Lane D: \");\n+\tif ((current_serdes & MASK_LANE_D) == 0)\n+\t\tprintf(\"PCIe,\\n\");\n+\telse\n+\t\tprintf(\"SGMII 2,\\n\");\n+\n+\tprintf(\"SGMII 1 is on lane \");\n+\tif ((current_serdes & MASK_SGMII) == 0)\n+\t\tprintf(\"C.\\n\");\n+\telse\n+\t\tprintf(\"B.\\n\");\n+}\n+\n+static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,\n+\t\t\t char * const argv[])\n+{\n+\tif (argc != 2)\n+\t\treturn CMD_RET_USAGE;\n+\tif (strcmp(argv[1], \"sata\") == 0) {\n+\t\tprintf(\"Set serdes lane B to SATA.\\n\");\n+\t\tconvert_serdes_mux(LANEB_SATA, NEED_RESET);\n+\t} else if (strcmp(argv[1], \"sgmii1b\") == 0) {\n+\t\tprintf(\"Set serdes lane B to SGMII 1.\\n\");\n+\t\tconvert_serdes_mux(LANEB_SGMII1, NEED_RESET);\n+\t} else if (strcmp(argv[1], \"sgmii1c\") == 0) {\n+\t\tprintf(\"Set serdes lane C to SGMII 1.\\n\");\n+\t\tconvert_serdes_mux(LANEC_SGMII1, NEED_RESET);\n+\t} else if (strcmp(argv[1], \"sgmii2\") == 0) {\n+\t\tprintf(\"Set serdes lane D to SGMII 2.\\n\");\n+\t\tconvert_serdes_mux(LANED_SGMII2, NEED_RESET);\n+\t} else if (strcmp(argv[1], \"pciex1\") == 0) {\n+\t\tprintf(\"Set serdes lane C to PCIe X1.\\n\");\n+\t\tconvert_serdes_mux(LANEC_PCIEX1, NEED_RESET);\n+\t} else if (strcmp(argv[1], \"pciex2\") == 0) {\n+\t\tprintf(\"Set serdes lane C & lane D to PCIe X2.\\n\");\n+\t\tconvert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);\n+\t} else if (strcmp(argv[1], \"show\") == 0) {\n+\t\tprint_serdes_mux();\n+\t} else {\n+\t\treturn CMD_RET_USAGE;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+U_BOOT_CMD(\n+\tlane_bank, 2, 0, serdes_mux_cmd,\n+\t\"Multiplexed function setting for SerDes Lanes\",\n+\t\"sata\\n\"\n+\t\"\t-change lane B to sata\\n\"\n+\t\"lane_bank sgmii1b\\n\"\n+\t\"\t-change lane B to SGMII1\\n\"\n+\t\"lane_bank sgmii1c\\n\"\n+\t\"\t-change lane C to SGMII1\\n\"\n+\t\"lane_bank sgmii2\\n\"\n+\t\"\t-change lane D to SGMII2\\n\"\n+\t\"lane_bank pciex1\\n\"\n+\t\"\t-change lane C to PCIeX1\\n\"\n+\t\"lane_bank pciex2\\n\"\n+\t\"\t-change lane C & lane D to PCIeX2\\n\"\n+\t\"\\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\\n\"\n+);\ndiff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig\nnew file mode 100644\nindex 0000000..5f465d3\n--- /dev/null\n+++ b/configs/ls1021atwr_nor_defconfig\n@@ -0,0 +1,2 @@\n+CONFIG_ARM=y\n+CONFIG_TARGET_LS1021ATWR=y\ndiff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h\nnew file mode 100644\nindex 0000000..f8cbe32\n--- /dev/null\n+++ b/include/configs/ls1021atwr.h\n@@ -0,0 +1,284 @@\n+/*\n+ * Copyright 2014 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#include <config_cmd_default.h>\n+\n+#define CONFIG_LS102xA\n+\n+#define CONFIG_SYS_GENERIC_BOARD\n+\n+#define CONFIG_DISPLAY_CPUINFO\n+#define CONFIG_DISPLAY_BOARDINFO\n+\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_BOARD_EARLY_INIT_F\n+\n+/*\n+ * Size of malloc() pool\n+ */\n+#define CONFIG_SYS_MALLOC_LEN\t\t(CONFIG_ENV_SIZE + 16 * 1024 * 1024)\n+\n+#define OCRAM_BASE_ADDR\t\t\t0x10000000\n+#define OCRAM_SIZE\t\t\t0x00020000\n+\n+#define CONFIG_SYS_INIT_RAM_ADDR\tOCRAM_BASE_ADDR\n+#define CONFIG_SYS_INIT_RAM_SIZE\tOCRAM_SIZE\n+\n+/*\n+ * Generic Timer Definitions\n+ */\n+#define GENERIC_TIMER_CLK\t\t12500000\n+\n+#ifndef __ASSEMBLY__\n+unsigned long get_board_sys_clk(void);\n+unsigned long get_board_ddr_clk(void);\n+#endif\n+\n+#define CONFIG_SYS_CLK_FREQ\t\t100000000\n+#define CONFIG_DDR_CLK_FREQ\t\t100000000\n+\n+#ifndef CONFIG_SYS_TEXT_BASE\n+#define CONFIG_SYS_TEXT_BASE\t\t0x67f80000\n+#endif\n+\n+#define CONFIG_NR_DRAM_BANKS\t\t1\n+#define PHYS_SDRAM\t\t\t0x80000000\n+#define PHYS_SDRAM_SIZE\t\t\t(1u * 1024 * 1024 * 1024)\n+\n+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL\n+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE\n+\n+#define CONFIG_SYS_HAS_SERDES\n+\n+/*\n+ * IFC Definitions\n+ */\n+#define CONFIG_FSL_IFC\n+#define CONFIG_SYS_FLASH_BASE\t\t0x60000000\n+#define CONFIG_SYS_FLASH_BASE_PHYS\tCONFIG_SYS_FLASH_BASE\n+\n+#define CONFIG_SYS_NOR0_CSPR_EXT\t(0x0)\n+#define CONFIG_SYS_NOR0_CSPR\t(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \\\n+\t\t\t\tCSPR_PORT_SIZE_16 | \\\n+\t\t\t\tCSPR_MSEL_NOR | \\\n+\t\t\t\tCSPR_V)\n+#define CONFIG_SYS_NOR_AMASK\t\tIFC_AMASK(128 * 1024 * 1024)\n+\n+/* NOR Flash Timing Params */\n+#define CONFIG_SYS_NOR_CSOR\t\t(CSOR_NOR_ADM_SHIFT(4) | \\\n+\t\t\t\t\tCSOR_NOR_TRHZ_80)\n+#define CONFIG_SYS_NOR_FTIM0\t\t(FTIM0_NOR_TACSE(0x4) | \\\n+\t\t\t\t\tFTIM0_NOR_TEADC(0x5) | \\\n+\t\t\t\t\tFTIM0_NOR_TAVDS(0x0) | \\\n+\t\t\t\t\tFTIM0_NOR_TEAHC(0x5))\n+#define CONFIG_SYS_NOR_FTIM1\t\t(FTIM1_NOR_TACO(0x35) | \\\n+\t\t\t\t\tFTIM1_NOR_TRAD_NOR(0x1A) | \\\n+\t\t\t\t\tFTIM1_NOR_TSEQRAD_NOR(0x13))\n+#define CONFIG_SYS_NOR_FTIM2\t\t(FTIM2_NOR_TCS(0x4) | \\\n+\t\t\t\t\tFTIM2_NOR_TCH(0x4) | \\\n+\t\t\t\t\tFTIM2_NOR_TWP(0x1c) | \\\n+\t\t\t\t\tFTIM2_NOR_TWPH(0x0e))\n+#define CONFIG_SYS_NOR_FTIM3\t\t0\n+\n+#define CONFIG_FLASH_CFI_DRIVER\n+#define CONFIG_SYS_FLASH_CFI\n+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE\n+#define CONFIG_SYS_FLASH_QUIET_TEST\n+#define CONFIG_FLASH_SHOW_PROGRESS\t45\t/* count down from 45/5: 9..1 */\n+\n+#define CONFIG_SYS_MAX_FLASH_BANKS\t1\t/* number of banks */\n+#define CONFIG_SYS_MAX_FLASH_SECT\t1024\t/* sectors per device */\n+#define CONFIG_SYS_FLASH_ERASE_TOUT\t60000\t/* Flash Erase Timeout (ms) */\n+#define CONFIG_SYS_FLASH_WRITE_TOUT\t500\t/* Flash Write Timeout (ms) */\n+\n+#define CONFIG_SYS_FLASH_EMPTY_INFO\n+#define CONFIG_SYS_FLASH_BANKS_LIST\t{ CONFIG_SYS_FLASH_BASE_PHYS }\n+\n+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS\n+\n+/* CPLD */\n+\n+#define CONFIG_SYS_CPLD_BASE\t0x7fb00000\n+#define CPLD_BASE_PHYS\t\tCONFIG_SYS_CPLD_BASE\n+\n+#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)\n+#define CONFIG_SYS_FPGA_CSPR\t\t(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \\\n+\t\t\t\t\tCSPR_PORT_SIZE_8 | \\\n+\t\t\t\t\tCSPR_MSEL_GPCM | \\\n+\t\t\t\t\tCSPR_V)\n+#define CONFIG_SYS_FPGA_AMASK\t\tIFC_AMASK(64 * 1024)\n+#define CONFIG_SYS_FPGA_CSOR\t\t(CSOR_NOR_ADM_SHIFT(4) | \\\n+\t\t\t\t\tCSOR_NOR_NOR_MODE_AVD_NOR | \\\n+\t\t\t\t\tCSOR_NOR_TRHZ_80)\n+\n+/* CPLD Timing parameters for IFC GPCM */\n+#define CONFIG_SYS_FPGA_FTIM0\t\t(FTIM0_GPCM_TACSE(0xf) | \\\n+\t\t\t\t\tFTIM0_GPCM_TEADC(0xf) | \\\n+\t\t\t\t\tFTIM0_GPCM_TEAHC(0xf))\n+#define CONFIG_SYS_FPGA_FTIM1\t\t(FTIM1_GPCM_TACO(0xff) | \\\n+\t\t\t\t\tFTIM1_GPCM_TRAD(0x3f))\n+#define CONFIG_SYS_FPGA_FTIM2\t\t(FTIM2_GPCM_TCS(0xf) | \\\n+\t\t\t\t\tFTIM2_GPCM_TCH(0xf) | \\\n+\t\t\t\t\tFTIM2_GPCM_TWP(0xff))\n+#define CONFIG_SYS_FPGA_FTIM3 0x0\n+#define CONFIG_SYS_CSPR0_EXT\t\tCONFIG_SYS_NOR0_CSPR_EXT\n+#define CONFIG_SYS_CSPR0\t\tCONFIG_SYS_NOR0_CSPR\n+#define CONFIG_SYS_AMASK0\t\tCONFIG_SYS_NOR_AMASK\n+#define CONFIG_SYS_CSOR0\t\tCONFIG_SYS_NOR_CSOR\n+#define CONFIG_SYS_CS0_FTIM0\t\tCONFIG_SYS_NOR_FTIM0\n+#define CONFIG_SYS_CS0_FTIM1\t\tCONFIG_SYS_NOR_FTIM1\n+#define CONFIG_SYS_CS0_FTIM2\t\tCONFIG_SYS_NOR_FTIM2\n+#define CONFIG_SYS_CS0_FTIM3\t\tCONFIG_SYS_NOR_FTIM3\n+#define CONFIG_SYS_CSPR1_EXT\t\tCONFIG_SYS_FPGA_CSPR_EXT\n+#define CONFIG_SYS_CSPR1\t\tCONFIG_SYS_FPGA_CSPR\n+#define CONFIG_SYS_AMASK1\t\tCONFIG_SYS_FPGA_AMASK\n+#define CONFIG_SYS_CSOR1\t\tCONFIG_SYS_FPGA_CSOR\n+#define CONFIG_SYS_CS1_FTIM0\t\tCONFIG_SYS_FPGA_FTIM0\n+#define CONFIG_SYS_CS1_FTIM1\t\tCONFIG_SYS_FPGA_FTIM1\n+#define CONFIG_SYS_CS1_FTIM2\t\tCONFIG_SYS_FPGA_FTIM2\n+#define CONFIG_SYS_CS1_FTIM3\t\tCONFIG_SYS_FPGA_FTIM3\n+\n+/*\n+ * Serial Port\n+ */\n+#define CONFIG_CONS_INDEX\t\t1\n+#define CONFIG_SYS_NS16550\n+#define CONFIG_SYS_NS16550_SERIAL\n+#define CONFIG_SYS_NS16550_REG_SIZE\t1\n+#define CONFIG_SYS_NS16550_CLK\t\tget_serial_clock()\n+\n+#define CONFIG_BAUDRATE\t\t\t115200\n+\n+/*\n+ * I2C\n+ */\n+#define CONFIG_CMD_I2C\n+#define CONFIG_SYS_I2C\n+#define CONFIG_SYS_I2C_MXC\n+\n+/*\n+ * I2C bus multiplexer\n+ */\n+#define I2C_MUX_PCA_ADDR_PRI\t\t0x77\n+#define I2C_MUX_CH_DEFAULT\t\t0x8\n+\n+/*\n+ * MMC\n+ */\n+#define CONFIG_MMC\n+#define CONFIG_CMD_MMC\n+#define CONFIG_FSL_ESDHC\n+#define CONFIG_GENERIC_MMC\n+\n+/*\n+ * eTSEC\n+ */\n+#define CONFIG_TSEC_ENET\n+\n+#ifdef CONFIG_TSEC_ENET\n+#define CONFIG_MII\n+#define CONFIG_MII_DEFAULT_TSEC\t\t1\n+#define CONFIG_TSEC1\t\t\t1\n+#define CONFIG_TSEC1_NAME\t\t\"eTSEC1\"\n+#define CONFIG_TSEC2\t\t\t1\n+#define CONFIG_TSEC2_NAME\t\t\"eTSEC2\"\n+#define CONFIG_TSEC3\t\t\t1\n+#define CONFIG_TSEC3_NAME\t\t\"eTSEC3\"\n+\n+#define TSEC1_PHY_ADDR\t\t\t2\n+#define TSEC2_PHY_ADDR\t\t\t0\n+#define TSEC3_PHY_ADDR\t\t\t1\n+\n+#define TSEC1_FLAGS\t\t\t(TSEC_GIGABIT | TSEC_REDUCED)\n+#define TSEC2_FLAGS\t\t\t(TSEC_GIGABIT | TSEC_REDUCED)\n+#define TSEC3_FLAGS\t\t\t(TSEC_GIGABIT | TSEC_REDUCED)\n+\n+#define TSEC1_PHYIDX\t\t\t0\n+#define TSEC2_PHYIDX\t\t\t0\n+#define TSEC3_PHYIDX\t\t\t0\n+\n+#define CONFIG_ETHPRIME\t\t\t\"eTSEC1\"\n+\n+#define CONFIG_PHY_GIGE\n+#define CONFIG_PHYLIB\n+#define CONFIG_PHY_ATHEROS\n+\n+#define CONFIG_HAS_ETH0\n+#define CONFIG_HAS_ETH1\n+#define CONFIG_HAS_ETH2\n+#endif\n+\n+#define CONFIG_CMD_PING\n+#define CONFIG_CMD_DHCP\n+#define CONFIG_CMD_MII\n+#define CONFIG_CMD_NET\n+\n+#define CONFIG_CMDLINE_TAG\n+#define CONFIG_CMDLINE_EDITING\n+#undef CONFIG_CMD_IMLS\n+\n+#define CONFIG_HWCONFIG\n+#define HWCONFIG_BUFFER_SIZE\t\t128\n+\n+#define CONFIG_BOOTDELAY\t\t3\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\t\"bootargs=root=/dev/ram0 rw console=ttyS0,115200\\0\" \\\n+\t\"initrd_high=0xcfffffff\\0\" \\\n+\t\"fdt_high=0xcfffffff\\0\"\n+\n+/*\n+ * Miscellaneous configurable options\n+ */\n+#define CONFIG_SYS_LONGHELP\t\t/* undef to save memory */\n+#define CONFIG_SYS_HUSH_PARSER\t\t/* use \"hush\" command parser */\n+#define CONFIG_SYS_PROMPT_HUSH_PS2\t\"> \"\n+#define CONFIG_SYS_PROMPT\t\t\"=> \"\n+#define CONFIG_AUTO_COMPLETE\n+#define CONFIG_SYS_CBSIZE\t\t256\t/* Console I/O Buffer Size */\n+#define CONFIG_SYS_PBSIZE\t\t\\\n+\t\t(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)\n+#define CONFIG_SYS_MAXARGS\t\t16\t/* max number of command args */\n+#define CONFIG_SYS_BARGSIZE\t\tCONFIG_SYS_CBSIZE\n+\n+#define CONFIG_CMD_MEMTEST\n+#define CONFIG_SYS_MEMTEST_START\t0x80000000\n+#define CONFIG_SYS_MEMTEST_END\t\t0x9fffffff\n+\n+#define CONFIG_SYS_LOAD_ADDR\t\t0x82000000\n+#define CONFIG_SYS_HZ\t\t\t1000\n+\n+/*\n+ * Stack sizes\n+ * The stack sizes are set up in start.S using the settings below\n+ */\n+#define CONFIG_STACKSIZE\t\t(30 * 1024)\n+\n+#define CONFIG_SYS_INIT_SP_OFFSET \\\n+\t(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)\n+#define CONFIG_SYS_INIT_SP_ADDR \\\n+\t(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)\n+\n+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */\n+\n+/*\n+ * Environment\n+ */\n+#define CONFIG_ENV_OVERWRITE\n+\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_ADDR\t\t(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)\n+#define CONFIG_ENV_SIZE\t\t\t0x20000\n+#define CONFIG_ENV_SECT_SIZE\t\t0x20000 /* 128K (one sector) */\n+\n+#define CONFIG_OF_LIBFDT\n+#define CONFIG_OF_BOARD_SETUP\n+#define CONFIG_CMD_BOOTZ\n+\n+#endif\n", "prefixes": [ "U-Boot", "v3", "12/18" ] }