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GET /api/patches/368963/?format=api
{ "id": 368963, "url": "http://patchwork.ozlabs.org/api/patches/368963/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1405054046-19791-3-git-send-email-b18965@freescale.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1405054046-19791-3-git-send-email-b18965@freescale.com>", "list_archive_url": null, "date": "2014-07-11T04:47:26", "name": "[U-Boot,2/2] arm: ls102xa: Add SD boot support for LS1021ATWR board", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "7b2a2890e3219b202b5ed5ba431abcedf8717e27", "submitter": { "id": 13010, "url": "http://patchwork.ozlabs.org/api/people/13010/?format=api", "name": "Alison Wang", "email": "b18965@freescale.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1405054046-19791-3-git-send-email-b18965@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/368963/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/368963/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 7E988140085\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 11 Jul 2014 15:34:18 +1000 (EST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id A430CA79CA;\n\tFri, 11 Jul 2014 07:34:09 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id ksw1tFGnvnbU; Fri, 11 Jul 2014 07:34:09 +0200 (CEST)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 1B122A79CC;\n\tFri, 11 Jul 2014 07:34:02 +0200 (CEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 1F8B2A746E\n\tfor <u-boot@lists.denx.de>; Fri, 11 Jul 2014 07:33:56 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id D8ZmFAL6OBpk for <u-boot@lists.denx.de>;\n\tFri, 11 Jul 2014 07:33:52 +0200 (CEST)", "from na01-bn1-obe.outbound.protection.outlook.com\n\t(mail-bn1blp0187.outbound.protection.outlook.com [207.46.163.187])\n\tby theia.denx.de (Postfix) with ESMTPS id E8EADA79BF\n\tfor <u-boot@lists.denx.de>; Fri, 11 Jul 2014 07:33:51 +0200 (CEST)", "from BN1PR0301MB0690.namprd03.prod.outlook.com (25.160.171.27) by\n\tBN1PR0301MB0628.namprd03.prod.outlook.com (25.160.171.13) with\n\tMicrosoft SMTP\n\tServer (TLS) id 15.0.974.11; Fri, 11 Jul 2014 05:33:45 +0000", "from CH1PR03CA011.namprd03.prod.outlook.com (10.255.156.156) by\n\tBN1PR0301MB0690.namprd03.prod.outlook.com (25.160.171.27) with\n\tMicrosoft SMTP\n\tServer (TLS) id 15.0.985.8; Fri, 11 Jul 2014 05:33:43 +0000", "from BN1BFFO11FD007.protection.gbl (10.255.156.132) by\n\tCH1PR03CA011.outlook.office365.com (10.255.156.156) with Microsoft\n\tSMTP Server (TLS) id 15.0.985.8 via Frontend Transport;\n\tFri, 11 Jul 2014 05:33:42 +0000", "from az84smr01.freescale.net (192.88.158.2) by\n\tBN1BFFO11FD007.mail.protection.outlook.com (10.58.144.70) with\n\tMicrosoft SMTP Server (TLS) id 15.0.980.11 via Frontend Transport;\n\tFri, 11 Jul 2014 05:33:42 +0000", "from rock.ap.freescale.net (rock.ap.freescale.net [10.193.20.106])\n\tby az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id\n\ts6B5XVgY028996; Thu, 10 Jul 2014 22:33:39 -0700" ], "X-Virus-Scanned": [ "Debian amavisd-new at theia.denx.de", "Debian amavisd-new at theia.denx.de" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Alison Wang <b18965@freescale.com>", "To": "<albert.u.boot@aribaud.net>, <u-boot@lists.denx.de>", "Date": "Fri, 11 Jul 2014 12:47:26 +0800", "Message-ID": "<1405054046-19791-3-git-send-email-b18965@freescale.com>", "X-Mailer": "git-send-email 1.8.0", "In-Reply-To": "<1405054046-19791-1-git-send-email-b18965@freescale.com>", "References": "<1405054046-19791-1-git-send-email-b18965@freescale.com>", "X-EOPAttributedMessage": "0", "X-Forefront-Antispam-Report": "CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI;\n\tEFV:NLI; SFV:NSPM;\n\tSFS:(6009001)(199002)(189002)(106466001)(64706001)(74502001)(20776003)(92566001)(47776003)(74662001)(31966008)(107046002)(95666004)(33646001)(81156004)(62966002)(229853001)(92726001)(21056001)(85306003)(6806004)(104016003)(83322001)(19580395003)(97736001)(88136002)(83072002)(105606002)(50986999)(81542001)(575784001)(81342001)(89996001)(93916002)(50466002)(85852003)(87286001)(84676001)(87936001)(44976005)(69596002)(68736004)(99396002)(77982001)(50226001)(19580405001)(46102001)(4396001)(36756003)(77156001)(80022001)(76482001)(76176999)(79102001)(102836001)(48376002)(104166001)(26826002)(42262001);\n\tDIR:OUT; SFP:; SCL:1; SRVR:BN1PR0301MB0690;\n\tH:az84smr01.freescale.net; FPR:; MLV:ovrnspm;\n\tPTR:InfoDomainNonexistent; MX:1; LANG:en; ", "MIME-Version": "1.0", "X-Microsoft-Antispam": [ "BCL:0;PCL:0;RULEID:", "BCL:0;PCL:0;RULEID:" ], "X-Forefront-PRVS": "02698DF457", "Received-SPF": "Fail (: domain of freescale.com does not designate 192.88.158.2\n\tas permitted sender) receiver=; client-ip=192.88.158.2;\n\thelo=az84smr01.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=alison.wang@freescale.com; ", "X-OriginatorOrg": "freescale.com", "Cc": "fabio.estevam@freescale.com, yorksun@freescale.com,\n\tAlison Wang <alison.wang@freescale.com>", "Subject": "[U-Boot] [PATCH 2/2] arm: ls102xa: Add SD boot support for\n\tLS1021ATWR board", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.11", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "This patch adds SD boot support for LS1021ATWR board. SPL\nframework is used. PBL initialize the internal RAM and copy\nSPL to it, then SPL initialize DDR using SPD and copy u-boot\nfrom SD card to DDR, finally SPL transfer control to u-boot.\n\nSigned-off-by: Alison Wang <alison.wang@freescale.com>\nSigned-off-by: Jason Jin <jason.jin@freescale.com>\n---\n board/freescale/ls1021atwr/ls1021atwr.c | 31 ++++++++++++++++-\n board/freescale/ls1021atwr/ls102xa_pbi.cfg | 8 +++++\n board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg | 14 ++++++++\n boards.cfg | 1 +\n include/configs/ls1021atwr.h | 49 +++++++++++++++++++++++++++\n 5 files changed, 102 insertions(+), 1 deletion(-)\n create mode 100644 board/freescale/ls1021atwr/ls102xa_pbi.cfg\n create mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg", "diff": "diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c\nindex 3de5b83..02d0d39 100644\n--- a/board/freescale/ls1021atwr/ls1021atwr.c\n+++ b/board/freescale/ls1021atwr/ls1021atwr.c\n@@ -16,6 +16,7 @@\n #include <netdev.h>\n #include <fsl_mdio.h>\n #include <tsec.h>\n+#include <spl.h>\n \n DECLARE_GLOBAL_DATA_PTR;\n \n@@ -66,6 +67,7 @@ struct cpld_data {\n \tu8 rev2;\t\t/* Reserved */\n };\n \n+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)\n static void convert_serdes_mux(int type, int need_reset);\n \n void cpld_show(void)\n@@ -103,11 +105,14 @@ void cpld_show(void)\n \t\tin_8(&cpld_data->serdes_mux));\n #endif\n }\n+#endif\n \n int checkboard(void)\n {\n \tputs(\"Board: LS1021ATWR\\n\");\n+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)\n \tcpld_show();\n+#endif\n \n \treturn 0;\n }\n@@ -218,6 +223,7 @@ int board_eth_init(bd_t *bis)\n }\n #endif\n \n+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)\n int config_serdes_mux(void)\n {\n \tstruct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\n@@ -249,6 +255,7 @@ int config_serdes_mux(void)\n \n \treturn 0;\n }\n+#endif\n \n int board_early_init_f(void)\n {\n@@ -273,6 +280,25 @@ int board_early_init_f(void)\n \treturn 0;\n }\n \n+#ifdef CONFIG_SPL_BUILD\n+void board_init_f(ulong dummy)\n+{\n+\t/* Set global data pointer */\n+\tgd = &gdata;\n+\n+\t/* Clear the BSS */\n+\tmemset(__bss_start, 0, __bss_end - __bss_start);\n+\n+\tget_clocks();\n+\n+\tpreloader_console_init();\n+\n+\tdram_init();\n+\n+\tboard_init_r(NULL, 0);\n+}\n+#endif\n+\n int board_init(void)\n {\n \tstruct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;\n@@ -284,9 +310,10 @@ int board_init(void)\n \n #ifndef CONFIG_SYS_FSL_NO_SERDES\n \tfsl_serdes_init();\n+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)\n \tconfig_serdes_mux();\n #endif\n-\n+#endif\n \treturn 0;\n }\n \n@@ -312,6 +339,7 @@ u16 flash_read16(void *addr)\n \treturn (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);\n }\n \n+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)\n static void convert_flash_bank(char bank)\n {\n \tstruct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);\n@@ -497,3 +525,4 @@ U_BOOT_CMD(\n \t\"\t-change lane C & lane D to PCIeX2\\n\"\n \t\"\\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\\n\"\n );\n+#endif\ndiff --git a/board/freescale/ls1021atwr/ls102xa_pbi.cfg b/board/freescale/ls1021atwr/ls102xa_pbi.cfg\nnew file mode 100644\nindex 0000000..edf9f94\n--- /dev/null\n+++ b/board/freescale/ls1021atwr/ls102xa_pbi.cfg\n@@ -0,0 +1,8 @@\n+#PBI commands\n+\n+#Configure Scratch register\n+09ee0200 10000000\n+#Configure alternate space\n+09570158 00080000\n+#Flush PBL data\n+096100c0 000FFFFF\ndiff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg\nnew file mode 100644\nindex 0000000..05e2082\n--- /dev/null\n+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg\n@@ -0,0 +1,14 @@\n+#PBL preamble and RCW header\n+aa55aa55 01ee0100\n+\n+#enable IFC, disable QSPI and DSPI\n+#0608000a 00000000 00000000 00000000\n+#20000000 00404000 60025a00 21042000\n+#00200000 00000000 00000000 01038000\n+#00000000 001b1200 00000000 00000000\n+\n+#disable IFC, enable QSPI and DSPI\n+0608000a 00000000 00000000 00000000\n+20000000 00404000 60025a00 21042000\n+00000000 00000000 00000000 01038000\n+20024800 001b1200 00000000 00000000\ndiff --git a/boards.cfg b/boards.cfg\nindex 3e5e1d0..65c3066 100644\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -304,6 +304,7 @@ Active arm armv7 keystone ti k2hk_evm\n Active arm armv7 ls102xa freescale ls1021aqds ls1021aqds_nor ls1021aqds Alison Wang <alison.wang@freescale.com>\n Active arm armv7 ls102xa freescale ls1021aqds ls1021aqds_sdcard ls1021aqds:RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT Alison Wang <alison.wang@freescale.com>\n Active arm armv7 ls102xa freescale ls1021atwr ls1021atwr_nor ls1021atwr Alison Wang <alison.wang@freescale.com>\n+Active arm armv7 ls102xa freescale ls1021atwr ls1021atwr_sdcard ls1021atwr:RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT Alison Wang <alison.wang@freescale.com>\n Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com>\n Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg -\n Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <sbabic@denx.de>\ndiff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h\nindex 5e1f958..806d143 100644\n--- a/include/configs/ls1021atwr.h\n+++ b/include/configs/ls1021atwr.h\n@@ -43,6 +43,42 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_SYS_CLK_FREQ\t\t100000000\n #define CONFIG_DDR_CLK_FREQ\t\t100000000\n \n+#ifdef CONFIG_RAMBOOT_PBL\n+#define CONFIG_SYS_FSL_PBL_PBI\tboard/freescale/ls1021atwr/ls102xa_pbi.cfg\n+#endif\n+\n+#ifdef CONFIG_SD_BOOT\n+#define CONFIG_SYS_FSL_PBL_RCW\tboard/freescale/ls1021atwr/ls102xa_rcw_sd.cfg\n+#define CONFIG_SPL\n+#define CONFIG_SPL_PBL_PAD\n+#define CONFIG_SPL_FRAMEWORK\n+#define CONFIG_SPL_LDSCRIPT\t\"arch/arm/cpu/armv7/ls102xa/u-boot-spl.lds\"\n+#define CONFIG_SPL_LIBCOMMON_SUPPORT\n+#define CONFIG_SPL_LIBGENERIC_SUPPORT\n+#define CONFIG_SPL_ENV_SUPPORT\n+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT\n+#define CONFIG_SPL_I2C_SUPPORT\n+#define CONFIG_SPL_WATCHDOG_SUPPORT\n+#define CONFIG_SPL_SERIAL_SUPPORT\n+#define CONFIG_SPL_MMC_SUPPORT\n+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR\t\t0x78\n+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS\t\t0x400\n+\n+#define CONFIG_SPL_TEXT_BASE\t\t0x10000000\n+#define CONFIG_SPL_MAX_SIZE\t\t0xd000\n+#define CONFIG_SPL_STACK\t\t0x1000f000\n+#define CONFIG_SPL_PAD_TO\t\t0xe000\n+#define CONFIG_SYS_TEXT_BASE\t\t0x82000000\n+\n+#define CONFIG_SYS_SPL_MALLOC_START\t0x80200000\n+#define CONFIG_SYS_SPL_MALLOC_SIZE\t0x100000\n+#define CONFIG_SPL_BSS_START_ADDR\t0x80100000\n+#define CONFIG_SPL_BSS_MAX_SIZE\t\t0x80000\n+#define CONFIG_SYS_MONITOR_LEN\t\t0x80000\n+#define CONFIG_SYS_SPL_ASSUME_UBOOT_NIH\n+#define CONFIG_SYS_NO_FLASH\n+#endif\n+\n #ifndef CONFIG_SYS_TEXT_BASE\n #define CONFIG_SYS_TEXT_BASE\t\t0x67f80000\n #endif\n@@ -59,6 +95,7 @@ unsigned long get_board_ddr_clk(void);\n /*\n * IFC Definitions\n */\n+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)\n #define CONFIG_FSL_IFC\n #define CONFIG_SYS_FLASH_BASE\t\t0x60000000\n #define CONFIG_SYS_FLASH_BASE_PHYS\tCONFIG_SYS_FLASH_BASE\n@@ -102,6 +139,7 @@ unsigned long get_board_ddr_clk(void);\n \n #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS\n \n+#endif\n \n /* CPLD */\n \n@@ -266,17 +304,28 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_SYS_INIT_SP_ADDR \\\n \t(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)\n \n+#ifdef CONFIG_SPL_BUILD\n+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE\n+#else\n #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */\n+#endif\n \n /*\n * Environment\n */\n #define CONFIG_ENV_OVERWRITE\n \n+#if defined(CONFIG_SD_BOOT)\n+#define CONFIG_ENV_OFFSET\t\t(1024 * 1024)\n+#define CONFIG_ENV_IS_IN_MMC\n+#define CONFIG_SYS_MMC_ENV_DEV\t\t0\n+#define CONFIG_ENV_SIZE\t\t\t0x20000\n+#else\n #define CONFIG_ENV_IS_IN_FLASH\n #define CONFIG_ENV_ADDR\t\t\t(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)\n #define CONFIG_ENV_SIZE\t\t\t0x20000\n #define CONFIG_ENV_SECT_SIZE\t\t0x20000 /* 128K (one sector) */\n+#endif\n \n #define CONFIG_OF_LIBFDT\n #define CONFIG_OF_BOARD_SETUP\n", "prefixes": [ "U-Boot", "2/2" ] }