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GET /api/patches/366822/?format=api
{ "id": 366822, "url": "http://patchwork.ozlabs.org/api/patches/366822/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1404381072-42875-5-git-send-email-Li.Xiubo@freescale.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1404381072-42875-5-git-send-email-Li.Xiubo@freescale.com>", "list_archive_url": null, "date": "2014-07-03T09:51:12", "name": "[U-Boot,4/4] ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "37af610c41e3b45ae2f5a67fac4496509631f00b", "submitter": { "id": 44085, "url": "http://patchwork.ozlabs.org/api/people/44085/?format=api", "name": "Xiubo Li", "email": "Li.Xiubo@freescale.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1404381072-42875-5-git-send-email-Li.Xiubo@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/366822/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/366822/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 22FCE140076\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 3 Jul 2014 20:18:22 +1000 (EST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id E9FDC4B174;\n\tThu, 3 Jul 2014 12:18:07 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id P1qKxqCSfjji; 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Thu, 3 Jul 2014 02:55:07 -0700" ], "X-Virus-Scanned": [ "Debian amavisd-new at theia.denx.de", "Debian amavisd-new at theia.denx.de" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Xiubo Li <Li.Xiubo@freescale.com>", "To": "<albert.u.boot@aribaud.net>, <u-boot@lists.denx.de>", "Date": "Thu, 3 Jul 2014 17:51:12 +0800", "Message-ID": "<1404381072-42875-5-git-send-email-Li.Xiubo@freescale.com>", "X-Mailer": "git-send-email 1.8.5", "In-Reply-To": "<1404381072-42875-1-git-send-email-Li.Xiubo@freescale.com>", "References": "<1404381072-42875-1-git-send-email-Li.Xiubo@freescale.com>", "X-EOPAttributedMessage": "0", "X-Forefront-Antispam-Report": "CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI;\n\tEFV:NLI; SFV:NSPM; \n\tSFS:(6009001)(199002)(189002)(6806004)(21056001)(106466001)(81156004)(107046002)(99396002)(36756003)(46102001)(44976005)(77156001)(87936001)(50466002)(48376002)(105606002)(87286001)(50986999)(104166001)(83072002)(64706001)(76176999)(19580405001)(89996001)(47776003)(20776003)(85852003)(19580395003)(68736004)(83322001)(69596002)(88136002)(104016002)(80022001)(50226001)(97736001)(92566001)(77982001)(81542001)(76482001)(81342001)(102836001)(31966008)(84676001)(74502001)(79102001)(229853001)(26826002)(95666004)(86362001)(92726001)(4396001)(93916002)(62966002)(74662001)(85306003);\n\tDIR:OUT; SFP:; SCL:1; SRVR:BLUPR03MB566;\n\tH:az84smr01.freescale.net; FPR:; MLV:ovrnspm;\n\tPTR:InfoDomainNonexistent; MX:1; LANG:; ", "MIME-Version": "1.0", "X-Microsoft-Antispam": "BL:0; ACTION:Default; RISK:Low; SCL:0; SPMLVL:NotSpam; \n\tPCL:0; RULEID:", "X-Forefront-PRVS": "0261CCEEDF", "Received-SPF": "Fail (: domain of freescale.com does not designate 192.88.158.2\n\tas permitted sender) receiver=; client-ip=192.88.158.2;\n\thelo=az84smr01.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=Li.Xiubo@freescale.com; ", "X-OriginatorOrg": "freescale.com", "X-Mailman-Approved-At": "Thu, 03 Jul 2014 12:17:23 +0200", "Cc": "R64188@freescale.com, b44548@freescale.com, marc.zyngier@arm.com,\n\tb46683@freescale.com, b35083@freescale.com,\n\tXiubo Li <Li.Xiubo@freescale.com>, b47053@freescale.com", "Subject": "[U-Boot] [PATCH 4/4] ARM: LS1021A: to allow non-secure R/W access\n\tfor all devices' mapped region", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.11", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>\n---\n arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +++++++++++++++++--\n board/freescale/ls1021aqds/ls1021aqds.c | 110 +++++++++++++++++++--\n board/freescale/ls1021atwr/ls1021atwr.c | 111 ++++++++++++++++++++--\n 3 files changed, 298 insertions(+), 21 deletions(-)", "diff": "diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\nindex 192d389..b959bf5 100644\n--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n@@ -34,14 +34,98 @@\n #define FSL_LS102xA_DEVDISR3_PCIE1 0x80000000\n #define FSL_LS102xA_DEVDISR3_PCIE2 0x40000000\n \n-/* CSU CSL2 register offset */\n-#define CSU_CSL2_IFC_REG_OFFSET\t\t0x4\n-/* Mask of Non secure read/write access in CSU_CL registers */\n-#define CSU_CSL2x_NS_SUP_WRITE_ACCESS\t0x00000080\n-#define CSU_CSL2x_NS_USER_WRITE_ACCESS\t0x00000040\t\n-#define CSU_CSL2x_NS_SUP_READ_ACCESS\t0x00000008\n-#define CSU_CSL2x_NS_USER_READ_ACCESS\t0x00000004\n+enum csu_cslx_access {\n+\tCSU_NS_SUP_R = 0x08,\n+\tCSU_NS_SUP_W = 0x80,\n+\tCSU_NS_SUP_RW = 0x88,\n+\tCSU_NS_USER_R = 0x04,\n+\tCSU_NS_USER_W = 0x40,\n+\tCSU_NS_USER_RW = 0x44,\n+};\n \n+enum csu_cslx_ind {\n+\tCSU_CSLX_PCIE2_IO = 0,\n+\tCSU_CSLX_PCIE1_IO,\n+\tCSU_CSLX_MG2TPR_IP,\n+\tCSU_CSLX_IFC_MEM,\n+\tCSU_CSLX_OCRAM,\n+\tCSU_CSLX_GIC,\n+\tCSU_CSLX_PCIE1,\n+\tCSU_CSLX_OCRAM2,\n+\tCSU_CSLX_QSPI_MEM,\n+\tCSU_CSLX_PCIE2,\n+\tCSU_CSLX_SATA,\n+\tCSU_CSLX_USB3,\n+\tCSU_CSLX_SERDES = 32,\n+\tCSU_CSLX_QDMA,\n+\tCSU_CSLX_LPUART2,\n+\tCSU_CSLX_LPUART1,\n+\tCSU_CSLX_LPUART4,\n+\tCSU_CSLX_LPUART3,\n+\tCSU_CSLX_LPUART6,\n+\tCSU_CSLX_LPUART5,\n+\tCSU_CSLX_DSPI2 = 40,\n+\tCSU_CSLX_DSPI1,\n+\tCSU_CSLX_QSPI,\n+\tCSU_CSLX_ESDHC,\n+\tCSU_CSLX_2D_ACE,\n+\tCSU_CSLX_IFC,\n+\tCSU_CSLX_I2C1,\n+\tCSU_CSLX_USB2,\n+\tCSU_CSLX_I2C3,\n+\tCSU_CSLX_I2C2,\n+\tCSU_CSLX_DUART2 = 50,\n+\tCSU_CSLX_DUART1,\n+\tCSU_CSLX_WDT2,\n+\tCSU_CSLX_WDT1,\n+\tCSU_CSLX_EDMA,\n+\tCSU_CSLX_SYS_CNT,\n+\tCSU_CSLX_DMA_MUX2,\n+\tCSU_CSLX_DMA_MUX1,\n+\tCSU_CSLX_DDR,\n+\tCSU_CSLX_QUICC,\n+\tCSU_CSLX_DCFG_CCU_RCPM = 60,\n+\tCSU_CSLX_SECURE_BOOTROM,\n+\tCSU_CSLX_SFP,\n+\tCSU_CSLX_TMU,\n+\tCSU_CSLX_SECURE_MONITOR,\n+\tCSU_CSLX_RESERVED0,\n+\tCSU_CSLX_ETSEC1,\n+\tCSU_CSLX_SEC5_5,\n+\tCSU_CSLX_ETSEC3,\n+\tCSU_CSLX_ETSEC2,\n+\tCSU_CSLX_GPIO2 = 70,\n+\tCSU_CSLX_GPIO1,\n+\tCSU_CSLX_GPIO4,\n+\tCSU_CSLX_GPIO3,\n+\tCSU_CSLX_PLATFORM_CONT,\n+\tCSU_CSLX_CSU,\n+\tCSU_CSLX_ASRC,\n+\tCSU_CSLX_SPDIF,\n+\tCSU_CSLX_FLEXCAN2,\n+\tCSU_CSLX_FLEXCAN1,\n+\tCSU_CSLX_FLEXCAN4 = 80,\n+\tCSU_CSLX_FLEXCAN3,\n+\tCSU_CSLX_SAI2,\n+\tCSU_CSLX_SAI1,\n+\tCSU_CSLX_SAI4,\n+\tCSU_CSLX_SAI3,\n+\tCSU_CSLX_FTM2,\n+\tCSU_CSLX_FTM1,\n+\tCSU_CSLX_FTM4,\n+\tCSU_CSLX_FTM3,\n+\tCSU_CSLX_FTM6 = 90,\n+\tCSU_CSLX_FTM5,\n+\tCSU_CSLX_FTM8,\n+\tCSU_CSLX_FTM7,\n+\tCSU_CSLX_COP_DCSR,\n+\tCSU_CSLX_EPU,\n+\tCSU_CSLX_GDI,\n+\tCSU_CSLX_DDI,\n+\tCSU_CSLX_RESERVED1,\n+\tCSU_CSLX_USB3_PHY = 117,\n+\tCSU_CSLX_RESERVED2,\n+};\n /*\n * Define default values for some CCSR macros to make header files cleaner*\n *\ndiff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c\nindex fe00421..7444e06 100644\n--- a/board/freescale/ls1021aqds/ls1021aqds.c\n+++ b/board/freescale/ls1021aqds/ls1021aqds.c\n@@ -377,15 +377,111 @@ int board_init(void)\n \treturn 0;\n }\n \n+struct csu_ns_dev {\n+\tunsigned long ind;\n+\tuint32_t val;\n+};\n \n-void enable_ifc_ns_read_access(void)\n+struct csu_ns_dev ns_dev[] =\n {\n-\tuint32_t *csu_csl2 = CONFIG_SYS_FSL_CSU_ADDR + CSU_CSL2_IFC_REG_OFFSET;\n-\tuint32_t reg; \n+\tCSU_CSLX_PCIE2_IO, CSU_NS_SUP_RW,\n+\tCSU_CSLX_PCIE1_IO, CSU_NS_SUP_RW,\n+\tCSU_CSLX_MG2TPR_IP, CSU_NS_SUP_RW,\n+\tCSU_CSLX_IFC_MEM, CSU_NS_SUP_R | CSU_NS_USER_R,\n+\tCSU_CSLX_OCRAM, CSU_NS_SUP_RW,\n+\tCSU_CSLX_GIC, CSU_NS_SUP_RW,\n+\tCSU_CSLX_PCIE1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_OCRAM2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_QSPI_MEM, CSU_NS_SUP_RW,\n+\tCSU_CSLX_PCIE2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SATA, CSU_NS_SUP_RW,\n+\tCSU_CSLX_USB3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SERDES, CSU_NS_SUP_RW,\n+\tCSU_CSLX_QDMA, CSU_NS_SUP_RW,\n+\tCSU_CSLX_LPUART2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_LPUART1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_LPUART4, CSU_NS_SUP_RW,\n+\tCSU_CSLX_LPUART3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_LPUART6, CSU_NS_SUP_RW,\n+\tCSU_CSLX_LPUART5, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DSPI2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DSPI1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_QSPI, CSU_NS_SUP_RW,\n+\tCSU_CSLX_ESDHC, CSU_NS_SUP_RW,\n+\tCSU_CSLX_2D_ACE, CSU_NS_SUP_RW,\n+\tCSU_CSLX_IFC, CSU_NS_SUP_RW,\n+\tCSU_CSLX_I2C1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_USB2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_I2C3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_I2C2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DUART2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DUART1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_WDT2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_WDT1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_EDMA, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SYS_CNT, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DMA_MUX2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DMA_MUX1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DDR, CSU_NS_SUP_RW,\n+\tCSU_CSLX_QUICC, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DCFG_CCU_RCPM, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SECURE_BOOTROM, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SFP, CSU_NS_SUP_RW,\n+\tCSU_CSLX_TMU, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SECURE_MONITOR, CSU_NS_SUP_RW,\n+\tCSU_CSLX_RESERVED0, CSU_NS_SUP_RW,\n+\tCSU_CSLX_ETSEC1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SEC5_5, CSU_NS_SUP_RW,\n+\tCSU_CSLX_ETSEC3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_ETSEC2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_GPIO2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_GPIO1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_GPIO4, CSU_NS_SUP_RW,\n+\tCSU_CSLX_GPIO3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_PLATFORM_CONT, CSU_NS_SUP_RW,\n+\tCSU_CSLX_CSU, CSU_NS_SUP_RW,\n+\tCSU_CSLX_ASRC, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SPDIF, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FLEXCAN2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FLEXCAN1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FLEXCAN4, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FLEXCAN3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SAI2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SAI1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SAI4, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SAI3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM4, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM6, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM5, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM8, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM7, CSU_NS_SUP_RW,\n+\tCSU_CSLX_COP_DCSR, CSU_NS_SUP_RW,\n+\tCSU_CSLX_EPU, CSU_NS_SUP_RW,\n+\tCSU_CSLX_GDI, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DDI, CSU_NS_SUP_RW,\n+\tCSU_CSLX_RESERVED1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_USB3_PHY, CSU_NS_SUP_RW,\n+\tCSU_CSLX_RESERVED2, CSU_NS_SUP_RW,\n+};\n \n-\treg = in_be32(csu_csl2);\n-\tout_be32(csu_csl2, reg | CSU_CSL2x_NS_SUP_READ_ACCESS |\n-\t\t\t CSU_CSL2x_NS_USER_READ_ACCESS);\n+void enable_devices_ns_access(void)\n+{\n+\tuint32_t *csu_csl;\n+\tuint32_t reg;\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ns_dev); i++) {\n+\t\tcsu_csl = CONFIG_SYS_FSL_CSU_ADDR + ns_dev[i].ind / 2 * 4;\n+\t\treg = in_be32(csu_csl);\n+\t\tif (ns_dev[i].ind % 2 == 0)\n+\t\t\treg |= ns_dev[i].val << 16;\n+\t\telse\n+\t\t\treg |= ns_dev[i].val;\n+\t\tout_be32(csu_csl, reg);\n+\t}\n }\n \n int board_late_init(void)\n@@ -403,7 +499,7 @@ int board_late_init(void)\n \n \tahci_init(AHCI_BASE_ADDR);\n \tscsi_scan(1);\n-\tenable_ifc_ns_read_access();\n+\tenable_devices_ns_access();\n \treturn 0;\n }\n \ndiff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c\nindex d57fa77..f75b779 100644\n--- a/board/freescale/ls1021atwr/ls1021atwr.c\n+++ b/board/freescale/ls1021atwr/ls1021atwr.c\n@@ -458,14 +458,111 @@ int board_init(void)\n \treturn 0;\n }\n \n-void enable_ifc_ns_read_access(void)\n+struct csu_ns_dev {\n+\tunsigned long ind;\n+\tuint32_t val;\n+};\n+\n+struct csu_ns_dev ns_dev[] =\n {\n-\tuint32_t *csu_csl2 = CONFIG_SYS_FSL_CSU_ADDR + CSU_CSL2_IFC_REG_OFFSET;\n-\tuint32_t reg;\n+\tCSU_CSLX_PCIE2_IO, CSU_NS_SUP_RW,\n+\tCSU_CSLX_PCIE1_IO, CSU_NS_SUP_RW,\n+\tCSU_CSLX_MG2TPR_IP, CSU_NS_SUP_RW,\n+\tCSU_CSLX_IFC_MEM, CSU_NS_SUP_R | CSU_NS_USER_R,\n+\tCSU_CSLX_OCRAM, CSU_NS_SUP_RW,\n+\tCSU_CSLX_GIC, CSU_NS_SUP_RW,\n+\tCSU_CSLX_PCIE1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_OCRAM2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_QSPI_MEM, CSU_NS_SUP_RW,\n+\tCSU_CSLX_PCIE2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SATA, CSU_NS_SUP_RW,\n+\tCSU_CSLX_USB3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SERDES, CSU_NS_SUP_RW,\n+\tCSU_CSLX_QDMA, CSU_NS_SUP_RW,\n+\tCSU_CSLX_LPUART2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_LPUART1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_LPUART4, CSU_NS_SUP_RW,\n+\tCSU_CSLX_LPUART3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_LPUART6, CSU_NS_SUP_RW,\n+\tCSU_CSLX_LPUART5, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DSPI2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DSPI1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_QSPI, CSU_NS_SUP_RW,\n+\tCSU_CSLX_ESDHC, CSU_NS_SUP_RW,\n+\tCSU_CSLX_2D_ACE, CSU_NS_SUP_RW,\n+\tCSU_CSLX_IFC, CSU_NS_SUP_RW,\n+\tCSU_CSLX_I2C1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_USB2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_I2C3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_I2C2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DUART2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DUART1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_WDT2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_WDT1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_EDMA, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SYS_CNT, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DMA_MUX2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DMA_MUX1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DDR, CSU_NS_SUP_RW,\n+\tCSU_CSLX_QUICC, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DCFG_CCU_RCPM, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SECURE_BOOTROM, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SFP, CSU_NS_SUP_RW,\n+\tCSU_CSLX_TMU, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SECURE_MONITOR, CSU_NS_SUP_RW,\n+\tCSU_CSLX_RESERVED0, CSU_NS_SUP_RW,\n+\tCSU_CSLX_ETSEC1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SEC5_5, CSU_NS_SUP_RW,\n+\tCSU_CSLX_ETSEC3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_ETSEC2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_GPIO2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_GPIO1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_GPIO4, CSU_NS_SUP_RW,\n+\tCSU_CSLX_GPIO3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_PLATFORM_CONT, CSU_NS_SUP_RW,\n+\tCSU_CSLX_CSU, CSU_NS_SUP_RW,\n+\tCSU_CSLX_ASRC, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SPDIF, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FLEXCAN2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FLEXCAN1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FLEXCAN4, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FLEXCAN3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SAI2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SAI1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SAI4, CSU_NS_SUP_RW,\n+\tCSU_CSLX_SAI3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM2, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM4, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM3, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM6, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM5, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM8, CSU_NS_SUP_RW,\n+\tCSU_CSLX_FTM7, CSU_NS_SUP_RW,\n+\tCSU_CSLX_COP_DCSR, CSU_NS_SUP_RW,\n+\tCSU_CSLX_EPU, CSU_NS_SUP_RW,\n+\tCSU_CSLX_GDI, CSU_NS_SUP_RW,\n+\tCSU_CSLX_DDI, CSU_NS_SUP_RW,\n+\tCSU_CSLX_RESERVED1, CSU_NS_SUP_RW,\n+\tCSU_CSLX_USB3_PHY, CSU_NS_SUP_RW,\n+\tCSU_CSLX_RESERVED2, CSU_NS_SUP_RW,\n+};\n \n-\treg = in_be32(csu_csl2);\n-\tout_be32(csu_csl2, reg | CSU_CSL2x_NS_SUP_READ_ACCESS |\n-\t\tCSU_CSL2x_NS_USER_READ_ACCESS);\n+void enable_devices_ns_access(void)\n+{\n+\tuint32_t *csu_csl;\n+\tuint32_t reg;\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ns_dev); i++) {\n+\t\tcsu_csl = CONFIG_SYS_FSL_CSU_ADDR + ns_dev[i].ind / 2 * 4;\n+\t\treg = in_be32(csu_csl);\n+\t\tif (ns_dev[i].ind % 2 == 0)\n+\t\t\treg |= ns_dev[i].val << 16;\n+\t\telse\n+\t\t\treg |= ns_dev[i].val;\n+\t\tout_be32(csu_csl, reg);\n+\t}\n }\n \n int board_late_init(void)\n@@ -483,7 +580,7 @@ int board_late_init(void)\n \n \tahci_init(AHCI_BASE_ADDR);\n \tscsi_scan(1);\n-\tenable_ifc_ns_read_access();\n+\tenable_devices_ns_access();\n \treturn 0;\n }\n \n", "prefixes": [ "U-Boot", "4/4" ] }