Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 354092,
    "url": "http://patchwork.ozlabs.org/api/patches/354092/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-21-git-send-email-hdoyu@nvidia.com/",
    "project": {
        "id": 21,
        "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api",
        "name": "Linux Tegra Development",
        "link_name": "linux-tegra",
        "list_id": "linux-tegra.vger.kernel.org",
        "list_email": "linux-tegra@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1401448834-32659-21-git-send-email-hdoyu@nvidia.com>",
    "list_archive_url": null,
    "date": "2014-05-30T11:20:33",
    "name": "[PATCHv8,20/21] ARM: dt: tegra124: add tegra,smmu entry",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "1b7317440b6204368376c726569608b48f87a3a3",
    "submitter": {
        "id": 10265,
        "url": "http://patchwork.ozlabs.org/api/people/10265/?format=api",
        "name": "Hiroshi Doyu",
        "email": "hdoyu@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-21-git-send-email-hdoyu@nvidia.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/354092/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/354092/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-tegra-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 273801400D6\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 30 May 2014 21:20:56 +1000 (EST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752059AbaE3LUv (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 30 May 2014 07:20:51 -0400",
            "from hqemgate14.nvidia.com ([216.228.121.143]:12089 \"EHLO\n\thqemgate14.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1755039AbaE3LUt (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tFri, 30 May 2014 07:20:49 -0400",
            "from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate14.nvidia.com\n\tid <B538869a30000>; Fri, 30 May 2014 04:21:07 -0700",
            "from hqemhub01.nvidia.com ([172.20.12.94])\n\tby hqnvupgp08.nvidia.com (PGP Universal service);\n\tFri, 30 May 2014 04:15:46 -0700",
            "from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com\n\t(172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 04:20:49 -0700",
            "from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com\n\t(10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 13:20:45 +0200"
        ],
        "X-PGP-Universal": "processed;\n\tby hqnvupgp08.nvidia.com on Fri, 30 May 2014 04:15:46 -0700",
        "From": "Hiroshi Doyu <hdoyu@nvidia.com>",
        "To": "<linux-tegra@vger.kernel.org>",
        "Subject": "[PATCHv8 20/21] ARM: dt: tegra124: add tegra,smmu entry",
        "Date": "Fri, 30 May 2014 14:20:33 +0300",
        "Message-ID": "<1401448834-32659-21-git-send-email-hdoyu@nvidia.com>",
        "X-Mailer": "git-send-email 2.0.0.rc1.15.g7e76a2f",
        "In-Reply-To": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>",
        "References": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>",
        "X-NVConfidentiality": "public",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "Sender": "linux-tegra-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-tegra.vger.kernel.org>",
        "X-Mailing-List": "linux-tegra@vger.kernel.org"
    },
    "content": "Add Tegra SMMU DT entry.\n\nSigned-off-by: Hiroshi Doyu <hdoyu@nvidia.com>\n---\n arch/arm/boot/dts/tegra124.dtsi | 15 +++++++++++++++\n 1 file changed, 15 insertions(+)",
    "diff": "diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi\nindex 6e6bc4e8185c..5b339ca8a1ab 100644\n--- a/arch/arm/boot/dts/tegra124.dtsi\n+++ b/arch/arm/boot/dts/tegra124.dtsi\n@@ -1,5 +1,6 @@\n #include <dt-bindings/clock/tegra124-car.h>\n #include <dt-bindings/gpio/tegra-gpio.h>\n+#include <dt-bindings/memory/tegra-swgroup.h>\n #include <dt-bindings/pinctrl/pinctrl-tegra.h>\n #include <dt-bindings/interrupt-controller/arm-gic.h>\n \n@@ -449,6 +450,20 @@\n \t\tclock-names = \"pclk\", \"clk32k_in\";\n \t};\n \n+       smmu: iommu {\n+               compatible = \"nvidia,tegra124-smmu\";\n+               reg = <0x0 0x70019010 0x0 0x34\n+                      0x0 0x700191f0 0x0 0x10\n+                      0x0 0x70019228 0x0 0x58\n+                      0x0 0x70019600 0x0 0x4\n+                      0x0 0x700199b8 0x0 0x4\n+                      0x0 0x700199e0 0x0 0x18\n+                      0x0 0x70019a88 0x0 0x24>;\n+               nvidia,#asids = <128>;\n+               dma-window = <0x0 0x0 0x0 0x40000000>;\n+\t       iommu-cells = <2>;\n+       };\n+\n \tsdhci@0,700b0000 {\n \t\tcompatible = \"nvidia,tegra124-sdhci\";\n \t\treg = <0x0 0x700b0000 0x0 0x200>;\n",
    "prefixes": [
        "PATCHv8",
        "20/21"
    ]
}