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{
    "id": 354091,
    "url": "http://patchwork.ozlabs.org/api/patches/354091/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-20-git-send-email-hdoyu@nvidia.com/",
    "project": {
        "id": 21,
        "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api",
        "name": "Linux Tegra Development",
        "link_name": "linux-tegra",
        "list_id": "linux-tegra.vger.kernel.org",
        "list_email": "linux-tegra@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1401448834-32659-20-git-send-email-hdoyu@nvidia.com>",
    "list_archive_url": null,
    "date": "2014-05-30T11:20:32",
    "name": "[PATCHv8,19/21] iommu/tegra124: smmu: add multiple asid_security support",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "7d725587e7c8ca49e056c38210a491961fac30bd",
    "submitter": {
        "id": 10265,
        "url": "http://patchwork.ozlabs.org/api/people/10265/?format=api",
        "name": "Hiroshi Doyu",
        "email": "hdoyu@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-20-git-send-email-hdoyu@nvidia.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/354091/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/354091/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-tegra-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Received": [
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            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753393AbaE3LUv (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 30 May 2014 07:20:51 -0400",
            "from hqemgate15.nvidia.com ([216.228.121.64]:17142 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752059AbaE3LUt (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tFri, 30 May 2014 07:20:49 -0400",
            "from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com\n\tid <B538869860001>; Fri, 30 May 2014 04:20:38 -0700",
            "from hqemhub01.nvidia.com ([172.20.12.94])\n\tby hqnvupgp07.nvidia.com (PGP Universal service);\n\tFri, 30 May 2014 04:13:36 -0700",
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        ],
        "X-PGP-Universal": "processed;\n\tby hqnvupgp07.nvidia.com on Fri, 30 May 2014 04:13:36 -0700",
        "From": "Hiroshi Doyu <hdoyu@nvidia.com>",
        "To": "<linux-tegra@vger.kernel.org>",
        "Subject": "[PATCHv8 19/21] iommu/tegra124: smmu: add multiple asid_security\n\tsupport",
        "Date": "Fri, 30 May 2014 14:20:32 +0300",
        "Message-ID": "<1401448834-32659-20-git-send-email-hdoyu@nvidia.com>",
        "X-Mailer": "git-send-email 2.0.0.rc1.15.g7e76a2f",
        "In-Reply-To": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>",
        "References": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>",
        "X-NVConfidentiality": "public",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "Sender": "linux-tegra-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-tegra.vger.kernel.org>",
        "X-Mailing-List": "linux-tegra@vger.kernel.org"
    },
    "content": "In Tegra124 the number of MC_SMMU_ASID_SECURITY_# registers\nincreased. Now this info is provided as platfrom data. If no platfrom\ndata the default valude(1) is used.\n\nSigned-off-by: Hiroshi Doyu <hdoyu@nvidia.com>\n---\n drivers/iommu/tegra-smmu.c | 38 ++++++++++++++++++++++++++++++++------\n 1 file changed, 32 insertions(+), 6 deletions(-)",
    "diff": "diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c\nindex f499ca1f8498..53a64a1ac24d 100644\n--- a/drivers/iommu/tegra-smmu.c\n+++ b/drivers/iommu/tegra-smmu.c\n@@ -108,6 +108,13 @@ enum {\n #define SMMU_PTC_FLUSH_1\t\t\t0x9b8\n \n #define SMMU_ASID_SECURITY\t\t\t0x38\n+#define SMMU_ASID_SECURITY_1\t\t\t0x3c\n+#define SMMU_ASID_SECURITY_2\t\t\t0x9e0\n+#define SMMU_ASID_SECURITY_3\t\t\t0x9e4\n+#define SMMU_ASID_SECURITY_4\t\t\t0x9e8\n+#define SMMU_ASID_SECURITY_5\t\t\t0x9ec\n+#define SMMU_ASID_SECURITY_6\t\t\t0x9f0\n+#define SMMU_ASID_SECURITY_7\t\t\t0x9f4\n \n #define SMMU_STATS_CACHE_COUNT_BASE\t\t0x1f0\n \n@@ -243,6 +250,7 @@ struct smmu_device {\n \tstruct page *avp_vector_page;\t/* dummy page shared by all AS's */\n \n \tint nr_xlats;\t\t/* number of translation_enable registers */\n+\tint nr_asid_secs;\t/* number of asid_security registers */\n \tu32 tlb_reset;\t\t/* TLB config reset value */\n \tu32 ptc_reset;\t\t/* PTC config reset value */\n \n@@ -250,7 +258,7 @@ struct smmu_device {\n \t * Register image savers for suspend/resume\n \t */\n \tu32 *xlat;\n-\tunsigned long asid_security;\n+\tu32 *asid_sec;\n \n \tstruct dentry *debugfs_root;\n \tstruct smmu_debugfs_info *debugfs_info;\n@@ -267,6 +275,7 @@ struct smmu_platform_data {\n \tint asids;\t\t/* number of asids */\n \tint nr_xlats;\t\t/* number of translation_enable registers */\n \tbool lpae;\t\t/* PA > 32 bit */\n+\tint nr_asid_secs;\t/* number of asid_security registers */\n \tu32 tlb_reset;\t\t/* TLB config reset value */\n \tu32 ptc_reset;\t\t/* PTC config reset value */\n };\n@@ -329,6 +338,17 @@ static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)\n  */\n #define FLUSH_SMMU_REGS(smmu)\tsmmu_read(smmu, SMMU_CONFIG)\n \n+static const u32 smmu_asid_sec_ofs[] = {\n+\tSMMU_ASID_SECURITY,\n+\tSMMU_ASID_SECURITY_1,\n+\tSMMU_ASID_SECURITY_2,\n+\tSMMU_ASID_SECURITY_3,\n+\tSMMU_ASID_SECURITY_4,\n+\tSMMU_ASID_SECURITY_5,\n+\tSMMU_ASID_SECURITY_6,\n+\tSMMU_ASID_SECURITY_7,\n+};\n+\n static size_t smmu_get_asid_offset(int id)\n {\n \tswitch (id) {\n@@ -526,7 +546,9 @@ static int smmu_setup_regs(struct smmu_device *smmu)\n \t\tsmmu_write(smmu, smmu->xlat[i],\n \t\t\t   SMMU_TRANSLATION_ENABLE_0 + i * sizeof(u32));\n \n-\tsmmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY);\n+\tfor (i = 0; i < smmu->nr_asid_secs; i++)\n+\t\tsmmu_write(smmu, smmu->asid_sec[i], smmu_asid_sec_ofs[i]);\n+\n \tsmmu_write(smmu, smmu->ptc_reset, SMMU_CACHE_CONFIG(_PTC));\n \tsmmu_write(smmu, smmu->tlb_reset, SMMU_CACHE_CONFIG(_TLB));\n \n@@ -1242,7 +1264,9 @@ static int tegra_smmu_suspend(struct device *dev)\n \t\tsmmu->xlat[i] = smmu_read(smmu,\n \t\t\t\tSMMU_TRANSLATION_ENABLE_0 + i * sizeof(u32));\n \n-\tsmmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY);\n+\tfor (i = 0; i < smmu->nr_asid_secs; i++)\n+\t\tsmmu->asid_sec[i] =\n+\t\t\tsmmu_read(smmu, smmu_asid_sec_ofs[i]);\n \treturn 0;\n }\n \n@@ -1300,7 +1324,7 @@ static int tegra_smmu_probe(struct platform_device *pdev)\n \tsize_t bytes, uninitialized_var(size);\n \tconst struct of_device_id *match;\n \tconst struct smmu_platform_data *pdata;\n-\tint nr_xlats;\n+\tint nr_xlats, nr_asid_secs;\n \n \tif (smmu_handle)\n \t\treturn -EIO;\n@@ -1312,6 +1336,7 @@ static int tegra_smmu_probe(struct platform_device *pdev)\n \t\treturn -EINVAL;\n \tpdata = match->data;\n \tnr_xlats = (pdata && pdata->nr_xlats) ?\tpdata->nr_xlats : 3;\n+\tnr_asid_secs = (pdata && pdata->nr_asid_secs) ?\tpdata->nr_asid_secs : 1;\n \n \tif (of_property_read_u32(dev->of_node, \"nvidia,#asids\", &asids))\n \t\tasids = (pdata && pdata->asids) ? pdata->asids : 4;\n@@ -1320,7 +1345,7 @@ static int tegra_smmu_probe(struct platform_device *pdev)\n \n \tbytes = sizeof(*smmu) + asids * (sizeof(*smmu->as) +\n \t\t\t\t\t sizeof(struct dma_iommu_mapping *));\n-\tbytes += sizeof(u32) * nr_xlats;\n+\tbytes += sizeof(u32) * (nr_asid_secs + nr_xlats);\n \tsmmu = devm_kzalloc(dev, bytes, GFP_KERNEL);\n \tif (!smmu) {\n \t\tdev_err(dev, \"failed to allocate smmu_device\\n\");\n@@ -1330,6 +1355,7 @@ static int tegra_smmu_probe(struct platform_device *pdev)\n \tsmmu->clients = RB_ROOT;\n \tsmmu->map = (struct dma_iommu_mapping **)(smmu->as + asids);\n \tsmmu->xlat = (u32 *)(smmu->map + smmu->num_as);\n+\tsmmu->asid_sec = smmu->xlat + smmu->nr_xlats;\n \tsmmu->nregs = pdev->num_resources;\n \tsmmu->tlb_reset = (pdata && pdata->tlb_reset) ? pdata->tlb_reset :\n \t\t(SMMU_TLB_CONFIG_RESET_VAL | 0x10);\n@@ -1369,7 +1395,7 @@ static int tegra_smmu_probe(struct platform_device *pdev)\n \tsmmu->nr_xlats = nr_xlats;\n \tsmmu->iovmm_base = base;\n \tsmmu->page_count = size;\n-\tsmmu->asid_security = 0;\n+\tsmmu->nr_asid_secs = nr_asid_secs;\n \tfor (i = 0; i < smmu->nr_xlats; i++)\n \t\tsmmu->xlat[i] = ~0;\n \n",
    "prefixes": [
        "PATCHv8",
        "19/21"
    ]
}