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GET /api/patches/354090/?format=api
{ "id": 354090, "url": "http://patchwork.ozlabs.org/api/patches/354090/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-19-git-send-email-hdoyu@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1401448834-32659-19-git-send-email-hdoyu@nvidia.com>", "list_archive_url": null, "date": "2014-05-30T11:20:31", "name": "[PATCHv8,18/21] iommu/tegra124: smmu: adjust TLB_FLUSH_ASID bit range", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b322dd73abfa25531148ad0386de3ce6896b869c", "submitter": { "id": 10265, "url": "http://patchwork.ozlabs.org/api/people/10265/?format=api", "name": "Hiroshi Doyu", "email": "hdoyu@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-19-git-send-email-hdoyu@nvidia.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/354090/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/354090/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-tegra-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 0668B1400D6\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 30 May 2014 21:20:55 +1000 (EST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751291AbaE3LUu (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 30 May 2014 07:20:50 -0400", "from hqemgate15.nvidia.com ([216.228.121.64]:17141 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753393AbaE3LUs (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tFri, 30 May 2014 07:20:48 -0400", "from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com\n\tid <B538869860000>; Fri, 30 May 2014 04:20:38 -0700", "from hqemhub01.nvidia.com ([172.20.12.94])\n\tby hqnvupgp08.nvidia.com (PGP Universal service);\n\tFri, 30 May 2014 04:15:45 -0700", "from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com\n\t(172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 04:20:48 -0700", "from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com\n\t(10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 13:20:45 +0200" ], "X-PGP-Universal": "processed;\n\tby hqnvupgp08.nvidia.com on Fri, 30 May 2014 04:15:45 -0700", "From": "Hiroshi Doyu <hdoyu@nvidia.com>", "To": "<linux-tegra@vger.kernel.org>", "Subject": "[PATCHv8 18/21] iommu/tegra124: smmu: adjust TLB_FLUSH_ASID bit\n\trange", "Date": "Fri, 30 May 2014 14:20:31 +0300", "Message-ID": "<1401448834-32659-19-git-send-email-hdoyu@nvidia.com>", "X-Mailer": "git-send-email 2.0.0.rc1.15.g7e76a2f", "In-Reply-To": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "References": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "Sender": "linux-tegra-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-tegra.vger.kernel.org>", "X-Mailing-List": "linux-tegra@vger.kernel.org" }, "content": "TLB_FLUSH_ASID bit range depends on the number of asids to support\nother number than the current 4, especially for a new Tegra124. Based\non Terje's internal patch.\n\nSigned-off-by: Hiroshi Doyu <hdoyu@nvidia.com>\nCc: Terje Bergstrom <tbergstrom@nvidia.com>\n---\n drivers/iommu/tegra-smmu.c | 9 ++++++---\n 1 file changed, 6 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c\nindex 7f13133eab0a..f499ca1f8498 100644\n--- a/drivers/iommu/tegra-smmu.c\n+++ b/drivers/iommu/tegra-smmu.c\n@@ -92,11 +92,14 @@ enum {\n #define SMMU_TLB_FLUSH_VA_MATCH_ALL\t\t0\n #define SMMU_TLB_FLUSH_VA_MATCH_SECTION\t\t2\n #define SMMU_TLB_FLUSH_VA_MATCH_GROUP\t\t3\n-#define SMMU_TLB_FLUSH_ASID_SHIFT\t\t29\n+#define SMMU_TLB_FLUSH_ASID_SHIFT_BASE\t\t31\n #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE\t0\n #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE\t1\n #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT\t\t31\n \n+#define SMMU_TLB_FLUSH_ASID_SHIFT(as)\t\t\t\t\t\\\n+\t(SMMU_TLB_FLUSH_ASID_SHIFT_BASE - __ffs((as)->smmu->num_as))\n+\n #define SMMU_PTC_FLUSH\t\t\t\t0x34\n #define SMMU_PTC_FLUSH_TYPE_ALL\t\t\t0\n #define SMMU_PTC_FLUSH_TYPE_ADR\t\t\t1\n@@ -562,7 +565,7 @@ static void flush_ptc_and_tlb(struct smmu_device *smmu,\n \n \tval = tlb_flush_va |\n \t\tSMMU_TLB_FLUSH_ASID_MATCH__ENABLE |\n-\t\t(as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);\n+\t\t(as->asid << SMMU_TLB_FLUSH_ASID_SHIFT(as));\n \tsmmu_write(smmu, val, SMMU_TLB_FLUSH);\n \tFLUSH_SMMU_REGS(smmu);\n }\n@@ -729,7 +732,7 @@ static int alloc_pdir(struct smmu_as *as)\n \n \tval = SMMU_TLB_FLUSH_VA_MATCH_ALL |\n \t\tSMMU_TLB_FLUSH_ASID_MATCH__ENABLE |\n-\t\t(as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);\n+\t\t(as->asid << SMMU_TLB_FLUSH_ASID_SHIFT(as));\n \tsmmu_write(smmu, val, SMMU_TLB_FLUSH);\n \tFLUSH_SMMU_REGS(as->smmu);\n \n", "prefixes": [ "PATCHv8", "18/21" ] }