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GET /api/patches/354089/?format=api
{ "id": 354089, "url": "http://patchwork.ozlabs.org/api/patches/354089/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-18-git-send-email-hdoyu@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1401448834-32659-18-git-send-email-hdoyu@nvidia.com>", "list_archive_url": null, "date": "2014-05-30T11:20:30", "name": "[PATCHv8,17/21] iommu/tegra124: smmu: {TLB,PTC} reset value per SoC", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a8fb352efb5bedd85f66e7156d57601de456a9c0", "submitter": { "id": 10265, "url": "http://patchwork.ozlabs.org/api/people/10265/?format=api", "name": "Hiroshi Doyu", "email": "hdoyu@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-18-git-send-email-hdoyu@nvidia.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/354089/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/354089/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-tegra-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 762121400E2\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 30 May 2014 21:20:54 +1000 (EST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753504AbaE3LUu (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 30 May 2014 07:20:50 -0400", "from hqemgate16.nvidia.com ([216.228.121.65]:3689 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751291AbaE3LUs (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tFri, 30 May 2014 07:20:48 -0400", "from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com\n\tid <B538869850000>; Fri, 30 May 2014 04:20:37 -0700", "from hqemhub01.nvidia.com ([172.20.12.94])\n\tby hqnvupgp07.nvidia.com (PGP Universal service);\n\tFri, 30 May 2014 04:13:35 -0700", "from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com\n\t(172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 04:20:47 -0700", "from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com\n\t(10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 13:20:44 +0200" ], "X-PGP-Universal": "processed;\n\tby hqnvupgp07.nvidia.com on Fri, 30 May 2014 04:13:35 -0700", "From": "Hiroshi Doyu <hdoyu@nvidia.com>", "To": "<linux-tegra@vger.kernel.org>", "Subject": "[PATCHv8 17/21] iommu/tegra124: smmu: {TLB, PTC} reset value per SoC", "Date": "Fri, 30 May 2014 14:20:30 +0300", "Message-ID": "<1401448834-32659-18-git-send-email-hdoyu@nvidia.com>", "X-Mailer": "git-send-email 2.0.0.rc1.15.g7e76a2f", "In-Reply-To": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "References": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "Sender": "linux-tegra-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-tegra.vger.kernel.org>", "X-Mailing-List": "linux-tegra@vger.kernel.org" }, "content": "T124 has some new register bits in {TLB,PTC}_CONFIG:\n\n- TLB_RR_ARB and PTC_REQ_LIMIT\n- TLB_ACTIVE_LINES 0x20 instead of 0x10\n\nThey are defined as platform data now.\n\nSigned-off-by: Hiroshi Doyu <hdoyu@nvidia.com>\n---\n drivers/iommu/tegra-smmu.c | 17 +++++++++++++----\n 1 file changed, 13 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c\nindex 24fe16f1a1d8..7f13133eab0a 100644\n--- a/drivers/iommu/tegra-smmu.c\n+++ b/drivers/iommu/tegra-smmu.c\n@@ -71,12 +71,13 @@ enum {\n #define SMMU_CACHE_CONFIG_STATS_TEST\t\t(1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)\n \n #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE\t(1 << 29)\n-#define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE\t0x10\n-#define SMMU_TLB_CONFIG_RESET_VAL\t\t0x20000010\n+#define SMMU_TLB_CONFIG_RESET_VAL\t\t0x20000000\n+#define SMMU_TLB_RR_ARB\t\t\t\t(1 << 28)\n \n #define SMMU_PTC_CONFIG_CACHE__ENABLE\t\t(1 << 29)\n #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN\t0x3f\n #define SMMU_PTC_CONFIG_RESET_VAL\t\t0x2000003f\n+#define SMMU_PTC_REQ_LIMIT\t\t\t(8 << 24)\n \n #define SMMU_PTB_ASID\t\t\t\t0x1c\n #define SMMU_PTB_ASID_CURRENT_SHIFT\t\t0\n@@ -239,6 +240,8 @@ struct smmu_device {\n \tstruct page *avp_vector_page;\t/* dummy page shared by all AS's */\n \n \tint nr_xlats;\t\t/* number of translation_enable registers */\n+\tu32 tlb_reset;\t\t/* TLB config reset value */\n+\tu32 ptc_reset;\t\t/* PTC config reset value */\n \n \t/*\n \t * Register image savers for suspend/resume\n@@ -261,6 +264,8 @@ struct smmu_platform_data {\n \tint asids;\t\t/* number of asids */\n \tint nr_xlats;\t\t/* number of translation_enable registers */\n \tbool lpae;\t\t/* PA > 32 bit */\n+\tu32 tlb_reset;\t\t/* TLB config reset value */\n+\tu32 ptc_reset;\t\t/* PTC config reset value */\n };\n \n static struct smmu_device *smmu_handle; /* unique for a system */\n@@ -519,8 +524,8 @@ static int smmu_setup_regs(struct smmu_device *smmu)\n \t\t\t SMMU_TRANSLATION_ENABLE_0 + i * sizeof(u32));\n \n \tsmmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY);\n-\tsmmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_TLB));\n-\tsmmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_PTC));\n+\tsmmu_write(smmu, smmu->ptc_reset, SMMU_CACHE_CONFIG(_PTC));\n+\tsmmu_write(smmu, smmu->tlb_reset, SMMU_CACHE_CONFIG(_TLB));\n \n \tsmmu_flush_regs(smmu, 1);\n \n@@ -1323,6 +1328,10 @@ static int tegra_smmu_probe(struct platform_device *pdev)\n \tsmmu->map = (struct dma_iommu_mapping **)(smmu->as + asids);\n \tsmmu->xlat = (u32 *)(smmu->map + smmu->num_as);\n \tsmmu->nregs = pdev->num_resources;\n+\tsmmu->tlb_reset = (pdata && pdata->tlb_reset) ? pdata->tlb_reset :\n+\t\t(SMMU_TLB_CONFIG_RESET_VAL | 0x10);\n+\tsmmu->ptc_reset = (pdata && pdata->ptc_reset) ? pdata->ptc_reset :\n+\t\t(SMMU_PTC_CONFIG_RESET_VAL | SMMU_PTC_REQ_LIMIT);\n \tsmmu->regs = devm_kzalloc(dev, 2 * smmu->nregs * sizeof(*smmu->regs),\n \t\t\t\t GFP_KERNEL);\n \tsmmu->rege = smmu->regs + smmu->nregs;\n", "prefixes": [ "PATCHv8", "17/21" ] }