Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/354088/?format=api
{ "id": 354088, "url": "http://patchwork.ozlabs.org/api/patches/354088/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-17-git-send-email-hdoyu@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1401448834-32659-17-git-send-email-hdoyu@nvidia.com>", "list_archive_url": null, "date": "2014-05-30T11:20:29", "name": "[PATCHv8,16/21] iommu/tegra124: smmu: support more than 32 bit pa", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "689c588cc940c99abaa20b98e0f7cde6e56ca84d", "submitter": { "id": 10265, "url": "http://patchwork.ozlabs.org/api/people/10265/?format=api", "name": "Hiroshi Doyu", "email": "hdoyu@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-17-git-send-email-hdoyu@nvidia.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/354088/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/354088/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-tegra-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id DBB7F1400D6\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 30 May 2014 21:20:53 +1000 (EST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755155AbaE3LUu (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 30 May 2014 07:20:50 -0400", "from hqemgate15.nvidia.com ([216.228.121.64]:17140 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753504AbaE3LUs (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tFri, 30 May 2014 07:20:48 -0400", "from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com\n\tid <B538869850000>; Fri, 30 May 2014 04:20:37 -0700", "from hqemhub01.nvidia.com ([172.20.12.94])\n\tby hqnvupgp08.nvidia.com (PGP Universal service);\n\tFri, 30 May 2014 04:15:44 -0700", "from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com\n\t(172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 04:20:47 -0700", "from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com\n\t(10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 13:20:44 +0200" ], "X-PGP-Universal": "processed;\n\tby hqnvupgp08.nvidia.com on Fri, 30 May 2014 04:15:44 -0700", "From": "Hiroshi Doyu <hdoyu@nvidia.com>", "To": "<linux-tegra@vger.kernel.org>", "Subject": "[PATCHv8 16/21] iommu/tegra124: smmu: support more than 32 bit pa", "Date": "Fri, 30 May 2014 14:20:29 +0300", "Message-ID": "<1401448834-32659-17-git-send-email-hdoyu@nvidia.com>", "X-Mailer": "git-send-email 2.0.0.rc1.15.g7e76a2f", "In-Reply-To": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "References": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "Sender": "linux-tegra-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-tegra.vger.kernel.org>", "X-Mailing-List": "linux-tegra@vger.kernel.org" }, "content": "Add support for more than 32 bit physical address. If physical\naddress space is 32bit, there will be no register write\nhappening. Based on Pavan's internal patch.\n\nSigned-off-by: Hiroshi Doyu <hdoyu@nvidia.com>\nCc: Pavan Kunapuli <pkunapuli@nvidia.com>\nCc: Mark Zhang <markz@nvidia.com>\n---\n drivers/iommu/tegra-smmu.c | 36 +++++++++++++++++++++++++++++-------\n 1 file changed, 29 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c\nindex 12a4a8f68538..24fe16f1a1d8 100644\n--- a/drivers/iommu/tegra-smmu.c\n+++ b/drivers/iommu/tegra-smmu.c\n@@ -101,6 +101,8 @@ enum {\n #define SMMU_PTC_FLUSH_TYPE_ADR\t\t\t1\n #define SMMU_PTC_FLUSH_ADR_SHIFT\t\t4\n \n+#define SMMU_PTC_FLUSH_1\t\t\t0x9b8\n+\n #define SMMU_ASID_SECURITY\t\t\t0x38\n \n #define SMMU_STATS_CACHE_COUNT_BASE\t\t0x1f0\n@@ -143,7 +145,7 @@ enum {\n #define SMMU_PDIR_SHIFT\t12\n #define SMMU_PDE_SHIFT\t12\n #define SMMU_PTE_SHIFT\t12\n-#define SMMU_PFN_MASK\t0x000fffff\n+#define SMMU_PFN_MASK\t0x0fffffff\n \n #define SMMU_ADDR_TO_PFN(addr)\t((addr) >> 12)\n #define SMMU_ADDR_TO_PDN(addr)\t((addr) >> 22)\n@@ -258,6 +260,7 @@ struct smmu_device {\n struct smmu_platform_data {\n \tint asids;\t\t/* number of asids */\n \tint nr_xlats;\t\t/* number of translation_enable registers */\n+\tbool lpae;\t\t/* PA > 32 bit */\n };\n \n static struct smmu_device *smmu_handle; /* unique for a system */\n@@ -301,6 +304,8 @@ static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)\n #define VA_PAGE_TO_PA(va, page)\t\\\n \t(page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))\n \n+#define VA_PAGE_TO_PA_HI(va, page) (u32)((u64)page_to_phys(page) >> 32)\n+\n #define FLUSH_CPU_DCACHE(va, page, size)\t\\\n \tdo {\t\\\n \t\tunsigned long _pa_ = VA_PAGE_TO_PA(va, page);\t\t\\\n@@ -525,6 +530,20 @@ static int smmu_setup_regs(struct smmu_device *smmu)\n \treturn 0;\n }\n \n+static void flush_ptc_by_addr(struct smmu_device *smmu, unsigned long *pte,\n+\t\t\t struct page *page)\n+{\n+\tu32 val;\n+\n+\tval = VA_PAGE_TO_PA_HI(pte, page);\n+\tsmmu_write(smmu, val, SMMU_PTC_FLUSH_1);\n+\n+\tval = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page);\n+\tsmmu_write(smmu, val, SMMU_PTC_FLUSH);\n+\n+\tFLUSH_SMMU_REGS(smmu);\n+}\n+\n static void flush_ptc_and_tlb(struct smmu_device *smmu,\n \t\t struct smmu_as *as, dma_addr_t iova,\n \t\t unsigned long *pte, struct page *page, int is_pde)\n@@ -534,9 +553,8 @@ static void flush_ptc_and_tlb(struct smmu_device *smmu,\n \t\t? SMMU_TLB_FLUSH_VA(iova, SECTION)\n \t\t: SMMU_TLB_FLUSH_VA(iova, GROUP);\n \n-\tval = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page);\n-\tsmmu_write(smmu, val, SMMU_PTC_FLUSH);\n-\tFLUSH_SMMU_REGS(smmu);\n+\tflush_ptc_by_addr(smmu, pte, page);\n+\n \tval = tlb_flush_va |\n \t\tSMMU_TLB_FLUSH_ASID_MATCH__ENABLE |\n \t\t(as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);\n@@ -701,9 +719,9 @@ static int alloc_pdir(struct smmu_as *as)\n \tfor (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)\n \t\tpdir[pdn] = _PDE_VACANT(pdn);\n \tFLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE);\n-\tval = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page);\n-\tsmmu_write(smmu, val, SMMU_PTC_FLUSH);\n-\tFLUSH_SMMU_REGS(as->smmu);\n+\n+\tflush_ptc_by_addr(as->smmu, pdir, page);\n+\n \tval = SMMU_TLB_FLUSH_VA_MATCH_ALL |\n \t\tSMMU_TLB_FLUSH_ASID_MATCH__ENABLE |\n \t\t(as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);\n@@ -1252,6 +1270,10 @@ static void tegra_smmu_create_default_map(struct smmu_device *smmu)\n static const struct smmu_platform_data tegra124_smmu_pdata = {\n \t.asids = 128,\n \t.nr_xlats = 4,\n+\t.lpae = true,\n+\t.nr_asid_secs = 8,\n+\t.tlb_reset = SMMU_TLB_CONFIG_RESET_VAL | SMMU_TLB_RR_ARB | 0x20,\n+\t.ptc_reset = SMMU_PTC_CONFIG_RESET_VAL | SMMU_PTC_REQ_LIMIT,\n };\n \n static struct of_device_id tegra_smmu_of_match[] = {\n", "prefixes": [ "PATCHv8", "16/21" ] }