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GET /api/patches/354087/?format=api
{ "id": 354087, "url": "http://patchwork.ozlabs.org/api/patches/354087/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-16-git-send-email-hdoyu@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1401448834-32659-16-git-send-email-hdoyu@nvidia.com>", "list_archive_url": null, "date": "2014-05-30T11:20:28", "name": "[PATCHv8,15/21] iommu/tegra124: smmu: add support platform data", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cf405d5c6318997d6606133beeddc2c0468ac077", "submitter": { "id": 10265, "url": "http://patchwork.ozlabs.org/api/people/10265/?format=api", "name": "Hiroshi Doyu", "email": "hdoyu@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-16-git-send-email-hdoyu@nvidia.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/354087/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/354087/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-tegra-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 534981400E2\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 30 May 2014 21:20:53 +1000 (EST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754908AbaE3LUt (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 30 May 2014 07:20:49 -0400", "from hqemgate15.nvidia.com ([216.228.121.64]:17139 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753146AbaE3LUr (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tFri, 30 May 2014 07:20:47 -0400", "from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com\n\tid <B538869840000>; Fri, 30 May 2014 04:20:36 -0700", "from hqemhub01.nvidia.com ([172.20.12.94])\n\tby hqnvupgp07.nvidia.com (PGP Universal service);\n\tFri, 30 May 2014 04:13:34 -0700", "from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com\n\t(172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 04:20:47 -0700", "from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com\n\t(10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 13:20:43 +0200" ], "X-PGP-Universal": "processed;\n\tby hqnvupgp07.nvidia.com on Fri, 30 May 2014 04:13:34 -0700", "From": "Hiroshi Doyu <hdoyu@nvidia.com>", "To": "<linux-tegra@vger.kernel.org>", "Subject": "[PATCHv8 15/21] iommu/tegra124: smmu: add support platform data", "Date": "Fri, 30 May 2014 14:20:28 +0300", "Message-ID": "<1401448834-32659-16-git-send-email-hdoyu@nvidia.com>", "X-Mailer": "git-send-email 2.0.0.rc1.15.g7e76a2f", "In-Reply-To": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "References": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "Sender": "linux-tegra-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-tegra.vger.kernel.org>", "X-Mailing-List": "linux-tegra@vger.kernel.org" }, "content": "The later Tegra SoC(>= T124) has more registers for\nMC_SMMU_TRANSLATION_ENABLE_*. Now those info is provided as platfrom\ndata. If those varies a lot on SoCs in the future, we can consider\nputting them into DT later.\n\nSigned-off-by: Hiroshi Doyu <hdoyu@nvidia.com>\n---\n .../bindings/iommu/nvidia,tegra30-smmu.txt | 4 +-\n drivers/iommu/tegra-smmu.c | 68 ++++++++++++++--------\n 2 files changed, 47 insertions(+), 25 deletions(-)", "diff": "diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt\nindex 89fb5434b730..38b444ff1d4c 100644\n--- a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt\n+++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt\n@@ -1,8 +1,8 @@\n NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit)\n \n Required properties:\n-- compatible : \"nvidia,tegra30-smmu\"\n-- reg : Should contain 3 register banks(address and length) for each\n+- compatible : \"nvidia,tegra124-smmu\", \"nvidia,tegra30-smmu\"\n+- reg : Can contain multiple register banks(address and length) for each\n of the SMMU register blocks.\n - interrupts : Should contain MC General interrupt.\n - nvidia,#asids : # of ASIDs\ndiff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c\nindex 080dbda874e5..12a4a8f68538 100644\n--- a/drivers/iommu/tegra-smmu.c\n+++ b/drivers/iommu/tegra-smmu.c\n@@ -32,6 +32,7 @@\n #include <linux/iommu.h>\n #include <linux/io.h>\n #include <linux/of.h>\n+#include <linux/of_device.h>\n #include <linux/of_iommu.h>\n #include <linux/debugfs.h>\n #include <linux/seq_file.h>\n@@ -108,8 +109,6 @@ enum {\n \t(SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss)\n \n #define SMMU_TRANSLATION_ENABLE_0\t\t0x228\n-#define SMMU_TRANSLATION_ENABLE_1\t\t0x22c\n-#define SMMU_TRANSLATION_ENABLE_2\t\t0x230\n \n #define SMMU_AFI_ASID\t0x238 /* PCIE */\n #define SMMU_ASID_BASE\tSMMU_AFI_ASID\n@@ -237,12 +236,12 @@ struct smmu_device {\n \tstruct rb_root\tclients;\n \tstruct page *avp_vector_page;\t/* dummy page shared by all AS's */\n \n+\tint nr_xlats;\t\t/* number of translation_enable registers */\n+\n \t/*\n \t * Register image savers for suspend/resume\n \t */\n-\tunsigned long translation_enable_0;\n-\tunsigned long translation_enable_1;\n-\tunsigned long translation_enable_2;\n+\tu32 *xlat;\n \tunsigned long asid_security;\n \n \tstruct dentry *debugfs_root;\n@@ -256,6 +255,11 @@ struct smmu_device {\n \tstruct smmu_as\tas[0];\t\t/* Run-time allocated array */\n };\n \n+struct smmu_platform_data {\n+\tint asids;\t\t/* number of asids */\n+\tint nr_xlats;\t\t/* number of translation_enable registers */\n+};\n+\n static struct smmu_device *smmu_handle; /* unique for a system */\n \n /*\n@@ -505,9 +509,10 @@ static int smmu_setup_regs(struct smmu_device *smmu)\n \t\t\t__smmu_client_set_swgroups(c, c->swgroups, 1);\n \t}\n \n-\tsmmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0);\n-\tsmmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1);\n-\tsmmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2);\n+\tfor (i = 0; i < smmu->nr_xlats; i++)\n+\t\tsmmu_write(smmu, smmu->xlat[i],\n+\t\t\t SMMU_TRANSLATION_ENABLE_0 + i * sizeof(u32));\n+\n \tsmmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY);\n \tsmmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_TLB));\n \tsmmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_PTC));\n@@ -1204,11 +1209,13 @@ err_out:\n \n static int tegra_smmu_suspend(struct device *dev)\n {\n+\tint i;\n \tstruct smmu_device *smmu = dev_get_drvdata(dev);\n \n-\tsmmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0);\n-\tsmmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1);\n-\tsmmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2);\n+\tfor (i = 0; i < smmu->nr_xlats; i++)\n+\t\tsmmu->xlat[i] = smmu_read(smmu,\n+\t\t\t\tSMMU_TRANSLATION_ENABLE_0 + i * sizeof(u32));\n+\n \tsmmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY);\n \treturn 0;\n }\n@@ -1242,6 +1249,18 @@ static void tegra_smmu_create_default_map(struct smmu_device *smmu)\n \t}\n }\n \n+static const struct smmu_platform_data tegra124_smmu_pdata = {\n+\t.asids = 128,\n+\t.nr_xlats = 4,\n+};\n+\n+static struct of_device_id tegra_smmu_of_match[] = {\n+\t{ .compatible = \"nvidia,tegra124-smmu\", .data = &tegra124_smmu_pdata, },\n+\t{ .compatible = \"nvidia,tegra30-smmu\", },\n+\t{ },\n+};\n+MODULE_DEVICE_TABLE(of, tegra_smmu_of_match);\n+\n static int tegra_smmu_probe(struct platform_device *pdev)\n {\n \tstruct smmu_device *smmu;\n@@ -1249,20 +1268,29 @@ static int tegra_smmu_probe(struct platform_device *pdev)\n \tint i, asids, err = 0;\n \tdma_addr_t uninitialized_var(base);\n \tsize_t bytes, uninitialized_var(size);\n+\tconst struct of_device_id *match;\n+\tconst struct smmu_platform_data *pdata;\n+\tint nr_xlats;\n \n \tif (smmu_handle)\n \t\treturn -EIO;\n \n \tBUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT);\n \n-\tif (of_property_read_u32(dev->of_node, \"nvidia,#asids\", &asids))\n-\t\treturn -ENODEV;\n+\tmatch = of_match_device(tegra_smmu_of_match, &pdev->dev);\n+\tif (!match)\n+\t\treturn -EINVAL;\n+\tpdata = match->data;\n+\tnr_xlats = (pdata && pdata->nr_xlats) ?\tpdata->nr_xlats : 3;\n \n+\tif (of_property_read_u32(dev->of_node, \"nvidia,#asids\", &asids))\n+\t\tasids = (pdata && pdata->asids) ? pdata->asids : 4;\n \tif (asids < NUM_OF_STATIC_MAPS)\n \t\treturn -EINVAL;\n \n \tbytes = sizeof(*smmu) + asids * (sizeof(*smmu->as) +\n \t\t\t\t\t sizeof(struct dma_iommu_mapping *));\n+\tbytes += sizeof(u32) * nr_xlats;\n \tsmmu = devm_kzalloc(dev, bytes, GFP_KERNEL);\n \tif (!smmu) {\n \t\tdev_err(dev, \"failed to allocate smmu_device\\n\");\n@@ -1271,6 +1299,7 @@ static int tegra_smmu_probe(struct platform_device *pdev)\n \n \tsmmu->clients = RB_ROOT;\n \tsmmu->map = (struct dma_iommu_mapping **)(smmu->as + asids);\n+\tsmmu->xlat = (u32 *)(smmu->map + smmu->num_as);\n \tsmmu->nregs = pdev->num_resources;\n \tsmmu->regs = devm_kzalloc(dev, 2 * smmu->nregs * sizeof(*smmu->regs),\n \t\t\t\t GFP_KERNEL);\n@@ -1303,13 +1332,12 @@ static int tegra_smmu_probe(struct platform_device *pdev)\n \tsmmu->ahb = of_parse_phandle(dev->of_node, \"nvidia,ahb\", 0);\n \tsmmu->iommu.dev = dev;\n \tsmmu->num_as = asids;\n+\tsmmu->nr_xlats = nr_xlats;\n \tsmmu->iovmm_base = base;\n \tsmmu->page_count = size;\n-\n-\tsmmu->translation_enable_0 = ~0;\n-\tsmmu->translation_enable_1 = ~0;\n-\tsmmu->translation_enable_2 = ~0;\n \tsmmu->asid_security = 0;\n+\tfor (i = 0; i < smmu->nr_xlats; i++)\n+\t\tsmmu->xlat[i] = ~0;\n \n \tfor (i = 0; i < smmu->num_as; i++) {\n \t\tstruct smmu_as *as = &smmu->as[i];\n@@ -1364,12 +1392,6 @@ static const struct dev_pm_ops tegra_smmu_pm_ops = {\n \t.resume\t\t= tegra_smmu_resume,\n };\n \n-static struct of_device_id tegra_smmu_of_match[] = {\n-\t{ .compatible = \"nvidia,tegra30-smmu\", },\n-\t{ },\n-};\n-MODULE_DEVICE_TABLE(of, tegra_smmu_of_match);\n-\n static struct platform_driver tegra_smmu_driver = {\n \t.probe\t\t= tegra_smmu_probe,\n \t.remove\t\t= tegra_smmu_remove,\n", "prefixes": [ "PATCHv8", "15/21" ] }