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GET /api/patches/354086/?format=api
{ "id": 354086, "url": "http://patchwork.ozlabs.org/api/patches/354086/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-15-git-send-email-hdoyu@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1401448834-32659-15-git-send-email-hdoyu@nvidia.com>", "list_archive_url": null, "date": "2014-05-30T11:20:27", "name": "[PATCHv8,14/21] iommu/tegra124: smmu: convert swgroup ID to asid offset", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d4e6d6a06179c219ba430044eb66e9e3913fc94f", "submitter": { "id": 10265, "url": "http://patchwork.ozlabs.org/api/people/10265/?format=api", "name": "Hiroshi Doyu", "email": "hdoyu@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-15-git-send-email-hdoyu@nvidia.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/354086/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/354086/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-tegra-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id B89BC1400D6\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 30 May 2014 21:20:52 +1000 (EST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754906AbaE3LUt (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 30 May 2014 07:20:49 -0400", "from hqemgate14.nvidia.com ([216.228.121.143]:12088 \"EHLO\n\thqemgate14.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752059AbaE3LUr (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tFri, 30 May 2014 07:20:47 -0400", "from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate14.nvidia.com\n\tid <B538869a10000>; Fri, 30 May 2014 04:21:05 -0700", "from hqemhub01.nvidia.com ([172.20.12.94])\n\tby hqnvupgp08.nvidia.com (PGP Universal service);\n\tFri, 30 May 2014 04:15:43 -0700", "from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com\n\t(172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 04:20:46 -0700", "from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com\n\t(10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 13:20:43 +0200" ], "X-PGP-Universal": "processed;\n\tby hqnvupgp08.nvidia.com on Fri, 30 May 2014 04:15:43 -0700", "From": "Hiroshi Doyu <hdoyu@nvidia.com>", "To": "<linux-tegra@vger.kernel.org>", "Subject": "[PATCHv8 14/21] iommu/tegra124: smmu: convert swgroup ID to asid\n\toffset", "Date": "Fri, 30 May 2014 14:20:27 +0300", "Message-ID": "<1401448834-32659-15-git-send-email-hdoyu@nvidia.com>", "X-Mailer": "git-send-email 2.0.0.rc1.15.g7e76a2f", "In-Reply-To": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "References": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "Sender": "linux-tegra-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-tegra.vger.kernel.org>", "X-Mailing-List": "linux-tegra@vger.kernel.org" }, "content": "Provide a conversion table from swgroup ID to MC_SMMU_<swgroup\nname>_ASID_0 register offset to support non-linear conversion. This\nconversion used to be exactly linear but after T124 we need a\nconversion table to support non-linear cases. We would also need\nanother table to convert swgroup ID to HOTRESET bit.\n\nSigned-off-by: Hiroshi Doyu <hdoyu@nvidia.com>\n---\n drivers/iommu/tegra-smmu.c | 21 ++++++++++++++++++---\n 1 file changed, 18 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c\nindex 20dddc305fb2..080dbda874e5 100644\n--- a/drivers/iommu/tegra-smmu.c\n+++ b/drivers/iommu/tegra-smmu.c\n@@ -184,8 +184,6 @@ enum {\n #define __smmu_client_enable_swgroups(c, m) __smmu_client_set_swgroups(c, m, 1)\n #define __smmu_client_disable_swgroups(c) __smmu_client_set_swgroups(c, 0, 0)\n \n-#define SWGROUPS_ASID_REG(x) ((x) * sizeof(u32) + SMMU_ASID_BASE)\n-\n /*\n * Per client for address space\n */\n@@ -314,6 +312,23 @@ static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)\n */\n #define FLUSH_SMMU_REGS(smmu)\tsmmu_read(smmu, SMMU_CONFIG)\n \n+static size_t smmu_get_asid_offset(int id)\n+{\n+\tswitch (id) {\n+\tcase TEGRA_SWGROUP_DC14:\n+\t\treturn 0x490;\n+\tcase TEGRA_SWGROUP_DC12:\n+\t\treturn 0xa88;\n+\tcase TEGRA_SWGROUP_AFI...TEGRA_SWGROUP_ISP:\n+\tcase TEGRA_SWGROUP_MPE...TEGRA_SWGROUP_PPCS1:\n+\t\treturn (id - TEGRA_SWGROUP_AFI) * sizeof(u32) + SMMU_ASID_BASE;\n+\tcase TEGRA_SWGROUP_SDMMC1A...63:\n+\t\treturn (id - TEGRA_SWGROUP_SDMMC1A) * sizeof(u32) + 0xa94;\n+\t};\n+\n+\tBUG();\n+}\n+\n static struct smmu_client *find_smmu_client(struct smmu_device *smmu,\n \t\t\t\t\t struct device_node *dev_node)\n {\n@@ -415,7 +430,7 @@ static int __smmu_client_set_swgroups(struct smmu_client *c,\n \t\tmap = c->swgroups;\n \n \tfor_each_set_bit(i, map, TEGRA_SWGROUP_MAX) {\n-\t\toffs = SWGROUPS_ASID_REG(i);\n+\t\toffs = smmu_get_asid_offset(i);\n \t\tval = smmu_read(smmu, offs);\n \t\tif (on) {\n \t\t\tif (val) {\n", "prefixes": [ "PATCHv8", "14/21" ] }