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{
    "id": 354085,
    "url": "http://patchwork.ozlabs.org/api/patches/354085/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-14-git-send-email-hdoyu@nvidia.com/",
    "project": {
        "id": 21,
        "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api",
        "name": "Linux Tegra Development",
        "link_name": "linux-tegra",
        "list_id": "linux-tegra.vger.kernel.org",
        "list_email": "linux-tegra@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1401448834-32659-14-git-send-email-hdoyu@nvidia.com>",
    "list_archive_url": null,
    "date": "2014-05-30T11:20:26",
    "name": "[PATCHv8,13/21] iommu/tegra124: smmu: optionaly AHB enables SMMU",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "e32672f334bbaf74466cf13e3fa3e564d22513dd",
    "submitter": {
        "id": 10265,
        "url": "http://patchwork.ozlabs.org/api/people/10265/?format=api",
        "name": "Hiroshi Doyu",
        "email": "hdoyu@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-14-git-send-email-hdoyu@nvidia.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/354085/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/354085/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-tegra-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 2C62A1400E2\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 30 May 2014 21:20:52 +1000 (EST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754740AbaE3LUs (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 30 May 2014 07:20:48 -0400",
            "from hqemgate15.nvidia.com ([216.228.121.64]:17138 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753393AbaE3LUq (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tFri, 30 May 2014 07:20:46 -0400",
            "from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com\n\tid <B538869830000>; Fri, 30 May 2014 04:20:35 -0700",
            "from hqemhub01.nvidia.com ([172.20.12.94])\n\tby hqnvupgp07.nvidia.com (PGP Universal service);\n\tFri, 30 May 2014 04:13:33 -0700",
            "from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com\n\t(172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 04:20:46 -0700",
            "from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com\n\t(10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 13:20:42 +0200"
        ],
        "X-PGP-Universal": "processed;\n\tby hqnvupgp07.nvidia.com on Fri, 30 May 2014 04:13:33 -0700",
        "From": "Hiroshi Doyu <hdoyu@nvidia.com>",
        "To": "<linux-tegra@vger.kernel.org>",
        "Subject": "[PATCHv8 13/21] iommu/tegra124: smmu: optionaly AHB enables SMMU",
        "Date": "Fri, 30 May 2014 14:20:26 +0300",
        "Message-ID": "<1401448834-32659-14-git-send-email-hdoyu@nvidia.com>",
        "X-Mailer": "git-send-email 2.0.0.rc1.15.g7e76a2f",
        "In-Reply-To": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>",
        "References": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>",
        "X-NVConfidentiality": "public",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "Sender": "linux-tegra-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-tegra.vger.kernel.org>",
        "X-Mailing-List": "linux-tegra@vger.kernel.org"
    },
    "content": "SMMU used to depend on AHB bus. AHB driver needs to be populated and\nAHB_XBAR_CTRL_SMMU_INIT_DONE bit needs to be set earliear than SMMU\nbeing populated. Later Tegra SoC (>= T124) doesn't need AHB to enable\nSMMU on AHB_XBAR_CTRL for AHB_XBAR_CTRL_SMMU_INIT_DONE any more. This\nsetting bit is now optional, depending on DT passing ahb phandle or\nnot.\n\nSigned-off-by: Hiroshi Doyu <hdoyu@nvidia.com>\n---\n drivers/iommu/tegra-smmu.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)",
    "diff": "diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c\nindex 4a326476c364..20dddc305fb2 100644\n--- a/drivers/iommu/tegra-smmu.c\n+++ b/drivers/iommu/tegra-smmu.c\n@@ -499,7 +499,10 @@ static int smmu_setup_regs(struct smmu_device *smmu)\n \n \tsmmu_flush_regs(smmu, 1);\n \n-\treturn tegra_ahb_enable_smmu(smmu->ahb);\n+\tif (smmu->ahb)\n+\t\treturn tegra_ahb_enable_smmu(smmu->ahb);\n+\n+\treturn 0;\n }\n \n static void flush_ptc_and_tlb(struct smmu_device *smmu,\n@@ -1283,9 +1286,6 @@ static int tegra_smmu_probe(struct platform_device *pdev)\n \t\treturn -EINVAL;\n \n \tsmmu->ahb = of_parse_phandle(dev->of_node, \"nvidia,ahb\", 0);\n-\tif (!smmu->ahb)\n-\t\treturn -ENODEV;\n-\n \tsmmu->iommu.dev = dev;\n \tsmmu->num_as = asids;\n \tsmmu->iovmm_base = base;\n",
    "prefixes": [
        "PATCHv8",
        "13/21"
    ]
}