Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 354083,
    "url": "http://patchwork.ozlabs.org/api/patches/354083/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-12-git-send-email-hdoyu@nvidia.com/",
    "project": {
        "id": 21,
        "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api",
        "name": "Linux Tegra Development",
        "link_name": "linux-tegra",
        "list_id": "linux-tegra.vger.kernel.org",
        "list_email": "linux-tegra@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1401448834-32659-12-git-send-email-hdoyu@nvidia.com>",
    "list_archive_url": null,
    "date": "2014-05-30T11:20:24",
    "name": "[PATCHv8,11/21] iommu/tegra: smmu: Rename hwgrp -> swgroups",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "b0a056b433d4018b775d1c71b84fab65d0f59fc2",
    "submitter": {
        "id": 10265,
        "url": "http://patchwork.ozlabs.org/api/people/10265/?format=api",
        "name": "Hiroshi Doyu",
        "email": "hdoyu@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-12-git-send-email-hdoyu@nvidia.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/354083/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/354083/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-tegra-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 075A91400D6\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 30 May 2014 21:20:51 +1000 (EST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754565AbaE3LUr (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 30 May 2014 07:20:47 -0400",
            "from hqemgate16.nvidia.com ([216.228.121.65]:3683 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753504AbaE3LUp (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tFri, 30 May 2014 07:20:45 -0400",
            "from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com\n\tid <B538869830001>; Fri, 30 May 2014 04:20:35 -0700",
            "from hqemhub01.nvidia.com ([172.20.12.94])\n\tby hqnvupgp07.nvidia.com (PGP Universal service);\n\tFri, 30 May 2014 04:13:32 -0700",
            "from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com\n\t(172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 04:20:45 -0700",
            "from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com\n\t(10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 13:20:42 +0200"
        ],
        "X-PGP-Universal": "processed;\n\tby hqnvupgp07.nvidia.com on Fri, 30 May 2014 04:13:32 -0700",
        "From": "Hiroshi Doyu <hdoyu@nvidia.com>",
        "To": "<linux-tegra@vger.kernel.org>",
        "Subject": "[PATCHv8 11/21] iommu/tegra: smmu: Rename hwgrp -> swgroups",
        "Date": "Fri, 30 May 2014 14:20:24 +0300",
        "Message-ID": "<1401448834-32659-12-git-send-email-hdoyu@nvidia.com>",
        "X-Mailer": "git-send-email 2.0.0.rc1.15.g7e76a2f",
        "In-Reply-To": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>",
        "References": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>",
        "X-NVConfidentiality": "public",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "Sender": "linux-tegra-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-tegra.vger.kernel.org>",
        "X-Mailing-List": "linux-tegra@vger.kernel.org"
    },
    "content": "Use the correct term for SWGROUP related variables and macros.\n\nThe term \"swgroup\" is the collection of \"memory client\". A \"memory\nclient\" usually represents a HardWare Accelerator(HWA) like\nGPU. Sometimes a strut device can belong to multiple \"swgroup\" so that\n\"swgroup's'\" is used here. This \"swgroups\" is the term used in Tegra\nTRM. Rename along with TRM.\n\nSigned-off-by: Hiroshi Doyu <hdoyu@nvidia.com>\n---\n drivers/iommu/tegra-smmu.c | 36 ++++++++++++++++++------------------\n 1 file changed, 18 insertions(+), 18 deletions(-)",
    "diff": "diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c\nindex caa531cb1c50..5cb0e2a2b267 100644\n--- a/drivers/iommu/tegra-smmu.c\n+++ b/drivers/iommu/tegra-smmu.c\n@@ -179,12 +179,12 @@ enum {\n \n #define NUM_SMMU_REG_BANKS\t3\n \n-#define smmu_client_enable_hwgrp(c, m)\tsmmu_client_set_hwgrp(c, m, 1)\n-#define smmu_client_disable_hwgrp(c)\tsmmu_client_set_hwgrp(c, 0, 0)\n-#define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)\n-#define __smmu_client_disable_hwgrp(c)\t__smmu_client_set_hwgrp(c, 0, 0)\n+#define smmu_client_enable_swgroups(c, m) smmu_client_set_swgroups(c, m, 1)\n+#define smmu_client_disable_swgroups(c) smmu_client_set_swgroups(c, 0, 0)\n+#define __smmu_client_enable_swgroups(c, m) __smmu_client_set_swgroups(c, m, 1)\n+#define __smmu_client_disable_swgroups(c) __smmu_client_set_swgroups(c, 0, 0)\n \n-#define HWGRP_ASID_REG(x) ((x) * sizeof(u32) + SMMU_ASID_BASE)\n+#define SWGROUPS_ASID_REG(x) ((x) * sizeof(u32) + SMMU_ASID_BASE)\n \n /*\n  * Per client for address space\n@@ -195,7 +195,7 @@ struct smmu_client {\n \tstruct device\t\t*dev;\n \tstruct list_head\tlist;\n \tstruct smmu_as\t\t*as;\n-\tunsigned long\t\thwgrp[2];\n+\tunsigned long\t\tswgroups[2];\n };\n \n /*\n@@ -377,7 +377,7 @@ static int register_smmu_client(struct smmu_device *smmu,\n \n \tclient->dev = dev;\n \tclient->of_node = dev->of_node;\n-\tmemcpy(client->hwgrp, swgroups, sizeof(u64));\n+\tmemcpy(client->swgroups, swgroups, sizeof(u64));\n \treturn insert_smmu_client(smmu, client);\n }\n \n@@ -402,7 +402,7 @@ static int smmu_of_get_swgroups(struct device *dev, unsigned long *swgroups)\n \treturn -ENODEV;\n }\n \n-static int __smmu_client_set_hwgrp(struct smmu_client *c,\n+static int __smmu_client_set_swgroups(struct smmu_client *c,\n \t\t\t\t   unsigned long *map, int on)\n {\n \tint i;\n@@ -411,10 +411,10 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c,\n \tstruct smmu_device *smmu = as->smmu;\n \n \tif (!on)\n-\t\tmap = c->hwgrp;\n+\t\tmap = c->swgroups;\n \n \tfor_each_set_bit(i, map, TEGRA_SWGROUP_MAX) {\n-\t\toffs = HWGRP_ASID_REG(i);\n+\t\toffs = SWGROUPS_ASID_REG(i);\n \t\tval = smmu_read(smmu, offs);\n \t\tif (on) {\n \t\t\tif (val) {\n@@ -424,7 +424,7 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c,\n \t\t\t}\n \n \t\t\tval = mask;\n-\t\t\tmemcpy(c->hwgrp, map, sizeof(u64));\n+\t\t\tmemcpy(c->swgroups, map, sizeof(u64));\n \t\t} else {\n \t\t\tWARN_ON((val & mask) == mask);\n \t\t\tval &= ~mask;\n@@ -437,7 +437,7 @@ skip:\n \treturn 0;\n }\n \n-static int smmu_client_set_hwgrp(struct smmu_client *c,\n+static int smmu_client_set_swgroups(struct smmu_client *c,\n \t\t\t\t unsigned long *map, int on)\n {\n \tint err;\n@@ -446,7 +446,7 @@ static int smmu_client_set_hwgrp(struct smmu_client *c,\n \tstruct smmu_device *smmu = as->smmu;\n \n \tspin_lock_irqsave(&smmu->lock, flags);\n-\terr = __smmu_client_set_hwgrp(c, map, on);\n+\terr = __smmu_client_set_swgroups(c, map, on);\n \tspin_unlock_irqrestore(&smmu->lock, flags);\n \treturn err;\n }\n@@ -486,7 +486,7 @@ static int smmu_setup_regs(struct smmu_device *smmu)\n \t\tsmmu_write(smmu, val, SMMU_PTB_DATA);\n \n \t\tlist_for_each_entry(c, &as->client, list)\n-\t\t\t__smmu_client_set_hwgrp(c, c->hwgrp, 1);\n+\t\t\t__smmu_client_set_swgroups(c, c->swgroups, 1);\n \t}\n \n \tsmmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0);\n@@ -814,7 +814,7 @@ static int smmu_iommu_attach_dev(struct iommu_domain *domain,\n \t\treturn -ENOMEM;\n \n \tclient->as = as;\n-\terr = smmu_client_enable_hwgrp(client, client->hwgrp);\n+\terr = smmu_client_enable_swgroups(client, client->swgroups);\n \tif (err)\n \t\treturn -EINVAL;\n \n@@ -834,7 +834,7 @@ static int smmu_iommu_attach_dev(struct iommu_domain *domain,\n \t * Reserve \"page zero\" for AVP vectors using a common dummy\n \t * page.\n \t */\n-\tif (test_bit(TEGRA_SWGROUP_AVPC, client->hwgrp)) {\n+\tif (test_bit(TEGRA_SWGROUP_AVPC, client->swgroups)) {\n \t\tstruct page *page;\n \n \t\tpage = as->smmu->avp_vector_page;\n@@ -847,7 +847,7 @@ static int smmu_iommu_attach_dev(struct iommu_domain *domain,\n \treturn 0;\n \n err_client:\n-\tsmmu_client_disable_hwgrp(client);\n+\tsmmu_client_disable_swgroups(client);\n \tspin_unlock(&as->client_lock);\n \treturn err;\n }\n@@ -863,7 +863,7 @@ static void smmu_iommu_detach_dev(struct iommu_domain *domain,\n \n \tlist_for_each_entry(c, &as->client, list) {\n \t\tif (c->dev == dev) {\n-\t\t\tsmmu_client_disable_hwgrp(c);\n+\t\t\tsmmu_client_disable_swgroups(c);\n \t\t\tlist_del(&c->list);\n \t\t\tc->as = NULL;\n \t\t\tdev_dbg(smmu->dev,\n",
    "prefixes": [
        "PATCHv8",
        "11/21"
    ]
}