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GET /api/patches/354080/?format=api
{ "id": 354080, "url": "http://patchwork.ozlabs.org/api/patches/354080/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-9-git-send-email-hdoyu@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1401448834-32659-9-git-send-email-hdoyu@nvidia.com>", "list_archive_url": null, "date": "2014-05-30T11:20:21", "name": "[PATCHv8,08/21] iommu/tegra: smmu: calculate ASID register offset by ID", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d8fe127eb4f131ffedb12ff8582458e3d767345f", "submitter": { "id": 10265, "url": "http://patchwork.ozlabs.org/api/people/10265/?format=api", "name": "Hiroshi Doyu", "email": "hdoyu@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-9-git-send-email-hdoyu@nvidia.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/354080/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/354080/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-tegra-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 47DB21400E2\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 30 May 2014 21:20:49 +1000 (EST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753588AbaE3LUq (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 30 May 2014 07:20:46 -0400", "from hqemgate14.nvidia.com ([216.228.121.143]:12085 \"EHLO\n\thqemgate14.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752887AbaE3LUo (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tFri, 30 May 2014 07:20:44 -0400", "from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate14.nvidia.com\n\tid <B5388699e0000>; Fri, 30 May 2014 04:21:02 -0700", "from hqemhub01.nvidia.com ([172.20.12.94])\n\tby hqnvupgp07.nvidia.com (PGP Universal service);\n\tFri, 30 May 2014 04:13:31 -0700", "from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com\n\t(172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 04:20:43 -0700", "from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com\n\t(10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 13:20:41 +0200" ], "X-PGP-Universal": "processed;\n\tby hqnvupgp07.nvidia.com on Fri, 30 May 2014 04:13:31 -0700", "From": "Hiroshi Doyu <hdoyu@nvidia.com>", "To": "<linux-tegra@vger.kernel.org>", "Subject": "[PATCHv8 08/21] iommu/tegra: smmu: calculate ASID register offset\n\tby ID", "Date": "Fri, 30 May 2014 14:20:21 +0300", "Message-ID": "<1401448834-32659-9-git-send-email-hdoyu@nvidia.com>", "X-Mailer": "git-send-email 2.0.0.rc1.15.g7e76a2f", "In-Reply-To": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "References": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "Sender": "linux-tegra-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-tegra.vger.kernel.org>", "X-Mailing-List": "linux-tegra@vger.kernel.org" }, "content": "ASID register offset is caclulated by SWGROUP ID so that we can get\nrid of old SoC specific MACROs. This ID conversion is needed for the\nunified SMMU driver over Tegra SoCs. We use dt-bindings MACRO instead\nof SoC dependent MACROs. The formula is:\n\n MC_SMMU_<swgroup name>_ASID_0 = MC_SMMU_AFI_ASID_0 + ID * 4;\n\nNow SWGROUP ID is the global HardWare Accelerator(HWA) identifier\namong all Tegra SoC except Tegra2.\n\nSigned-off-by: Hiroshi Doyu <hdoyu@nvidia.com>\n---\n drivers/iommu/tegra-smmu.c | 111 +++++++--------------------------------------\n 1 file changed, 17 insertions(+), 94 deletions(-)", "diff": "diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c\nindex ae5a1e7b48af..fe351cdd5c05 100644\n--- a/drivers/iommu/tegra-smmu.c\n+++ b/drivers/iommu/tegra-smmu.c\n@@ -43,46 +43,6 @@\n \n #include <dt-bindings/memory/tegra-swgroup.h>\n \n-enum smmu_hwgrp {\n-\tHWGRP_AFI,\n-\tHWGRP_AVPC,\n-\tHWGRP_DC,\n-\tHWGRP_DCB,\n-\tHWGRP_EPP,\n-\tHWGRP_G2,\n-\tHWGRP_HC,\n-\tHWGRP_HDA,\n-\tHWGRP_ISP,\n-\tHWGRP_MPE,\n-\tHWGRP_NV,\n-\tHWGRP_NV2,\n-\tHWGRP_PPCS,\n-\tHWGRP_SATA,\n-\tHWGRP_VDE,\n-\tHWGRP_VI,\n-\n-\tHWGRP_COUNT,\n-\n-\tHWGRP_END = ~0,\n-};\n-\n-#define HWG_AFI\t\t(1 << HWGRP_AFI)\n-#define HWG_AVPC\t(1 << HWGRP_AVPC)\n-#define HWG_DC\t\t(1 << HWGRP_DC)\n-#define HWG_DCB\t\t(1 << HWGRP_DCB)\n-#define HWG_EPP\t\t(1 << HWGRP_EPP)\n-#define HWG_G2\t\t(1 << HWGRP_G2)\n-#define HWG_HC\t\t(1 << HWGRP_HC)\n-#define HWG_HDA\t\t(1 << HWGRP_HDA)\n-#define HWG_ISP\t\t(1 << HWGRP_ISP)\n-#define HWG_MPE\t\t(1 << HWGRP_MPE)\n-#define HWG_NV\t\t(1 << HWGRP_NV)\n-#define HWG_NV2\t\t(1 << HWGRP_NV2)\n-#define HWG_PPCS\t(1 << HWGRP_PPCS)\n-#define HWG_SATA\t(1 << HWGRP_SATA)\n-#define HWG_VDE\t\t(1 << HWGRP_VDE)\n-#define HWG_VI\t\t(1 << HWGRP_VI)\n-\n /* bitmap of the page sizes currently supported */\n #define SMMU_IOMMU_PGSIZES\t(SZ_4K)\n \n@@ -152,21 +112,7 @@ enum {\n #define SMMU_TRANSLATION_ENABLE_2\t\t0x230\n \n #define SMMU_AFI_ASID\t0x238 /* PCIE */\n-#define SMMU_AVPC_ASID\t0x23c /* AVP */\n-#define SMMU_DC_ASID\t0x240 /* Display controller */\n-#define SMMU_DCB_ASID\t0x244 /* Display controller B */\n-#define SMMU_EPP_ASID\t0x248 /* Encoder pre-processor */\n-#define SMMU_G2_ASID\t0x24c /* 2D engine */\n-#define SMMU_HC_ASID\t0x250 /* Host1x */\n-#define SMMU_HDA_ASID\t0x254 /* High-def audio */\n-#define SMMU_ISP_ASID\t0x258 /* Image signal processor */\n-#define SMMU_MPE_ASID\t0x264 /* MPEG encoder */\n-#define SMMU_NV_ASID\t0x268 /* (3D) */\n-#define SMMU_NV2_ASID\t0x26c /* (3D) */\n-#define SMMU_PPCS_ASID\t0x270 /* AHB */\n-#define SMMU_SATA_ASID\t0x278 /* SATA */\n-#define SMMU_VDE_ASID\t0x27c /* Video decoder */\n-#define SMMU_VI_ASID\t0x280 /* Video input */\n+#define SMMU_ASID_BASE\tSMMU_AFI_ASID\n \n #define SMMU_PDE_NEXT_SHIFT\t\t28\n \n@@ -238,27 +184,7 @@ enum {\n #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)\n #define __smmu_client_disable_hwgrp(c)\t__smmu_client_set_hwgrp(c, 0, 0)\n \n-#define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID\n-\n-static const u32 smmu_hwgrp_asid_reg[] = {\n-\tHWGRP_INIT(AFI),\n-\tHWGRP_INIT(AVPC),\n-\tHWGRP_INIT(DC),\n-\tHWGRP_INIT(DCB),\n-\tHWGRP_INIT(EPP),\n-\tHWGRP_INIT(G2),\n-\tHWGRP_INIT(HC),\n-\tHWGRP_INIT(HDA),\n-\tHWGRP_INIT(ISP),\n-\tHWGRP_INIT(MPE),\n-\tHWGRP_INIT(NV),\n-\tHWGRP_INIT(NV2),\n-\tHWGRP_INIT(PPCS),\n-\tHWGRP_INIT(SATA),\n-\tHWGRP_INIT(VDE),\n-\tHWGRP_INIT(VI),\n-};\n-#define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])\n+#define HWGRP_ASID_REG(x) ((x) * sizeof(u32) + SMMU_ASID_BASE)\n \n /*\n * Per client for address space\n@@ -267,7 +193,7 @@ struct smmu_client {\n \tstruct device\t\t*dev;\n \tstruct list_head\tlist;\n \tstruct smmu_as\t\t*as;\n-\tu32\t\t\thwgrp;\n+\tunsigned long\t\thwgrp[2];\n };\n \n /*\n@@ -384,41 +310,37 @@ static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)\n */\n #define FLUSH_SMMU_REGS(smmu)\tsmmu_read(smmu, SMMU_CONFIG)\n \n-#define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)\n-\n static int __smmu_client_set_hwgrp(struct smmu_client *c,\n-\t\t\t\t unsigned long map, int on)\n+\t\t\t\t unsigned long *map, int on)\n {\n \tint i;\n \tstruct smmu_as *as = c->as;\n \tu32 val, offs, mask = SMMU_ASID_ENABLE(as->asid);\n \tstruct smmu_device *smmu = as->smmu;\n \n-\tWARN_ON(!on && map);\n-\tif (on && !map)\n-\t\treturn -EINVAL;\n \tif (!on)\n-\t\tmap = smmu_client_hwgrp(c);\n+\t\tmap = c->hwgrp;\n \n-\tfor_each_set_bit(i, &map, HWGRP_COUNT) {\n+\tfor_each_set_bit(i, map, TEGRA_SWGROUP_MAX) {\n \t\toffs = HWGRP_ASID_REG(i);\n \t\tval = smmu_read(smmu, offs);\n \t\tif (on) {\n \t\t\tif (WARN_ON(val & mask))\n \t\t\t\tgoto err_hw_busy;\n \t\t\tval |= mask;\n+\t\t\tmemcpy(c->hwgrp, map, sizeof(u64));\n \t\t} else {\n \t\t\tWARN_ON((val & mask) == mask);\n \t\t\tval &= ~mask;\n \t\t}\n \t\tsmmu_write(smmu, val, offs);\n \t}\n+\n \tFLUSH_SMMU_REGS(smmu);\n-\tc->hwgrp = map;\n \treturn 0;\n \n err_hw_busy:\n-\tfor_each_set_bit(i, &map, HWGRP_COUNT) {\n+\tfor_each_set_bit(i, map, TEGRA_SWGROUP_MAX) {\n \t\toffs = HWGRP_ASID_REG(i);\n \t\tval = smmu_read(smmu, offs);\n \t\tval &= ~mask;\n@@ -427,17 +349,18 @@ err_hw_busy:\n \treturn -EBUSY;\n }\n \n-static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on)\n+static int smmu_client_set_hwgrp(struct smmu_client *c,\n+\t\t\t\t unsigned long *map, int on)\n {\n-\tu32 val;\n+\tint err;\n \tunsigned long flags;\n \tstruct smmu_as *as = c->as;\n \tstruct smmu_device *smmu = as->smmu;\n \n \tspin_lock_irqsave(&smmu->lock, flags);\n-\tval = __smmu_client_set_hwgrp(c, map, on);\n+\terr = __smmu_client_set_hwgrp(c, map, on);\n \tspin_unlock_irqrestore(&smmu->lock, flags);\n-\treturn val;\n+\treturn err;\n }\n \n /*\n@@ -796,7 +719,7 @@ static int smmu_iommu_attach_dev(struct iommu_domain *domain,\n \tstruct smmu_as *as = domain->priv;\n \tstruct smmu_device *smmu = as->smmu;\n \tstruct smmu_client *client, *c;\n-\tu32 map;\n+\tunsigned long *map;\n \tint err;\n \n \tclient = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL);\n@@ -804,7 +727,7 @@ static int smmu_iommu_attach_dev(struct iommu_domain *domain,\n \t\treturn -ENOMEM;\n \tclient->dev = dev;\n \tclient->as = as;\n-\tmap = (unsigned long)dev->platform_data;\n+\tmap = (unsigned long *)dev->platform_data;\n \tif (!map)\n \t\treturn -EINVAL;\n \n@@ -828,7 +751,7 @@ static int smmu_iommu_attach_dev(struct iommu_domain *domain,\n \t * Reserve \"page zero\" for AVP vectors using a common dummy\n \t * page.\n \t */\n-\tif (map & HWG_AVPC) {\n+\tif (test_bit(TEGRA_SWGROUP_AVPC, map)) {\n \t\tstruct page *page;\n \n \t\tpage = as->smmu->avp_vector_page;\n", "prefixes": [ "PATCHv8", "08/21" ] }