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GET /api/patches/354079/?format=api
{ "id": 354079, "url": "http://patchwork.ozlabs.org/api/patches/354079/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-8-git-send-email-hdoyu@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1401448834-32659-8-git-send-email-hdoyu@nvidia.com>", "list_archive_url": null, "date": "2014-05-30T11:20:20", "name": "[PATCHv8,07/21] iommu/tegra: smmu: register device to iommu dynamically", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "37001b53b0fc76431a5fdbb410efa5ebf0f3f760", "submitter": { "id": 10265, "url": "http://patchwork.ozlabs.org/api/people/10265/?format=api", "name": "Hiroshi Doyu", "email": "hdoyu@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-8-git-send-email-hdoyu@nvidia.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/354079/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/354079/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-tegra-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 970801400D6\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 30 May 2014 21:20:48 +1000 (EST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752220AbaE3LUp (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 30 May 2014 07:20:45 -0400", "from hqemgate15.nvidia.com ([216.228.121.64]:17135 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751291AbaE3LUo (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tFri, 30 May 2014 07:20:44 -0400", "from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com\n\tid <B538869810000>; Fri, 30 May 2014 04:20:33 -0700", "from hqemhub01.nvidia.com ([172.20.12.94])\n\tby hqnvupgp08.nvidia.com (PGP Universal service);\n\tFri, 30 May 2014 04:15:40 -0700", "from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com\n\t(172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 04:20:43 -0700", "from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com\n\t(10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 13:20:40 +0200" ], "X-PGP-Universal": "processed;\n\tby hqnvupgp08.nvidia.com on Fri, 30 May 2014 04:15:40 -0700", "From": "Hiroshi Doyu <hdoyu@nvidia.com>", "To": "<linux-tegra@vger.kernel.org>", "Subject": "[PATCHv8 07/21] iommu/tegra: smmu: register device to iommu\n\tdynamically", "Date": "Fri, 30 May 2014 14:20:20 +0300", "Message-ID": "<1401448834-32659-8-git-send-email-hdoyu@nvidia.com>", "X-Mailer": "git-send-email 2.0.0.rc1.15.g7e76a2f", "In-Reply-To": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "References": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "Sender": "linux-tegra-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-tegra.vger.kernel.org>", "X-Mailing-List": "linux-tegra@vger.kernel.org" }, "content": "platform_devices are registered as IOMMU'able dynamically via\nadd_device() and remove_device().\n\nTegra SMMU can have multiple address spaces(AS). IOMMU'able devices\ncan belong to one of them. Multiple IOVA maps are created at boot-up,\nwhich can be attached to devices later. We reserve 2 of them for\nstatic assignment, AS[0] for system default, AS[1] for AHB clusters as\nprotected domain from others, where there are many traditional\npheripheral devices like USB, SD/MMC. They should be isolated from\nsome smart devices like host1x for system robustness. Even if smart\ndevices behaves wrongly, the traditional devices(SD/MMC, USB) wouldn't\nbe affected, and the system could continue most likely. DMA API(ARM)\nneeds ARM_DMA_USE_IOMMU to be enabled.\n\nSigned-off-by: Hiroshi Doyu <hdoyu@nvidia.com>\n---\n drivers/iommu/Kconfig | 1 +\n drivers/iommu/tegra-smmu.c | 70 +++++++++++++++++++++++++++++++++++++++++++++-\n 2 files changed, 70 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig\nindex d260605e6d5f..ed4aba0b62eb 100644\n--- a/drivers/iommu/Kconfig\n+++ b/drivers/iommu/Kconfig\n@@ -170,6 +170,7 @@ config TEGRA_IOMMU_SMMU\n \tbool \"Tegra SMMU IOMMU Support\"\n \tdepends on ARCH_TEGRA && TEGRA_AHB\n \tselect IOMMU_API\n+\tselect ARM_DMA_USE_IOMMU\n \thelp\n \t Enables support for remapping discontiguous physical memory\n \t shared with the operating system into contiguous I/O virtual\ndiff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c\nindex 605b5b46a903..ae5a1e7b48af 100644\n--- a/drivers/iommu/tegra-smmu.c\n+++ b/drivers/iommu/tegra-smmu.c\n@@ -39,6 +39,9 @@\n \n #include <asm/page.h>\n #include <asm/cacheflush.h>\n+#include <asm/dma-iommu.h>\n+\n+#include <dt-bindings/memory/tegra-swgroup.h>\n \n enum smmu_hwgrp {\n \tHWGRP_AFI,\n@@ -319,6 +322,8 @@ struct smmu_device {\n \n \tstruct device_node *ahb;\n \n+\tstruct dma_iommu_mapping **map;\n+\n \tint\t\tnum_as;\n \tstruct smmu_as\tas[0];\t\t/* Run-time allocated array */\n };\n@@ -947,6 +952,44 @@ static void smmu_iommu_domain_destroy(struct iommu_domain *domain)\n \tdev_dbg(smmu->dev, \"smmu_as@%p\\n\", as);\n }\n \n+/*\n+ * ASID[0] for the system default\n+ * ASID[1] for PPCS(\"AHB bus children\"), which has SDMMC\n+ * ASID[2][3].. open for drivers, first come, first served.\n+ */\n+enum {\n+\tSYSTEM_DEFAULT,\n+\tSYSTEM_PROTECTED,\n+\tNUM_OF_STATIC_MAPS,\n+};\n+\n+static int smmu_iommu_bound_driver(struct device *dev)\n+{\n+\tint err = -EPROBE_DEFER;\n+\tu32 swgroups = dev->platform_data;\n+\tstruct dma_iommu_mapping *map = NULL;\n+\n+\tif (test_bit(TEGRA_SWGROUP_PPCS, swgroups))\n+\t\tmap = smmu_handle->map[SYSTEM_PROTECTED];\n+\telse\n+\t\tmap = smmu_handle->map[SYSTEM_DEFAULT];\n+\n+\tif (map)\n+\t\terr = arm_iommu_attach_device(dev, map);\n+\telse\n+\t\treturn -EPROBE_DEFER;\n+\n+\tpr_debug(\"swgroups=%08lx map=%p err=%d %s\\n\",\n+\t\t swgroups, map, err, dev_name(dev));\n+\treturn err;\n+}\n+\n+static void smmu_iommu_unbind_driver(struct device *dev)\n+{\n+\tdev_dbg(dev, \"Detaching from map %p\\n\", to_dma_iommu_mapping(dev));\n+\tarm_iommu_detach_device(dev);\n+}\n+\n static struct iommu_ops smmu_iommu_ops = {\n \t.domain_init\t= smmu_iommu_domain_init,\n \t.domain_destroy\t= smmu_iommu_domain_destroy,\n@@ -956,6 +999,8 @@ static struct iommu_ops smmu_iommu_ops = {\n \t.unmap\t\t= smmu_iommu_unmap,\n \t.iova_to_phys\t= smmu_iommu_iova_to_phys,\n \t.domain_has_cap\t= smmu_iommu_domain_has_cap,\n+\t.bound_driver\t= smmu_iommu_bound_driver,\n+\t.unbind_driver\t= smmu_iommu_unbind_driver,\n \t.pgsize_bitmap\t= SMMU_IOMMU_PGSIZES,\n };\n \n@@ -1144,6 +1189,23 @@ static int tegra_smmu_resume(struct device *dev)\n \treturn err;\n }\n \n+static void tegra_smmu_create_default_map(struct smmu_device *smmu)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < smmu->num_as; i++) {\n+\t\tdma_addr_t base = smmu->iovmm_base;\n+\t\tsize_t size = smmu->page_count << PAGE_SHIFT;\n+\n+\t\tsmmu->map[i] = arm_iommu_create_mapping(&platform_bus_type,\n+\t\t\t\t\t\t\tbase, size);\n+\t\tif (IS_ERR(smmu->map[i]))\n+\t\t\tdev_err(smmu->dev,\n+\t\t\t\t\"Couldn't create: asid=%d map=%p %pa-%pa\\n\",\n+\t\t\t\ti, smmu->map[i], &base, &base + size - 1);\n+\t}\n+}\n+\n static int tegra_smmu_probe(struct platform_device *pdev)\n {\n \tstruct smmu_device *smmu;\n@@ -1160,13 +1222,18 @@ static int tegra_smmu_probe(struct platform_device *pdev)\n \tif (of_property_read_u32(dev->of_node, \"nvidia,#asids\", &asids))\n \t\treturn -ENODEV;\n \n-\tbytes = sizeof(*smmu) + asids * sizeof(*smmu->as);\n+\tif (asids < NUM_OF_STATIC_MAPS)\n+\t\treturn -EINVAL;\n+\n+\tbytes = sizeof(*smmu) + asids * (sizeof(*smmu->as) +\n+\t\t\t\t\t sizeof(struct dma_iommu_mapping *));\n \tsmmu = devm_kzalloc(dev, bytes, GFP_KERNEL);\n \tif (!smmu) {\n \t\tdev_err(dev, \"failed to allocate smmu_device\\n\");\n \t\treturn -ENOMEM;\n \t}\n \n+\tsmmu->map = (struct dma_iommu_mapping **)(smmu->as + asids);\n \tsmmu->nregs = pdev->num_resources;\n \tsmmu->regs = devm_kzalloc(dev, 2 * smmu->nregs * sizeof(*smmu->regs),\n \t\t\t\t GFP_KERNEL);\n@@ -1236,6 +1303,7 @@ static int tegra_smmu_probe(struct platform_device *pdev)\n \tsmmu_debugfs_create(smmu);\n \tsmmu_handle = smmu;\n \tbus_set_iommu(&platform_bus_type, &smmu_iommu_ops);\n+\ttegra_smmu_create_default_map(smmu);\n \treturn 0;\n }\n \n", "prefixes": [ "PATCHv8", "07/21" ] }