Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 354074,
    "url": "http://patchwork.ozlabs.org/api/patches/354074/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-5-git-send-email-hdoyu@nvidia.com/",
    "project": {
        "id": 21,
        "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api",
        "name": "Linux Tegra Development",
        "link_name": "linux-tegra",
        "list_id": "linux-tegra.vger.kernel.org",
        "list_email": "linux-tegra@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1401448834-32659-5-git-send-email-hdoyu@nvidia.com>",
    "list_archive_url": null,
    "date": "2014-05-30T11:20:17",
    "name": "[PATCHv8,04/21] driver/core: populate devices in order for IOMMUs",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "4859707e9c2b9bddff1d306c265776278489a89d",
    "submitter": {
        "id": 10265,
        "url": "http://patchwork.ozlabs.org/api/people/10265/?format=api",
        "name": "Hiroshi Doyu",
        "email": "hdoyu@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-5-git-send-email-hdoyu@nvidia.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/354074/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/354074/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-tegra-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id C53301400E5\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 30 May 2014 21:20:45 +1000 (EST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751745AbaE3LUn (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 30 May 2014 07:20:43 -0400",
            "from hqemgate16.nvidia.com ([216.228.121.65]:3679 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752220AbaE3LUm (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tFri, 30 May 2014 07:20:42 -0400",
            "from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com\n\tid <B538869800000>; Fri, 30 May 2014 04:20:32 -0700",
            "from hqemhub01.nvidia.com ([172.20.12.94])\n\tby hqnvupgp07.nvidia.com (PGP Universal service);\n\tFri, 30 May 2014 04:13:29 -0700",
            "from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com\n\t(172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 04:20:42 -0700",
            "from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com\n\t(10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 13:20:39 +0200"
        ],
        "X-PGP-Universal": "processed;\n\tby hqnvupgp07.nvidia.com on Fri, 30 May 2014 04:13:29 -0700",
        "From": "Hiroshi Doyu <hdoyu@nvidia.com>",
        "To": "<linux-tegra@vger.kernel.org>",
        "Subject": "[PATCHv8 04/21] driver/core: populate devices in order for IOMMUs",
        "Date": "Fri, 30 May 2014 14:20:17 +0300",
        "Message-ID": "<1401448834-32659-5-git-send-email-hdoyu@nvidia.com>",
        "X-Mailer": "git-send-email 2.0.0.rc1.15.g7e76a2f",
        "In-Reply-To": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>",
        "References": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>",
        "X-NVConfidentiality": "public",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "Sender": "linux-tegra-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-tegra.vger.kernel.org>",
        "X-Mailing-List": "linux-tegra@vger.kernel.org"
    },
    "content": "IOMMU devices on the bus need to be poplulated first, then iommu\nmaster devices are done later.\n\nWith CONFIG_OF_IOMMU, \"iommus=\" DT binding would be used to identify\nwhether a device can be an iommu msater or not. If a device can, we'll\ndefer to populate that device till an iommu device is populated. Then,\nthose deferred iommu master devices are populated and configured with\nhelp of the already populated iommu device.\n\nSigned-off-by: Hiroshi Doyu <hdoyu@nvidia.com>\nCc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>\n---\n drivers/base/dd.c | 5 +++++\n 1 file changed, 5 insertions(+)",
    "diff": "diff --git a/drivers/base/dd.c b/drivers/base/dd.c\nindex 62ec61e8f84a..ef5069d03831 100644\n--- a/drivers/base/dd.c\n+++ b/drivers/base/dd.c\n@@ -25,6 +25,7 @@\n #include <linux/async.h>\n #include <linux/pm_runtime.h>\n #include <linux/pinctrl/devinfo.h>\n+#include <linux/of_iommu.h>\n \n #include \"base.h\"\n #include \"power/power.h\"\n@@ -287,6 +288,10 @@ static int really_probe(struct device *dev, struct device_driver *drv)\n \n \tdev->driver = drv;\n \n+\tret = of_iommu_attach(dev);\n+\tif (ret)\n+\t\tgoto probe_failed;\n+\n \t/* If using pinctrl, bind pins now before probing */\n \tret = pinctrl_bind_pins(dev);\n \tif (ret)\n",
    "prefixes": [
        "PATCHv8",
        "04/21"
    ]
}