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GET /api/patches/335250/?format=api
{ "id": 335250, "url": "http://patchwork.ozlabs.org/api/patches/335250/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1396260336-2785-1-git-send-email-prabhakar@freescale.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1396260336-2785-1-git-send-email-prabhakar@freescale.com>", "list_archive_url": null, "date": "2014-03-31T10:05:36", "name": "[U-Boot,10/10] board/t104xrdb: Add support of NAND, SD, SPI boot for T1040RDB", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "c14787a5751b756cb5f94668e783d301a75edcfc", "submitter": { "id": 6576, "url": "http://patchwork.ozlabs.org/api/people/6576/?format=api", "name": "Prabhakar Kushwaha", "email": "prabhakar@freescale.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1396260336-2785-1-git-send-email-prabhakar@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/335250/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/335250/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 432BE1400B2\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 31 Mar 2014 21:06:26 +1100 (EST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id CB8384B669;\n\tMon, 31 Mar 2014 12:06:24 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id O06Pcu8+JP+J; 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Mon, 31 Mar 2014 10:05:54 +0000 (UTC)", "from mail205-tx2 (localhost.localdomain [127.0.0.1]) by mail205-tx2\n\t(MessageSwitch) id 1396260352896041_22132;\n\tMon, 31 Mar 2014 10:05:52 +0000 (UTC)", "from TX2EHSMHS020.bigfish.com (unknown [10.9.14.239])\tby\n\tmail205-tx2.bigfish.com (Postfix) with ESMTP id EB3AB3E006C;\n\tMon, 31 Mar 2014 10:05:47 +0000 (UTC)", "from mail.freescale.net (70.37.183.190) by TX2EHSMHS020.bigfish.com\n\t(10.9.99.120) with Microsoft SMTP Server (TLS) id 14.1.225.23;\n\tMon, 31 Mar 2014 10:05:44 +0000", "from tx30smr01.am.freescale.net (10.81.153.31) by\n\t039-SN1MMR1-004.039d.mgd.msft.net (10.84.1.14) with Microsoft SMTP\n\tServer (TLS) id 14.3.158.2; Mon, 31 Mar 2014 10:05:43 +0000", "from b32579-VirtualBox.ap.freescale.net\n\t(B32579-02-010232132051.ap.freescale.net [10.232.132.51])\tby\n\ttx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\ts2VA5bvi027515; Mon, 31 Mar 2014 03:05:41 -0700" ], "X-Virus-Scanned": [ "Debian amavisd-new at theia.denx.de", "Debian amavisd-new at theia.denx.de" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "X-Forefront-Antispam-Report": "CIP:70.37.183.190; KIP:(null); UIP:(null);\n\tIPV:NLI; \n\tH:mail.freescale.net; RD:none; EFVD:NLI", "X-SpamScore": "0", "X-BigFish": "VS0(zze0eahzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah21bch1fc6hzz1de098h17326ah8275bh8275dh1de097h186068hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h24afh2327h2336h2438h2461h2487h24d7h2516h2545h255eh25cch25f6h2605h268bh1155h)", "From": "Prabhakar Kushwaha <prabhakar@freescale.com>", "To": "<u-boot@lists.denx.de>", "Date": "Mon, 31 Mar 2014 15:35:36 +0530", "Message-ID": "<1396260336-2785-1-git-send-email-prabhakar@freescale.com>", "X-Mailer": "git-send-email 1.7.9.5", "MIME-Version": "1.0", "X-OriginatorOrg": "freescale.com", "X-FOPE-CONNECTOR": [ "Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn%", "Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn%" ], "Cc": "yorksun@freescale.com", "Subject": "[U-Boot] [PATCH 10/10] board/t104xrdb: Add support of NAND, SD,\n\tSPI boot for T1040RDB", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.11", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.\nhere, PBL initialise the internal SRAM and copy SPL(160KB). This further\ninitialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.\nFinally SPL transer control to u-boot.\n\nInitialise/create followings required for SPL framework\n - Add spl.c which defines board_init_f, board_init_r\n - update tlb and ddr accordingly\n\nSigned-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>\n---\n This patch depends upon \n \"[PATCH 3] powerpc/t104xrdb: Unification of T104xRDB header files\"\n http://patchwork.ozlabs.org/patch/335207/\n\n board/freescale/t104xrdb/Makefile | 7 +-\n board/freescale/t104xrdb/README | 87 ++++++++++++++++++++++\n board/freescale/t104xrdb/ddr.c | 5 +-\n board/freescale/t104xrdb/spl.c | 118 +++++++++++++++++++++++++++++\n board/freescale/t104xrdb/t1040_rcw.cfg | 7 ++\n board/freescale/t104xrdb/t1042_rcw.cfg | 7 ++\n board/freescale/t104xrdb/t104x_pbi.cfg | 26 +++++++\n board/freescale/t104xrdb/tlb.c | 12 +++\n boards.cfg | 6 ++\n include/configs/T104xRDB.h | 128 ++++++++++++++++++++++++++++----\n 10 files changed, 384 insertions(+), 19 deletions(-)\n create mode 100644 board/freescale/t104xrdb/spl.c\n create mode 100644 board/freescale/t104xrdb/t1040_rcw.cfg\n create mode 100644 board/freescale/t104xrdb/t1042_rcw.cfg\n create mode 100644 board/freescale/t104xrdb/t104x_pbi.cfg", "diff": "diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile\nindex e51fb7a..a68c951 100644\n--- a/board/freescale/t104xrdb/Makefile\n+++ b/board/freescale/t104xrdb/Makefile\n@@ -4,10 +4,13 @@\n # SPDX-License-Identifier:\tGPL-2.0+\n #\n \n-\n+ifdef CONFIG_SPL_BUILD\n+obj-y += spl.o\n+else\n obj-y\t+= t104xrdb.o\n-obj-y\t+= ddr.o\n obj-y\t+= eth.o\n obj-$(CONFIG_PCI)\t+= pci.o\n+endif\n+obj-y\t+= ddr.o\n obj-y\t+= law.o\n obj-y\t+= tlb.o\ndiff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README\nindex 1da52bb..4001ac8 100644\n--- a/board/freescale/t104xrdb/README\n+++ b/board/freescale/t104xrdb/README\n@@ -198,3 +198,90 @@ The below commands apply to the board\n \n \t2.To change from vbank4 to vbank0\n \t\t=> qixis reset (it will boot using vbank0)\n+\n+NAND boot with 2 Stage boot loader\n+----------------------------------\n+PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.\n+SPL further initialise DDR using SPD and environment variables and copy\n+u-boot(768 KB) from flash to DDR.\n+Finally SPL transer control to u-boot for futher booting.\n+\n+SPL has following features:\n+ - Executes within 256K\n+ - No relocation required\n+\n+ Run time view of SPL framework during NAND boot :-\n+ -----------------------------------------------\n+ Area | Address |\n+-----------------------------------------------\n+ Reserve | 0xFFFC0000 (32KB) |\n+ -----------------------------------------------\n+ GD, BD | 0xFFFC8000 (4KB) |\n+ -----------------------------------------------\n+ ENV | 0xFFFC9000 (6KB) |\n+ -----------------------------------------------\n+ HEAP | 0xFFFCA800 (34KB) |\n+ -----------------------------------------------\n+ STACK | 0xFFFD8000 (20KB) |\n+ -----------------------------------------------\n+ U-boot SPL | 0xFFFD8000 (160KB) |\n+ -----------------------------------------------\n+\n+ Run time view of SPL framework during SD, SPI boot :-\n+ -----------------------------------------------\n+ Area | Address |\n+-----------------------------------------------\n+ Reserve | 0xFFFC0000 (32KB) |\n+ -----------------------------------------------\n+ GD, BD | 0xFFFC8000 (4KB) |\n+ -----------------------------------------------\n+ HEAP | 0xFFFC9000 (40KB) |\n+ -----------------------------------------------\n+ STACK | 0xFFFD8000 (20KB) |\n+ -----------------------------------------------\n+ U-boot SPL | 0xFFFD8000 (160KB) |\n+ -----------------------------------------------\n+\n+NAND Flash memory Map on T104xRDB\n+------------------------------------------\n+ Start\t\t End\t\tDefinition\t\t\tSize\n+0x000000\t0x0FFFFF\tu-boot 1MB\n+0x180000\t0x19FFFF\tu-boot env 128KB\n+0x200000\t0x21FFFF\tFMAN Ucode 128KB\n+0x280000\t0x29FFFF\tQE Firmware 128KB\n+\n+SD Card memory Map on T104xRDB\n+------------------------------------------\n+ Block\t\t#blocks\t\tDefinition\t\t\tSize\n+0x008\t\t2048\t\tu-boot 1MB\n+0x800\t\t0024\t\tu-boot env 8KB\n+0x820\t\t0256\t\tFMAN Ucode 128KB\n+0x920\t\t0256\t\tQE Firmware 128KB\n+\n+SPI Flash memory Map on T104xRDB\n+------------------------------------------\n+ Start\t\t End\t\tDefinition\t\t\tSize\n+0x000000\t0x0FFFFF\tu-boot 1MB\n+0x100000\t0x101FFF\tu-boot env 8KB\n+0x110000\t0x12FFFF\tFMAN Ucode 128KB\n+0x130000\t0x14FFFF\tQE Firmware 128KB\n+\n+Please note QE Firmware is only valid for T1040RDB\n+\n+\n+Switch Settings: (ON is 0, OFF is 1)\n+===============\n+NAND boot SW setting:\n+SW1: 10001000\n+SW2: 00111001\n+SW3: 11110001\n+\n+SPI boot SW setting:\n+SW1: 00100010\n+SW2: 10111001\n+SW3: 11100001\n+\n+SD boot SW setting:\n+SW1: 00100000\n+SW2: 00111001\n+SW3: 11100001\ndiff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c\nindex 57d0f9c..34c9224 100644\n--- a/board/freescale/t104xrdb/ddr.c\n+++ b/board/freescale/t104xrdb/ddr.c\n@@ -113,6 +113,7 @@ phys_size_t initdram(int board_type)\n {\n \tphys_size_t dram_size;\n \n+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)\n \tputs(\"Initializing....using SPD\\n\");\n \n \tdram_size = fsl_ddr_sdram();\n@@ -120,6 +121,8 @@ phys_size_t initdram(int board_type)\n \tdram_size = setup_ddr_tlbs(dram_size / 0x100000);\n \tdram_size *= 0x100000;\n \n-\tputs(\" DDR: \");\n+#else\n+\tdram_size = fsl_ddr_sdram_size();\n+#endif\n \treturn dram_size;\n }\ndiff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c\nnew file mode 100644\nindex 0000000..3aca0ca\n--- /dev/null\n+++ b/board/freescale/t104xrdb/spl.c\n@@ -0,0 +1,118 @@\n+/* Copyright 2013 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <malloc.h>\n+#include <ns16550.h>\n+#include <nand.h>\n+#include <i2c.h>\n+#include <mmc.h>\n+#include <fsl_esdhc.h>\n+#include <spi_flash.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+phys_size_t get_effective_memsize(void)\n+{\n+\treturn CONFIG_SYS_L3_SIZE;\n+}\n+\n+unsigned long get_board_sys_clk(void)\n+{\n+\treturn CONFIG_SYS_CLK_FREQ;\n+}\n+\n+unsigned long get_board_ddr_clk(void)\n+{\n+\treturn CONFIG_DDR_CLK_FREQ;\n+}\n+\n+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK\t0xFF800000\n+void board_init_f(ulong bootflag)\n+{\n+\tu32 plat_ratio, sys_clk, uart_clk;\n+#ifdef CONFIG_SPL_NAND_BOOT\n+\tu32 porsr1, pinctl;\n+#endif\n+\tccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;\n+\n+#ifdef CONFIG_SPL_NAND_BOOT\n+\t/*\n+\t * There is T1040 SoC issue where NOR, FPGA are inaccessible during\n+\t * NAND boot because IFC signals > IFC_AD7 are not enabled.\n+\t * This workaround changes RCW source to make all signals enabled.\n+\t */\n+\tporsr1 = in_be32(&gur->porsr1);\n+\tpinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);\n+\tout_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);\n+#endif\n+\n+\t/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */\n+\tmemcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));\n+\n+\t/* Update GD pointer */\n+\tgd = (gd_t *)(CONFIG_SPL_GD_ADDR);\n+\t__asm__ __volatile__(\"\" : : : \"memory\");\n+\n+\tconsole_init_f();\n+\n+\t/* initialize selected port with appropriate baud rate */\n+\tsys_clk = get_board_sys_clk();\n+\tplat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;\n+\tuart_clk = sys_clk * plat_ratio / 2;\n+\n+\tNS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,\n+\t\t uart_clk / 16 / CONFIG_BAUDRATE);\n+\n+\trelocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);\n+}\n+\n+void board_init_r(gd_t *gd, ulong dest_addr)\n+{\n+\tbd_t *bd;\n+\n+\tbd = (bd_t *)(gd + sizeof(gd_t));\n+\tmemset(bd, 0, sizeof(bd_t));\n+\tgd->bd = bd;\n+\tbd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;\n+\tbd->bi_memsize = CONFIG_SYS_L3_SIZE;\n+\n+\tprobecpu();\n+\tget_clocks();\n+\tmem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,\n+\t\t\tCONFIG_SPL_RELOC_MALLOC_SIZE);\n+\n+#ifndef CONFIG_SPL_NAND_BOOT\n+\tenv_init();\n+#endif\n+\n+#ifdef CONFIG_SPL_MMC_BOOT\n+\tmmc_initialize(bd);\n+#endif\n+\n+\t/* relocate environment function pointers etc. */\n+#ifdef CONFIG_SPL_NAND_BOOT\n+\tnand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,\n+\t\t\t (uchar *)CONFIG_ENV_ADDR);\n+\tgd->env_addr = (ulong)(CONFIG_ENV_ADDR);\n+\tgd->env_valid = 1;\n+#else\n+\tenv_relocate();\n+#endif\n+\n+\ti2c_init_all();\n+\n+\tputs(\"\\n\\n\");\n+\n+\tgd->ram_size = initdram(0);\n+\n+#ifdef CONFIG_SPL_MMC_BOOT\n+\tmmc_boot();\n+#elif defined(CONFIG_SPL_SPI_BOOT)\n+\tspi_boot();\n+#elif defined(CONFIG_SPL_NAND_BOOT)\n+\tnand_boot();\n+#endif\n+}\ndiff --git a/board/freescale/t104xrdb/t1040_rcw.cfg b/board/freescale/t104xrdb/t1040_rcw.cfg\nnew file mode 100644\nindex 0000000..3300c18\n--- /dev/null\n+++ b/board/freescale/t104xrdb/t1040_rcw.cfg\n@@ -0,0 +1,7 @@\n+#PBL preamble and RCW header\n+aa55aa55 010e0100\n+# serdes protocol 0x66\n+0c18000e 0e000000 00000000 00000000\n+66000002 80000002 e8106000 01000000\n+00000000 00000000 00000000 00032810\n+00000000 0342500f 00000000 00000000\ndiff --git a/board/freescale/t104xrdb/t1042_rcw.cfg b/board/freescale/t104xrdb/t1042_rcw.cfg\nnew file mode 100644\nindex 0000000..a3ea8ad\n--- /dev/null\n+++ b/board/freescale/t104xrdb/t1042_rcw.cfg\n@@ -0,0 +1,7 @@\n+#PBL preamble and RCW header\n+aa55aa55 010e0100\n+# serdes protocol 0x66\n+0c18000e 0e000000 00000000 00000000\n+06000002 00400002 e8106000 01000000\n+00000000 00000000 00000000 00030810\n+00000000 01fe0a06 00000000 00000000\ndiff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg\nnew file mode 100644\nindex 0000000..7b9e9b0\n--- /dev/null\n+++ b/board/freescale/t104xrdb/t104x_pbi.cfg\n@@ -0,0 +1,26 @@\n+#PBI commands\n+#Initialize CPC1\n+09010000 00200400\n+09138000 00000000\n+091380c0 00000100\n+#Configure CPC1 as 256KB SRAM\n+09010100 00000000\n+09010104 fffc0007\n+09010f00 08000000\n+09010000 80000000\n+#Configure LAW for CPC1\n+09000cd0 00000000\n+09000cd4 fffc0000\n+09000cd8 81000011\n+#Configure alternate space\n+09000010 00000000\n+09000014 ff000000\n+09000018 81000000\n+#Configure SPI controller\n+09110000 80000403\n+09110020 2d170008\n+09110024 00100008\n+09110028 00100008\n+0911002c 00100008\n+#Flush PBL data\n+091380c0 000FFFFF\ndiff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c\nindex 84f97a4..95c15aa 100644\n--- a/board/freescale/t104xrdb/tlb.c\n+++ b/board/freescale/t104xrdb/tlb.c\n@@ -53,6 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = {\n \t\t MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,\n \t\t 0, 2, BOOKE_PAGESZ_256M, 1),\n \n+#ifndef CONFIG_SPL_BUILD\n \t/* *I*G* - PCI */\n \tSET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,\n \t\t MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,\n@@ -82,6 +83,7 @@ struct fsl_e_tlb_entry tlb_table[] = {\n \t\t MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,\n \t\t 0, 8, BOOKE_PAGESZ_16M, 1),\n #endif\n+#endif\n #ifdef CONFIG_SYS_DCSRBAR_PHYS\n \tSET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,\n \t\t MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,\n@@ -102,6 +104,16 @@ struct fsl_e_tlb_entry tlb_table[] = {\n \t\t MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,\n \t\t 0, 11, BOOKE_PAGESZ_256K, 1),\n #endif\n+\n+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)\n+\tSET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,\n+\t\t MAS3_SX|MAS3_SW|MAS3_SR, 0,\n+\t\t 0, 12, BOOKE_PAGESZ_1G, 1),\n+\tSET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,\n+\t\t CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,\n+\t\t MAS3_SX|MAS3_SW|MAS3_SR, 0,\n+\t\t 0, 13, BOOKE_PAGESZ_1G, 1)\n+#endif\n };\n \n int num_tlb_entries = ARRAY_SIZE(tlb_table);\ndiff --git a/boards.cfg b/boards.cfg\nindex 76f3aae..1c96a51 100644\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -933,7 +933,13 @@ Active powerpc mpc85xx - freescale p2041rdb\n Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -\n Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>\n Active powerpc mpc85xx - freescale t104xrdb T1040RDB T104xRDB:PPC_T1040,T1040RDB Priyanka Jain <Priyanka.Jain@freescale.com>\n+Active powerpc mpc85xx - freescale t104xrdb T1040RDB_NAND T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,RAMBOOT_SPLPBL,NAND Priyanka Jain <Priyanka.Jain@freescale.com>\n+Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SPIFLASH T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,RAMBOOT_SPLPBL,SPIFLASH Priyanka Jain <Priyanka.Jain@freescale.com>\n+Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SDCARD T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,RAMBOOT_SPLPBL,SDCARD\n Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T104xRDB:PPC_T1042,T1042RDB_PI Priyanka Jain <Priyanka.Jain@freescale.com>\n+Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_NAND T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,RAMBOOT_SPLPBL,NAND Priyanka Jain <Priyanka.Jain@freescale.com>\n+Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SPIFLASH T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,RAMBOOT_SPLPBL,SPIFLASH Priyanka Jain <Priyanka.Jain@freescale.com>\n+Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SDCARD T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,RAMBOOT_SPLPBL,SDCARD\n Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 -\n Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -\n Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -\ndiff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h\nindex 90ac1ec..6e0bb2b 100644\n--- a/include/configs/T104xRDB.h\n+++ b/include/configs/T104xRDB.h\n@@ -14,8 +14,79 @@\n #define CONFIG_PHYS_64BIT\n \n #ifdef CONFIG_RAMBOOT_PBL\n-#define CONFIG_RAMBOOT_TEXT_BASE\tCONFIG_SYS_TEXT_BASE\n-#define CONFIG_RESET_VECTOR_ADDRESS\t0xfffffffc\n+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg\n+#ifdef CONFIG_T1040RDB\n+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg\n+#endif\n+#ifdef CONFIG_T1042RDB_PI\n+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg\n+#endif\n+\n+#define CONFIG_SPL\n+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT\n+#define CONFIG_SPL_ENV_SUPPORT\n+#define CONFIG_SPL_SERIAL_SUPPORT\n+#define CONFIG_SPL_FLUSH_IMAGE\n+#define CONFIG_SPL_TARGET\t\t\"u-boot-with-spl.bin\"\n+#define CONFIG_SPL_LIBGENERIC_SUPPORT\n+#define CONFIG_SPL_LIBCOMMON_SUPPORT\n+#define CONFIG_SPL_I2C_SUPPORT\n+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT\n+#define CONFIG_FSL_LAW /* Use common FSL init code */\n+#define CONFIG_SYS_TEXT_BASE\t\t0x00201000\n+#define CONFIG_SPL_TEXT_BASE\t\t0xFFFD8000\n+#define CONFIG_SPL_PAD_TO\t\t0x40000\n+#define CONFIG_SPL_MAX_SIZE\t\t0x28000\n+#ifdef CONFIG_SPL_BUILD\n+#define CONFIG_SPL_SKIP_RELOCATE\n+#define CONFIG_SPL_COMMON_INIT_DDR\n+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE\n+#define CONFIG_SYS_NO_FLASH\n+#endif\n+#define RESET_VECTOR_OFFSET\t\t0x27FFC\n+#define BOOT_PAGE_OFFSET\t\t0x27000\n+\n+#ifdef CONFIG_NAND\n+#define CONFIG_SPL_NAND_SUPPORT\n+#define CONFIG_SYS_NAND_U_BOOT_SIZE\t(768 << 10)\n+#define CONFIG_SYS_NAND_U_BOOT_DST\t0x00200000\n+#define CONFIG_SYS_NAND_U_BOOT_START\t0x00200000\n+#define CONFIG_SYS_NAND_U_BOOT_OFFS\t(256 << 10)\n+#define CONFIG_SYS_LDSCRIPT\t\"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds\"\n+#define CONFIG_SPL_NAND_BOOT\n+#endif\n+\n+#ifdef CONFIG_SPIFLASH\n+#define\tCONFIG_RESET_VECTOR_ADDRESS\t\t0x200FFC\n+#define CONFIG_SPL_SPI_SUPPORT\n+#define CONFIG_SPL_SPI_FLASH_SUPPORT\n+#define CONFIG_SPL_SPI_FLASH_MINIMAL\n+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE\t(768 << 10)\n+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST\t\t(0x00200000)\n+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START\t(0x00200000)\n+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS\t(256 << 10)\n+#define CONFIG_SYS_LDSCRIPT\t\"arch/powerpc/cpu/mpc85xx/u-boot.lds\"\n+#ifndef CONFIG_SPL_BUILD\n+#define\tCONFIG_SYS_MPC85XX_NO_RESETVEC\n+#endif\n+#define CONFIG_SPL_SPI_BOOT\n+#endif\n+\n+#ifdef CONFIG_SDCARD\n+#define\tCONFIG_RESET_VECTOR_ADDRESS\t\t0x200FFC\n+#define CONFIG_SPL_MMC_SUPPORT\n+#define CONFIG_SPL_MMC_MINIMAL\n+#define CONFIG_SYS_MMC_U_BOOT_SIZE\t(768 << 10)\n+#define CONFIG_SYS_MMC_U_BOOT_DST\t(0x00200000)\n+#define CONFIG_SYS_MMC_U_BOOT_START\t(0x00200000)\n+#define CONFIG_SYS_MMC_U_BOOT_OFFS\t(260 << 10)\n+#define CONFIG_SYS_LDSCRIPT\t\"arch/powerpc/cpu/mpc85xx/u-boot.lds\"\n+#ifndef CONFIG_SPL_BUILD\n+#define\tCONFIG_SYS_MPC85XX_NO_RESETVEC\n+#endif\n+#define CONFIG_SPL_MMC_BOOT\n+#endif\n+\n #endif\n \n /* High Level Configuration Options */\n@@ -50,15 +121,12 @@\n \n #define CONFIG_ENV_OVERWRITE\n \n-#ifdef CONFIG_SYS_NO_FLASH\n-#define CONFIG_ENV_IS_NOWHERE\n-#else\n+#ifndef CONFIG_SYS_NO_FLASH\n #define CONFIG_FLASH_CFI_DRIVER\n #define CONFIG_SYS_FLASH_CFI\n #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE\n #endif\n \n-#ifndef CONFIG_SYS_NO_FLASH\n #if defined(CONFIG_SPIFLASH)\n #define CONFIG_SYS_EXTRA_ENV_RELOC\n #define CONFIG_ENV_IS_IN_SPI_FLASH\n@@ -70,11 +138,11 @@\n #define CONFIG_ENV_IS_IN_MMC\n #define CONFIG_SYS_MMC_ENV_DEV 0\n #define CONFIG_ENV_SIZE\t\t\t0x2000\n-#define CONFIG_ENV_OFFSET\t\t(512 * 1658)\n+#define CONFIG_ENV_OFFSET\t\t(512 * 0x800)\n #elif defined(CONFIG_NAND)\n #define CONFIG_SYS_EXTRA_ENV_RELOC\n #define CONFIG_ENV_IS_IN_NAND\n-#define CONFIG_ENV_SIZE\t\t\tCONFIG_SYS_NAND_BLOCK_SIZE\n+#define CONFIG_ENV_SIZE\t\t\t0x2000\n #define CONFIG_ENV_OFFSET\t\t(3 * CONFIG_SYS_NAND_BLOCK_SIZE)\n #else\n #define CONFIG_ENV_IS_IN_FLASH\n@@ -82,10 +150,6 @@\n #define CONFIG_ENV_SIZE\t\t0x2000\n #define CONFIG_ENV_SECT_SIZE\t0x20000 /* 128K (one sector) */\n #endif\n-#else /* CONFIG_SYS_NO_FLASH */\n-#define CONFIG_ENV_SIZE 0x2000\n-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */\n-#endif\n \n #define CONFIG_SYS_CLK_FREQ\t100000000\n #define CONFIG_DDR_CLK_FREQ\t66666666\n@@ -117,6 +181,18 @@\n * Config the L3 Cache as L3 SRAM\n */\n #define CONFIG_SYS_INIT_L3_ADDR\t\t0xFFFC0000\n+#define CONFIG_SYS_L3_SIZE\t\t256 << 10\n+#define CONFIG_SPL_GD_ADDR\t\t(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)\n+#ifdef CONFIG_NAND\n+#define CONFIG_ENV_ADDR\t\t\t(CONFIG_SPL_GD_ADDR + 4 * 1024)\n+#define CONFIG_SPL_RELOC_MALLOC_ADDR\t(CONFIG_SPL_GD_ADDR + 10 * 1024)\n+#define CONFIG_SPL_RELOC_MALLOC_SIZE\t(34 << 10)\n+#else\n+#define CONFIG_SPL_RELOC_MALLOC_ADDR\t(CONFIG_SPL_GD_ADDR + 4 * 1024)\n+#define CONFIG_SPL_RELOC_MALLOC_SIZE\t(40 << 10)\n+#endif\n+#define CONFIG_SPL_RELOC_STACK\t\t(CONFIG_SPL_GD_ADDR + 64 * 1024)\n+#define CONFIG_SPL_RELOC_STACK_SIZE\t(20 << 10)\n \n #define CONFIG_SYS_DCSRBAR\t\t0xf0000000\n #define CONFIG_SYS_DCSRBAR_PHYS\t\t0xf00000000ull\n@@ -279,7 +355,11 @@\n #define CONFIG_SYS_CS1_FTIM3\t\tCONFIG_SYS_NAND_FTIM3\n #endif\n \n-#define CONFIG_SYS_MONITOR_BASE\t\tCONFIG_SYS_TEXT_BASE\n+#ifdef CONFIG_SPL_BUILD\n+#define CONFIG_SYS_MONITOR_BASE\tCONFIG_SPL_TEXT_BASE\n+#else\n+#define CONFIG_SYS_MONITOR_BASE\tCONFIG_SYS_TEXT_BASE\t/* start of monitor */\n+#endif\n \n #if defined(CONFIG_RAMBOOT_PBL)\n #define CONFIG_SYS_RAMBOOT\n@@ -327,7 +407,9 @@\n #define CONFIG_SYS_NS16550_COM3\t(CONFIG_SYS_CCSRBAR+0x11D500)\n #define CONFIG_SYS_NS16550_COM4\t(CONFIG_SYS_CCSRBAR+0x11D600)\n #define CONFIG_SERIAL_MULTI\t\t/* Enable both serial ports */\n+#ifndef CONFIG_SPL_BUILD\n #define CONFIG_SYS_CONSOLE_IS_IN_ENV\t/* determine from environment */\n+#endif\n \n /* Use the HUSH parser */\n #define CONFIG_SYS_HUSH_PARSER\n@@ -517,11 +599,11 @@\n #elif defined(CONFIG_SDCARD)\n /*\n * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is\n- * about 825KB (1650 blocks), Env is stored after the image, and the env size is\n- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.\n+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is\n+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.\n */\n #define CONFIG_SYS_QE_FMAN_FW_IN_MMC\n-#define CONFIG_SYS_QE_FMAN_FW_ADDR\t(512 * 1680)\n+#define CONFIG_SYS_QE_FMAN_FW_ADDR\t\t(512 * 0x820)\n #elif defined(CONFIG_NAND)\n #define CONFIG_SYS_QE_FMAN_FW_IN_NAND\n #define CONFIG_SYS_QE_FMAN_FW_ADDR\t(4 * CONFIG_SYS_NAND_BLOCK_SIZE)\n@@ -529,6 +611,20 @@\n #define CONFIG_SYS_QE_FMAN_FW_IN_NOR\n #define CONFIG_SYS_QE_FMAN_FW_ADDR\t\t0xEFF00000\n #endif\n+\n+#ifdef CONFIG_T1040RDB\n+#if defined(CONFIG_SPIFLASH)\n+#define CONFIG_SYS_QE_FW_ADDR\t\t0x130000\n+#elif defined(CONFIG_SDCARD)\n+#define CONFIG_SYS_QE_FW_ADDR\t\t(512 * 0x920)\n+#elif defined(CONFIG_NAND)\n+#define CONFIG_SYS_QE_FW_ADDR\t\t(5 * CONFIG_SYS_NAND_BLOCK_SIZE)\n+#else\n+#define CONFIG_SYS_QE_FW_ADDR\t\t0xEFF10000\n+#endif\n+#endif\n+\n+\n #define CONFIG_SYS_QE_FMAN_FW_LENGTH\t0x10000\n #define CONFIG_SYS_FDT_PAD\t\t(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)\n #endif /* CONFIG_NOBQFMAN */\n", "prefixes": [ "U-Boot", "10/10" ] }