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GET /api/patches/335249/?format=api
{ "id": 335249, "url": "http://patchwork.ozlabs.org/api/patches/335249/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1396260323-2751-1-git-send-email-prabhakar@freescale.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1396260323-2751-1-git-send-email-prabhakar@freescale.com>", "list_archive_url": null, "date": "2014-03-31T10:05:23", "name": "[U-Boot,9/10] board/b4qds:Add support of 2 stage NAND boot-loader", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "ac1230ab3fa3b8ea639e31d007aa1800c4f3c505", "submitter": { "id": 6576, "url": "http://patchwork.ozlabs.org/api/people/6576/?format=api", "name": "Prabhakar Kushwaha", "email": "prabhakar@freescale.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1396260323-2751-1-git-send-email-prabhakar@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/335249/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/335249/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 5C3901400B2\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 31 Mar 2014 21:05:57 +1100 (EST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id CCB0C4B695;\n\tMon, 31 Mar 2014 12:05:55 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id EMpZ5X07wbTh; Mon, 31 Mar 2014 12:05:55 +0200 (CEST)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 487A84B67D;\n\tMon, 31 Mar 2014 12:05:53 +0200 (CEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 76D104B677\n\tfor <u-boot@lists.denx.de>; Mon, 31 Mar 2014 12:05:47 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id MJrUAPcAd8pM for <u-boot@lists.denx.de>;\n\tMon, 31 Mar 2014 12:05:46 +0200 (CEST)", "from am1outboundpool.messaging.microsoft.com\n\t(am1ehsobe001.messaging.microsoft.com [213.199.154.204])\n\tby theia.denx.de (Postfix) with ESMTPS id 9A7C24B695\n\tfor <u-boot@lists.denx.de>; Mon, 31 Mar 2014 12:05:37 +0200 (CEST)", "from mail30-am1-R.bigfish.com (10.3.201.245) by\n\tAM1EHSOBE023.bigfish.com (10.3.207.145) with Microsoft SMTP Server id\n\t14.1.225.22; Mon, 31 Mar 2014 10:05:37 +0000", "from mail30-am1 (localhost [127.0.0.1])\tby mail30-am1-R.bigfish.com\n\t(Postfix) with ESMTP id 14E713A01FD\tfor <u-boot@lists.denx.de>;\n\tMon, 31 Mar 2014 10:05:37 +0000 (UTC)", "from mail30-am1 (localhost.localdomain [127.0.0.1]) by mail30-am1\n\t(MessageSwitch) id 1396260334290946_4077;\n\tMon, 31 Mar 2014 10:05:34 +0000 (UTC)", "from AM1EHSMHS002.bigfish.com (unknown [10.3.201.251])\tby\n\tmail30-am1.bigfish.com (Postfix) with ESMTP id 3A85F200265;\n\tMon, 31 Mar 2014 10:05:34 +0000 (UTC)", "from mail.freescale.net (70.37.183.190) by AM1EHSMHS002.bigfish.com\n\t(10.3.207.102) with Microsoft SMTP Server (TLS) id 14.16.227.3;\n\tMon, 31 Mar 2014 10:05:32 +0000", "from tx30smr01.am.freescale.net (10.81.153.31) by\n\t039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP\n\tServer (TLS) id 14.3.158.2; Mon, 31 Mar 2014 10:05:30 +0000", "from b32579-VirtualBox.ap.freescale.net\n\t(B32579-02-010232132051.ap.freescale.net [10.232.132.51])\tby\n\ttx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\ts2VA5Oiv027423; Mon, 31 Mar 2014 03:05:28 -0700" ], "X-Virus-Scanned": [ "Debian amavisd-new at theia.denx.de", "Debian amavisd-new at theia.denx.de" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "X-Forefront-Antispam-Report": "CIP:70.37.183.190; KIP:(null); UIP:(null);\n\tIPV:NLI; \n\tH:mail.freescale.net; RD:none; EFVD:NLI", "X-SpamScore": "0", "X-BigFish": "VS0(zze0eahzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah21bch1fc6hzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h24afh2327h2336h2438h2461h2487h24d7h2516h2545h255eh25cch25f6h2605h268bh1155h)", "From": "Prabhakar Kushwaha <prabhakar@freescale.com>", "To": "<u-boot@lists.denx.de>", "Date": "Mon, 31 Mar 2014 15:35:23 +0530", "Message-ID": "<1396260323-2751-1-git-send-email-prabhakar@freescale.com>", "X-Mailer": "git-send-email 1.7.9.5", "MIME-Version": "1.0", "X-OriginatorOrg": "freescale.com", "X-FOPE-CONNECTOR": [ "Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn%", "Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn%" ], "Cc": "yorksun@freescale.com", "Subject": "[U-Boot] [PATCH 9/10] board/b4qds:Add support of 2 stage NAND\n\tboot-loader", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.11", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "Add support of 2 stage NAND boot loader using SPL framework.\nhere, PBL initialise the internal SRAM and copy SPL(160KB). This further\ninitialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.\nFinally SPL transer control to u-boot.\n\nInitialise/create followings required for SPL framework\n - Add spl.c which defines board_init_f, board_init_r\n - update tlb and ddr accordingly\n\nSigned-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>\n---\n board/freescale/b4860qds/Makefile | 9 ++-\n board/freescale/b4860qds/ddr.c | 5 +-\n board/freescale/b4860qds/spl.c | 115 +++++++++++++++++++++++++++++++++++++\n board/freescale/b4860qds/tlb.c | 10 ++++\n boards.cfg | 4 +-\n doc/README.b4860qds | 35 +++++++++++\n include/configs/B4860QDS.h | 64 ++++++++++++++++++---\n 7 files changed, 230 insertions(+), 12 deletions(-)\n create mode 100644 board/freescale/b4860qds/spl.c", "diff": "diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile\nindex e5cc054..0acd2a9 100644\n--- a/board/freescale/b4860qds/Makefile\n+++ b/board/freescale/b4860qds/Makefile\n@@ -4,9 +4,14 @@\n # SPDX-License-Identifier:\tGPL-2.0+\n #\n \n+ifdef CONFIG_SPL_BUILD\n+obj-y += spl.o\n+else\n obj-y\t+= b4860qds.o\n-obj-y\t+= ddr.o\n obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o\n-obj-$(CONFIG_PCI)\t+= pci.o\n+obj-$(CONFIG_PCI) += pci.o\n+endif\n+\n+obj-y\t+= ddr.o\n obj-y\t+= law.o\n obj-y\t+= tlb.o\ndiff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c\nindex 187c3b3..2c17156 100644\n--- a/board/freescale/b4860qds/ddr.c\n+++ b/board/freescale/b4860qds/ddr.c\n@@ -179,6 +179,7 @@ phys_size_t initdram(int board_type)\n {\n \tphys_size_t dram_size;\n \n+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)\n \tputs(\"Initializing....using SPD\\n\");\n \n \tdram_size = fsl_ddr_sdram();\n@@ -186,7 +187,9 @@ phys_size_t initdram(int board_type)\n \tdram_size = setup_ddr_tlbs(dram_size / 0x100000);\n \tdram_size *= 0x100000;\n \n-\tputs(\" DDR: \");\n+#else\n+\tdram_size = fsl_ddr_sdram_size();\n+#endif\n \treturn dram_size;\n }\n \ndiff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c\nnew file mode 100644\nindex 0000000..d56cd30\n--- /dev/null\n+++ b/board/freescale/b4860qds/spl.c\n@@ -0,0 +1,115 @@\n+/* Copyright 2013 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/spl.h>\n+#include <malloc.h>\n+#include <ns16550.h>\n+#include <nand.h>\n+#include <i2c.h>\n+#include \"../common/qixis.h\"\n+#include \"b4860qds_qixis.h\"\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+phys_size_t get_effective_memsize(void)\n+{\n+\treturn CONFIG_SYS_L3_SIZE;\n+}\n+\n+unsigned long get_board_sys_clk(void)\n+{\n+\tu8 sysclk_conf = QIXIS_READ(brdcfg[1]);\n+\n+\tswitch ((sysclk_conf & 0x0C) >> 2) {\n+\tcase QIXIS_CLK_100:\n+\t\treturn 100000000;\n+\tcase QIXIS_CLK_125:\n+\t\treturn 125000000;\n+\tcase QIXIS_CLK_133:\n+\t\treturn 133333333;\n+\t}\n+\treturn 66666666;\n+}\n+\n+unsigned long get_board_ddr_clk(void)\n+{\n+\tu8 ddrclk_conf = QIXIS_READ(brdcfg[1]);\n+\n+\tswitch (ddrclk_conf & 0x03) {\n+\tcase QIXIS_CLK_100:\n+\t\treturn 100000000;\n+\tcase QIXIS_CLK_125:\n+\t\treturn 125000000;\n+\tcase QIXIS_CLK_133:\n+\t\treturn 133333333;\n+\t}\n+\treturn 66666666;\n+}\n+\n+void board_init_f(ulong bootflag)\n+{\n+\tu32 plat_ratio, sys_clk, uart_clk;\n+\tccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;\n+\n+\t/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */\n+\tmemcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));\n+\n+\t/* Update GD pointer */\n+\tgd = (gd_t *)(CONFIG_SPL_GD_ADDR);\n+\t__asm__ __volatile__(\"\" : : : \"memory\");\n+\n+\tconsole_init_f();\n+\n+\t/* initialize selected port with appropriate baud rate */\n+\tsys_clk = get_board_sys_clk();\n+\tplat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;\n+\tuart_clk = sys_clk * plat_ratio / 2;\n+\n+\tNS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,\n+\t\t uart_clk / 16 / CONFIG_BAUDRATE);\n+\n+\trelocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);\n+}\n+\n+void board_init_r(gd_t *gd, ulong dest_addr)\n+{\n+\tbd_t *bd;\n+\n+\tbd = (bd_t *)(gd + sizeof(gd_t));\n+\tmemset(bd, 0, sizeof(bd_t));\n+\tgd->bd = bd;\n+\tbd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;\n+\tbd->bi_memsize = CONFIG_SYS_L3_SIZE;\n+\n+\tprobecpu();\n+\tget_clocks();\n+\tmem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,\n+\t\t\tCONFIG_SPL_RELOC_MALLOC_SIZE);\n+\n+#ifndef CONFIG_SPL_NAND_BOOT\n+\tenv_init();\n+#endif\n+\n+\t/* relocate environment function pointers etc. */\n+#ifdef CONFIG_SPL_NAND_BOOT\n+\tnand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,\n+\t\t\t (uchar *)CONFIG_ENV_ADDR);\n+\tgd->env_addr = (ulong)(CONFIG_ENV_ADDR);\n+\tgd->env_valid = 1;\n+#else\n+\tenv_relocate();\n+#endif\n+\n+\ti2c_init_all();\n+\n+\tputs(\"\\n\\n\");\n+\n+\tgd->ram_size = initdram(0);\n+\n+#ifdef CONFIG_SPL_NAND_BOOT\n+\tnand_boot();\n+#endif\n+}\ndiff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c\nindex 00798a1..7b55b86 100644\n--- a/board/freescale/b4860qds/tlb.c\n+++ b/board/freescale/b4860qds/tlb.c\n@@ -62,6 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {\n \t\t MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,\n \t\t 0, 2, BOOKE_PAGESZ_256M, 1),\n \n+#ifndef CONFIG_SPL_BUILD\n \t/* *I*G* - PCI */\n \tSET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,\n \t\t MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,\n@@ -96,6 +97,7 @@ struct fsl_e_tlb_entry tlb_table[] = {\n \t\t MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,\n \t\t 0, 9, BOOKE_PAGESZ_16M, 1),\n #endif\n+#endif\n #ifdef CONFIG_SYS_DCSRBAR_PHYS\n \tSET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,\n \t\t MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,\n@@ -118,6 +120,7 @@ struct fsl_e_tlb_entry tlb_table[] = {\n \t * entry 14 and 15 has been used hard coded, they will be disabled\n \t * in cpu_init_f, so we use entry 16 for SRIO2.\n \t */\n+#ifndef CONFIG_SPL_BUILD\n #ifdef CONFIG_SYS_SRIO1_MEM_PHYS\n \t/* *I*G* - SRIO1 */\n \tSET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,\n@@ -140,6 +143,13 @@ struct fsl_e_tlb_entry tlb_table[] = {\n \t\t MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,\n \t\t 0, 17, BOOKE_PAGESZ_1M, 1),\n #endif\n+#endif\n+\n+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)\n+\tSET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,\n+\t\t MAS3_SX|MAS3_SW|MAS3_SR, 0,\n+\t\t 0, 17, BOOKE_PAGESZ_2G, 1)\n+#endif\n };\n \n int num_tlb_entries = ARRAY_SIZE(tlb_table);\ndiff --git a/boards.cfg b/boards.cfg\nindex 5afca26..76f3aae 100644\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -740,10 +740,10 @@ Active powerpc mpc85xx - - sbc8548\n Active powerpc mpc85xx - - socrates socrates - -\n Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>\n Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 -\n-Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -\n+Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,RAMBOOT_SPLPBL,NAND -\n Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -\n Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 -\n-Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -\n+Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,RAMBOOT_SPLPBL,NAND\n Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -\n Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -\n Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal <poonam.aggrwal@freescale.com>\ndiff --git a/doc/README.b4860qds b/doc/README.b4860qds\nindex 3da77d9..44b46da 100644\n--- a/doc/README.b4860qds\n+++ b/doc/README.b4860qds\n@@ -328,3 +328,38 @@ The below commands apply to both B4860QDS and B4420QDS.\n On Linux the interfaces are renamed as:\n \t. eth2 -> fm1-gb2\n \t. eth3 -> fm1-gb3\n+\n+NAND boot with 2 Stage boot loader\n+----------------------------------\n+PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.\n+SPL further initialise DDR using SPD and environment variables and copy\n+u-boot(768 KB) from flash to DDR.\n+Finally SPL transer control to u-boot for futher booting.\n+\n+SPL has following features:\n+ - Executes within 256K\n+ - No relocation required\n+\n+ Run time view of SPL framework :-\n+ -----------------------------------------------\n+ Area | Address |\n+-----------------------------------------------\n+ Reserve | 0xFFFC0000 (32KB) |\n+ -----------------------------------------------\n+ GD, BD | 0xFFFC8000 (4KB) |\n+ -----------------------------------------------\n+ ENV | 0xFFFC9000 (6KB) |\n+ -----------------------------------------------\n+ HEAP | 0xFFFCA800 (30KB) |\n+ -----------------------------------------------\n+ STACK | 0xFFFD8000 (20KB) |\n+ -----------------------------------------------\n+ U-boot SPL | 0xFFFD8000 (160KB) |\n+ -----------------------------------------------\n+\n+NAND Flash memory Map on B4860 and B4420QDS\n+------------------------------------------\n+ Start\t\t End\t\tDefinition\t\t\tSize\n+0x000000\t0x0FFFFF\tu-boot 1MB\n+0x140000\t0x15FFFF\tu-boot env 128KB\n+0x160000\t0x17FFFF\tFMAN Ucode 128KB\ndiff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h\nindex 8fcd1de..4df28a2 100644\n--- a/include/configs/B4860QDS.h\n+++ b/include/configs/B4860QDS.h\n@@ -14,10 +14,43 @@\n #define CONFIG_PHYS_64BIT\n \n #ifdef CONFIG_RAMBOOT_PBL\n+#define CONFIG_SYS_FSL_PBL_PBI\t$(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg\n+#define CONFIG_SYS_FSL_PBL_RCW\t$(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg\n+#ifndef CONFIG_NAND\n #define CONFIG_RAMBOOT_TEXT_BASE\tCONFIG_SYS_TEXT_BASE\n #define CONFIG_RESET_VECTOR_ADDRESS\t0xfffffffc\n-#define CONFIG_SYS_FSL_PBL_PBI\tboard/freescale/b4860qds/b4_pbi.cfg\n-#define CONFIG_SYS_FSL_PBL_RCW\tboard/freescale/b4860qds/b4_rcw.cfg\n+#else\n+#define CONFIG_SPL\n+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT\n+#define CONFIG_SPL_ENV_SUPPORT\n+#define CONFIG_SPL_SERIAL_SUPPORT\n+#define CONFIG_SPL_FLUSH_IMAGE\n+#define CONFIG_SPL_TARGET\t\t\"u-boot-with-spl.bin\"\n+#define CONFIG_SPL_LIBGENERIC_SUPPORT\n+#define CONFIG_SPL_LIBCOMMON_SUPPORT\n+#define CONFIG_SPL_I2C_SUPPORT\n+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT\n+#define CONFIG_FSL_LAW /* Use common FSL init code */\n+#define CONFIG_SYS_TEXT_BASE\t\t0x00201000\n+#define CONFIG_SPL_TEXT_BASE\t\t0xFFFD8000\n+#define CONFIG_SPL_PAD_TO\t\t0x40000\n+#define CONFIG_SPL_MAX_SIZE\t\t0x28000\n+#define RESET_VECTOR_OFFSET\t\t0x27FFC\n+#define BOOT_PAGE_OFFSET\t\t0x27000\n+#define CONFIG_SPL_NAND_SUPPORT\n+#define CONFIG_SYS_NAND_U_BOOT_SIZE\t(768 << 10)\n+#define CONFIG_SYS_NAND_U_BOOT_DST\t0x00200000\n+#define CONFIG_SYS_NAND_U_BOOT_START\t0x00200000\n+#define CONFIG_SYS_NAND_U_BOOT_OFFS\t(256 << 10)\n+#define CONFIG_SYS_LDSCRIPT\t\"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds\"\n+#define CONFIG_SPL_NAND_BOOT\n+#ifdef CONFIG_SPL_BUILD\n+#define CONFIG_SPL_SKIP_RELOCATE\n+#define CONFIG_SPL_COMMON_INIT_DDR\n+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE\n+#define CONFIG_SYS_NO_FLASH\n+#endif\n+#endif\n #endif\n \n #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE\n@@ -113,8 +146,8 @@\n #elif defined(CONFIG_NAND)\n #define CONFIG_SYS_EXTRA_ENV_RELOC\n #define CONFIG_ENV_IS_IN_NAND\n-#define CONFIG_ENV_SIZE\t\t\tCONFIG_SYS_NAND_BLOCK_SIZE\n-#define CONFIG_ENV_OFFSET\t\t(7 * CONFIG_SYS_NAND_BLOCK_SIZE)\n+#define CONFIG_ENV_SIZE\t\t\t0x2000\n+#define CONFIG_ENV_OFFSET\t\t(10 * CONFIG_SYS_NAND_BLOCK_SIZE)\n #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)\n #define CONFIG_ENV_IS_IN_REMOTE\n #define CONFIG_ENV_ADDR\t\t0xffe20000\n@@ -164,7 +197,16 @@ unsigned long get_board_ddr_clk(void);\n /*\n * Config the L3 Cache as L3 SRAM\n */\n-#define CONFIG_SYS_INIT_L3_ADDR\t\tCONFIG_RAMBOOT_TEXT_BASE\n+#define CONFIG_SYS_INIT_L3_ADDR\t\t0xFFFC0000\n+#define CONFIG_SYS_L3_SIZE\t\t256 << 10\n+#define CONFIG_SPL_GD_ADDR\t\t(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)\n+#ifdef CONFIG_NAND\n+#define CONFIG_ENV_ADDR\t\t\t(CONFIG_SPL_GD_ADDR + 4 * 1024)\n+#endif\n+#define CONFIG_SPL_RELOC_MALLOC_ADDR\t(CONFIG_SPL_GD_ADDR + 10 * 1024)\n+#define CONFIG_SPL_RELOC_MALLOC_SIZE\t(34 << 10)\n+#define CONFIG_SPL_RELOC_STACK\t\t(CONFIG_SPL_GD_ADDR + 64 * 1024)\n+#define CONFIG_SPL_RELOC_STACK_SIZE\t(20 << 10)\n \n #ifdef CONFIG_PHYS_64BIT\n #define CONFIG_SYS_DCSRBAR\t\t0xf0000000\n@@ -193,7 +235,9 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_DDR_SPD\n #define CONFIG_SYS_DDR_RAW_TIMING\n #define CONFIG_SYS_FSL_DDR3\n+#ifndef CONFIG_SPL_BUILD\n #define CONFIG_FSL_DDR_INTERACTIVE\n+#endif\n \n #define CONFIG_SYS_SPD_BUS_NUM\t0\n #define SPD_EEPROM_ADDRESS1\t0x51\n@@ -381,7 +425,11 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_SYS_CS1_FTIM2\t\tCONFIG_SYS_NOR_FTIM2\n #define CONFIG_SYS_CS1_FTIM3\t\tCONFIG_SYS_NOR_FTIM3\n \n-#define CONFIG_SYS_MONITOR_BASE\t\tCONFIG_SYS_TEXT_BASE\n+#ifdef CONFIG_SPL_BUILD\n+#define CONFIG_SYS_MONITOR_BASE\tCONFIG_SPL_TEXT_BASE\n+#else\n+#define CONFIG_SYS_MONITOR_BASE\tCONFIG_SYS_TEXT_BASE\t/* start of monitor */\n+#endif\n \n #if defined(CONFIG_RAMBOOT_PBL)\n #define CONFIG_SYS_RAMBOOT\n@@ -435,7 +483,9 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_SYS_NS16550_COM3\t(CONFIG_SYS_CCSRBAR+0x11D500)\n #define CONFIG_SYS_NS16550_COM4\t(CONFIG_SYS_CCSRBAR+0x11D600)\n #define CONFIG_SERIAL_MULTI\t\t/* Enable both serial ports */\n+#ifndef CONFIG_SPL_BUILD\n #define CONFIG_SYS_CONSOLE_IS_IN_ENV\t/* determine from environment */\n+#endif\n \n \n /* Use the HUSH parser */\n@@ -607,7 +657,7 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_SYS_QE_FMAN_FW_ADDR\t(512 * 1130)\n #elif defined(CONFIG_NAND)\n #define CONFIG_SYS_QE_FMAN_FW_IN_NAND\n-#define CONFIG_SYS_QE_FMAN_FW_ADDR\t(8 * CONFIG_SYS_NAND_BLOCK_SIZE)\n+#define CONFIG_SYS_QE_FMAN_FW_ADDR\t(11 * CONFIG_SYS_NAND_BLOCK_SIZE)\n #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)\n /*\n * Slave has no ucode locally, it can fetch this from remote. When implementing\n", "prefixes": [ "U-Boot", "9/10" ] }