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GET /api/patches/291442/?format=api
{ "id": 291442, "url": "http://patchwork.ozlabs.org/api/patches/291442/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1384487159-43032-8-git-send-email-fenghua@phytium.com.cn/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1384487159-43032-8-git-send-email-fenghua@phytium.com.cn>", "list_archive_url": null, "date": "2013-11-15T03:45:56", "name": "[U-Boot,v15,07/10] arm64: core support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "7bc9a114c90a03883cfa6a45c4cc8ec85b109a33", "submitter": { "id": 34808, "url": "http://patchwork.ozlabs.org/api/people/34808/?format=api", "name": null, "email": "fenghua@phytium.com.cn" }, "delegate": { "id": 1694, "url": "http://patchwork.ozlabs.org/api/users/1694/?format=api", "username": "aaribaud", "first_name": "Albert", "last_name": "ARIBAUD", "email": "albert.aribaud@free.fr" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1384487159-43032-8-git-send-email-fenghua@phytium.com.cn/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/291442/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/291442/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 020132C00BC\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 15 Nov 2013 14:49:12 +1100 (EST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id E53204ADCC;\n\tFri, 15 Nov 2013 04:48:43 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id Yq-UJGYd5WQ6; Fri, 15 Nov 2013 04:48:43 +0100 (CET)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 33C084AE21;\n\tFri, 15 Nov 2013 04:48:20 +0100 (CET)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id A78874ADC6\n\tfor <u-boot@lists.denx.de>; Fri, 15 Nov 2013 04:48:13 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id PwZ4OFHu79Jf for <u-boot@lists.denx.de>;\n\tFri, 15 Nov 2013 04:48:08 +0100 (CET)", "from mail.corpease.net (mail37.corpease.net [61.145.121.42])\n\tby theia.denx.de (Postfix) with ESMTP id 06F6E4ADE4\n\tfor <u-boot@lists.denx.de>; Fri, 15 Nov 2013 04:47:43 +0100 (CET)", "from localhost (unknown [220.202.153.92])\n\tby mail37.corpease.net (Coremail) with SMTP id\n\tKgGowJBrOgQ_mYVSRQQzAA--.40290S3; \n\tFri, 15 Nov 2013 11:47:13 +0800 (CST)" ], "X-Virus-Scanned": [ "Debian amavisd-new at theia.denx.de", "Debian amavisd-new at theia.denx.de" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tBL_NJABL=ERR(-1.5) (only DNSBL check requested)", "From": "fenghua@phytium.com.cn", "To": "u-boot@lists.denx.de", "Date": "Fri, 15 Nov 2013 11:45:56 +0800", "Message-Id": "<1384487159-43032-8-git-send-email-fenghua@phytium.com.cn>", "X-Mailer": "git-send-email 1.7.9.5", "In-Reply-To": "<1384487159-43032-7-git-send-email-fenghua@phytium.com.cn>", "References": "<1384487159-43032-1-git-send-email-fenghua@phytium.com.cn>\n\t<1384487159-43032-2-git-send-email-fenghua@phytium.com.cn>\n\t<1384487159-43032-3-git-send-email-fenghua@phytium.com.cn>\n\t<1384487159-43032-4-git-send-email-fenghua@phytium.com.cn>\n\t<1384487159-43032-5-git-send-email-fenghua@phytium.com.cn>\n\t<1384487159-43032-6-git-send-email-fenghua@phytium.com.cn>\n\t<1384487159-43032-7-git-send-email-fenghua@phytium.com.cn>", "X-CM-TRANSID": "KgGowJBrOgQ_mYVSRQQzAA--.40290S3", "X-Coremail-Antispam": "1UD129KBjvAXoWDAryDWr45CF13KF4UZFy3XFb_yoWxJr17Co\n\tWavF4qgw4rGrZrCrs8Cw1DtFW7Xrn5Kry7Zw15tFW5XF12y3WDGr17Kw45ZFy5GF18Kw1k\n\tuFya93Z7XrWrtr93n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3\n\tAaLaJ3UjIYCTnIWjp_UUUOW7k042IEc7kJM7k042IE4IxYO2xFxVAqjxCEw4Av424lb7IF\n\t0VCFvT92vfvE14ylb7IF0VCIc40E14yl14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8V\n\tAvwI8IcIk0rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK\n\t67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26r1I6r4UM28EF7xvwVC0I7IYx2IY6xkF7I\n\t0E14v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr0_Cr1l84ACjcxK6I8E87Iv6xkF7I0E\n\t14v26r4j6r4UJwAawVCI420E548m6r1fJF45GwAS0I0E0xvYzxvE52x082IY62kv0487Mc\n\t804VCqF7xvr2I5Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUAVWU\n\ttwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI4\n\t8JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwAKzVCY07xG64k0F24lc2xSY4AK67AK6r48MxAI\n\tw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMxCIbVAxMI8I3I0E5I8CrVAFwI\n\t0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y\n\t0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1I6r4UMIIF0xvE2Ix0cI8IcVCY1x0267AKxV\n\tW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1l\n\tIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7x5xrUlUUUUU\n\tU==", "X-Originating-IP": "[220.202.153.92]", "X-CM-SenderInfo": "pihqwxdxd61x51wl3zoofrzhdfq/", "Cc": "trini@ti.com, scottwood@freescale.com", "Subject": "[U-Boot] [PATCH v15 07/10] arm64: core support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.11", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "From: David Feng <fenghua@phytium.com.cn>\n\nRelocation code based on a patch by Scott Wood, which is:\nSigned-off-by: Scott Wood <scottwood@freescale.com>\n\nSigned-off-by: David Feng <fenghua@phytium.com.cn>\n---\n arch/arm/config.mk | 3 +-\n arch/arm/cpu/armv8/Makefile | 17 +++\n arch/arm/cpu/armv8/cache.S | 136 +++++++++++++++++++\n arch/arm/cpu/armv8/cache_v8.c | 219 +++++++++++++++++++++++++++++++\n arch/arm/cpu/armv8/config.mk | 15 +++\n arch/arm/cpu/armv8/cpu.c | 43 ++++++\n arch/arm/cpu/armv8/exceptions.S | 113 ++++++++++++++++\n arch/arm/cpu/armv8/generic_timer.c | 31 +++++\n arch/arm/cpu/armv8/gic.S | 106 +++++++++++++++\n arch/arm/cpu/armv8/start.S | 164 +++++++++++++++++++++++\n arch/arm/cpu/armv8/tlb.S | 34 +++++\n arch/arm/cpu/armv8/transition.S | 83 ++++++++++++\n arch/arm/cpu/armv8/u-boot.lds | 89 +++++++++++++\n arch/arm/include/asm/armv8/mmu.h | 111 ++++++++++++++++\n arch/arm/include/asm/byteorder.h | 12 ++\n arch/arm/include/asm/cache.h | 5 +\n arch/arm/include/asm/config.h | 6 +\n arch/arm/include/asm/gic.h | 49 ++++++-\n arch/arm/include/asm/global_data.h | 6 +-\n arch/arm/include/asm/io.h | 15 ++-\n arch/arm/include/asm/macro.h | 53 ++++++++\n arch/arm/include/asm/posix_types.h | 10 ++\n arch/arm/include/asm/proc-armv/ptrace.h | 21 +++\n arch/arm/include/asm/proc-armv/system.h | 59 ++++++++-\n arch/arm/include/asm/system.h | 84 ++++++++++++\n arch/arm/include/asm/types.h | 4 +\n arch/arm/include/asm/u-boot.h | 4 +\n arch/arm/include/asm/unaligned.h | 2 +-\n arch/arm/lib/Makefile | 20 ++-\n arch/arm/lib/board.c | 7 +-\n arch/arm/lib/bootm.c | 24 ++++\n arch/arm/lib/crt0_64.S | 113 ++++++++++++++++\n arch/arm/lib/interrupts_64.c | 120 +++++++++++++++++\n arch/arm/lib/relocate_64.S | 58 ++++++++\n common/image.c | 1 +\n doc/README.arm64 | 46 +++++++\n examples/standalone/stubs.c | 15 +++\n include/image.h | 1 +\n 38 files changed, 1878 insertions(+), 21 deletions(-)\n create mode 100644 arch/arm/cpu/armv8/Makefile\n create mode 100644 arch/arm/cpu/armv8/cache.S\n create mode 100644 arch/arm/cpu/armv8/cache_v8.c\n create mode 100644 arch/arm/cpu/armv8/config.mk\n create mode 100644 arch/arm/cpu/armv8/cpu.c\n create mode 100644 arch/arm/cpu/armv8/exceptions.S\n create mode 100644 arch/arm/cpu/armv8/generic_timer.c\n create mode 100644 arch/arm/cpu/armv8/gic.S\n create mode 100644 arch/arm/cpu/armv8/start.S\n create mode 100644 arch/arm/cpu/armv8/tlb.S\n create mode 100644 arch/arm/cpu/armv8/transition.S\n create mode 100644 arch/arm/cpu/armv8/u-boot.lds\n create mode 100644 arch/arm/include/asm/armv8/mmu.h\n create mode 100644 arch/arm/lib/crt0_64.S\n create mode 100644 arch/arm/lib/interrupts_64.c\n create mode 100644 arch/arm/lib/relocate_64.S\n create mode 100644 doc/README.arm64", "diff": "diff --git a/arch/arm/config.mk b/arch/arm/config.mk\nindex bdabcf4..49cc7cc 100644\n--- a/arch/arm/config.mk\n+++ b/arch/arm/config.mk\n@@ -17,7 +17,8 @@ endif\n \n LDFLAGS_FINAL += --gc-sections\n PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \\\n-\t\t -fno-common -ffixed-r9 -msoft-float\n+\t\t -fno-common -ffixed-r9\n+PLATFORM_RELFLAGS += $(call cc-option, -msoft-float)\n \n # Support generic board on ARM\n __HAVE_ARCH_GENERIC_BOARD := y\ndiff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile\nnew file mode 100644\nindex 0000000..b6eb6de\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/Makefile\n@@ -0,0 +1,17 @@\n+#\n+# (C) Copyright 2000-2003\n+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+extra-y\t:= start.o\n+\n+obj-y\t+= cpu.o\n+obj-y\t+= generic_timer.o\n+obj-y\t+= cache_v8.o\n+obj-y\t+= exceptions.o\n+obj-y\t+= cache.o\n+obj-y\t+= tlb.o\n+obj-y\t+= gic.o\n+obj-y\t+= transition.o\ndiff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S\nnew file mode 100644\nindex 0000000..546a83e\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/cache.S\n@@ -0,0 +1,136 @@\n+/*\n+ * (C) Copyright 2013\n+ * David Feng <fenghua@phytium.com.cn>\n+ *\n+ * This file is based on sample code from ARMv8 ARM.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <asm-offsets.h>\n+#include <config.h>\n+#include <version.h>\n+#include <asm/macro.h>\n+#include <linux/linkage.h>\n+\n+/*\n+ * void __asm_flush_dcache_level(level)\n+ *\n+ * clean and invalidate one level cache.\n+ *\n+ * x0: cache level\n+ * x1~x9: clobbered\n+ */\n+ENTRY(__asm_flush_dcache_level)\n+\tlsl\tx1, x0, #1\n+\tmsr\tcsselr_el1, x1\t\t/* select cache level */\n+\tisb\t\t\t\t/* sync change of cssidr_el1 */\n+\tmrs\tx6, ccsidr_el1\t\t/* read the new cssidr_el1 */\n+\tand\tx2, x6, #7\t\t/* x2 <- log2(cache line size)-4 */\n+\tadd\tx2, x2, #4\t\t/* x2 <- log2(cache line size) */\n+\tmov\tx3, #0x3ff\n+\tand\tx3, x3, x6, lsr #3\t/* x3 <- max number of #ways */\n+\tadd\tw4, w3, w3\n+\tsub\tw4, w4, 1\t\t/* round up log2(#ways + 1) */\n+\tclz\tw5, w4\t\t\t/* bit position of #ways */\n+\tmov\tx4, #0x7fff\n+\tand\tx4, x4, x6, lsr #13\t/* x4 <- max number of #sets */\n+\t/* x1 <- cache level << 1 */\n+\t/* x2 <- line length offset */\n+\t/* x3 <- number of cache ways - 1 */\n+\t/* x4 <- number of cache sets - 1 */\n+\t/* x5 <- bit position of #ways */\n+\n+loop_set:\n+\tmov\tx6, x3\t\t\t/* x6 <- working copy of #ways */\n+loop_way:\n+\tlsl\tx7, x6, x5\n+\torr\tx9, x1, x7\t\t/* map way and level to cisw value */\n+\tlsl\tx7, x4, x2\n+\torr\tx9, x9, x7\t\t/* map set number to cisw value */\n+\tdc\tcisw, x9\t\t/* clean & invalidate by set/way */\n+\tsubs\tx6, x6, #1\t\t/* decrement the way */\n+\tb.ge\tloop_way\n+\tsubs\tx4, x4, #1\t\t/* decrement the set */\n+\tb.ge\tloop_set\n+\n+\tret\n+ENDPROC(__asm_flush_dcache_level)\n+\n+/*\n+ * void __asm_flush_dcache_all(void)\n+ *\n+ * clean and invalidate all data cache by SET/WAY.\n+ */\n+ENTRY(__asm_flush_dcache_all)\n+\tdsb\tsy\n+\tmrs\tx10, clidr_el1\t\t/* read clidr_el1 */\n+\tlsr\tx11, x10, #24\n+\tand\tx11, x11, #0x7\t\t/* x11 <- loc */\n+\tcbz\tx11, finished\t\t/* if loc is 0, exit */\n+\tmov\tx15, lr\n+\tmov\tx0, #0\t\t\t/* start flush at cache level 0 */\n+\t/* x0 <- cache level */\n+\t/* x10 <- clidr_el1 */\n+\t/* x11 <- loc */\n+\t/* x15 <- return address */\n+\n+loop_level:\n+\tlsl\tx1, x0, #1\n+\tadd\tx1, x1, x0\t\t/* x0 <- tripled cache level */\n+\tlsr\tx1, x10, x1\n+\tand\tx1, x1, #7\t\t/* x1 <- cache type */\n+\tcmp\tx1, #2\n+\tb.lt\tskip\t\t\t/* skip if no cache or icache */\n+\tbl\t__asm_flush_dcache_level\n+skip:\n+\tadd\tx0, x0, #1\t\t/* increment cache level */\n+\tcmp\tx11, x0\n+\tb.gt\tloop_level\n+\n+\tmov\tx0, #0\n+\tmsr\tcsselr_el1, x0\t\t/* resotre csselr_el1 */\n+\tdsb\tsy\n+\tisb\n+\tmov\tlr, x15\n+\n+finished:\n+\tret\n+ENDPROC(__asm_flush_dcache_all)\n+\n+/*\n+ * void __asm_flush_dcache_range(start, end)\n+ *\n+ * clean & invalidate data cache in the range\n+ *\n+ * x0: start address\n+ * x1: end address\n+ */\n+ENTRY(__asm_flush_dcache_range)\n+\tmrs\tx3, ctr_el0\n+\tlsr\tx3, x3, #16\n+\tand\tx3, x3, #0xf\n+\tmov\tx2, #4\n+\tlsl\tx2, x2, x3\t\t/* cache line size */\n+\n+\t/* x2 <- minimal cache line size in cache system */\n+\tsub\tx3, x2, #1\n+\tbic\tx0, x0, x3\n+1:\tdc\tcivac, x0\t/* clean & invalidate data or unified cache */\n+\tadd\tx0, x0, x2\n+\tcmp\tx0, x1\n+\tb.lo\t1b\n+\tdsb\tsy\n+\tret\n+ENDPROC(__asm_flush_dcache_range)\n+\n+/*\n+ * void __asm_invalidate_icache_all(void)\n+ *\n+ * invalidate all tlb entries.\n+ */\n+ENTRY(__asm_invalidate_icache_all)\n+\tic\tialluis\n+\tisb\tsy\n+\tret\n+ENDPROC(__asm_invalidate_icache_all)\ndiff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c\nnew file mode 100644\nindex 0000000..131fdab\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/cache_v8.c\n@@ -0,0 +1,219 @@\n+/*\n+ * (C) Copyright 2013\n+ * David Feng <fenghua@phytium.com.cn>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/system.h>\n+#include <asm/armv8/mmu.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+#ifndef CONFIG_SYS_DCACHE_OFF\n+\n+static void set_pgtable_section(u64 section, u64 memory_type)\n+{\n+\tu64 *page_table = (u64 *)gd->arch.tlb_addr;\n+\tu64 value;\n+\n+\tvalue = (section << SECTION_SHIFT) | PMD_TYPE_SECT | PMD_SECT_AF;\n+\tvalue |= PMD_ATTRINDX(memory_type);\n+\tpage_table[section] = value;\n+}\n+\n+/* to activate the MMU we need to set up virtual memory */\n+static void mmu_setup(void)\n+{\n+\tint i, j, el;\n+\tbd_t *bd = gd->bd;\n+\n+\t/* Setup an identity-mapping for all spaces */\n+\tfor (i = 0; i < (PGTABLE_SIZE >> 3); i++)\n+\t\tset_pgtable_section(i, MT_DEVICE_NGNRNE);\n+\n+\t/* Setup an identity-mapping for all RAM space */\n+\tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n+\t\tulong start = bd->bi_dram[i].start;\n+\t\tulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;\n+\t\tfor (j = start >> SECTION_SHIFT;\n+\t\t j < end >> SECTION_SHIFT; j++) {\n+\t\t\tset_pgtable_section(j, MT_NORMAL);\n+\t\t}\n+\t}\n+\n+\t/* load TTBR0 */\n+\tel = current_el();\n+\tif (el == 1)\n+\t\tasm volatile(\"msr ttbr0_el1, %0\"\n+\t\t\t : : \"r\" (gd->arch.tlb_addr) : \"memory\");\n+\telse if (el == 2)\n+\t\tasm volatile(\"msr ttbr0_el2, %0\"\n+\t\t\t : : \"r\" (gd->arch.tlb_addr) : \"memory\");\n+\telse\n+\t\tasm volatile(\"msr ttbr0_el3, %0\"\n+\t\t\t : : \"r\" (gd->arch.tlb_addr) : \"memory\");\n+\n+\t/* enable the mmu */\n+\tset_sctlr(get_sctlr() | CR_M);\n+}\n+\n+/*\n+ * Performs a invalidation of the entire data cache at all levels\n+ */\n+void invalidate_dcache_all(void)\n+{\n+\t__asm_flush_dcache_all();\n+}\n+\n+/*\n+ * Performs a clean & invalidation of the entire data cache at all levels\n+ */\n+void flush_dcache_all(void)\n+{\n+\t__asm_flush_dcache_all();\n+}\n+\n+/*\n+ * Invalidates range in all levels of D-cache/unified cache\n+ */\n+void invalidate_dcache_range(unsigned long start, unsigned long stop)\n+{\n+\t__asm_flush_dcache_range(start, stop);\n+}\n+\n+/*\n+ * Flush range(clean & invalidate) from all levels of D-cache/unified cache\n+ */\n+void flush_dcache_range(unsigned long start, unsigned long stop)\n+{\n+\t__asm_flush_dcache_range(start, stop);\n+}\n+\n+void dcache_enable(void)\n+{\n+\t/* The data cache is not active unless the mmu is enabled */\n+\tif (!(get_sctlr() & CR_M)) {\n+\t\tinvalidate_dcache_all();\n+\t\t__asm_invalidate_tlb_all();\n+\t\tmmu_setup();\n+\t}\n+\n+\tset_sctlr(get_sctlr() | CR_C);\n+}\n+\n+void dcache_disable(void)\n+{\n+\tuint32_t sctlr;\n+\n+\tsctlr = get_sctlr();\n+\n+\t/* if cache isn't enabled no need to disable */\n+\tif (!(sctlr & CR_C))\n+\t\treturn;\n+\n+\tset_sctlr(sctlr & ~(CR_C|CR_M));\n+\n+\tflush_dcache_all();\n+\t__asm_invalidate_tlb_all();\n+}\n+\n+int dcache_status(void)\n+{\n+\treturn (get_sctlr() & CR_C) != 0;\n+}\n+\n+#else\t/* CONFIG_SYS_DCACHE_OFF */\n+\n+void invalidate_dcache_all(void)\n+{\n+}\n+\n+void flush_dcache_all(void)\n+{\n+}\n+\n+void invalidate_dcache_range(unsigned long start, unsigned long stop)\n+{\n+}\n+\n+void flush_dcache_range(unsigned long start, unsigned long stop)\n+{\n+}\n+\n+void dcache_enable(void)\n+{\n+}\n+\n+void dcache_disable(void)\n+{\n+}\n+\n+int dcache_status(void)\n+{\n+\treturn 0;\n+}\n+\n+#endif\t/* CONFIG_SYS_DCACHE_OFF */\n+\n+#ifndef CONFIG_SYS_ICACHE_OFF\n+\n+void icache_enable(void)\n+{\n+\tset_sctlr(get_sctlr() | CR_I);\n+}\n+\n+void icache_disable(void)\n+{\n+\tset_sctlr(get_sctlr() & ~CR_I);\n+}\n+\n+int icache_status(void)\n+{\n+\treturn (get_sctlr() & CR_I) != 0;\n+}\n+\n+void invalidate_icache_all(void)\n+{\n+\t__asm_invalidate_icache_all();\n+}\n+\n+#else\t/* CONFIG_SYS_ICACHE_OFF */\n+\n+void icache_enable(void)\n+{\n+}\n+\n+void icache_disable(void)\n+{\n+}\n+\n+int icache_status(void)\n+{\n+\treturn 0;\n+}\n+\n+void invalidate_icache_all(void)\n+{\n+}\n+\n+#endif\t/* CONFIG_SYS_ICACHE_OFF */\n+\n+/*\n+ * Enable dCache & iCache, whether cache is actually enabled\n+ * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF\n+ */\n+void enable_caches(void)\n+{\n+\ticache_enable();\n+\tdcache_enable();\n+}\n+\n+/*\n+ * Flush range from all levels of d-cache/unified-cache\n+ */\n+void flush_cache(unsigned long start, unsigned long size)\n+{\n+\tflush_dcache_range(start, start + size);\n+}\ndiff --git a/arch/arm/cpu/armv8/config.mk b/arch/arm/cpu/armv8/config.mk\nnew file mode 100644\nindex 0000000..027a68c\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/config.mk\n@@ -0,0 +1,15 @@\n+#\n+# (C) Copyright 2002\n+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+PLATFORM_RELFLAGS += -fno-common -ffixed-x18\n+\n+# SEE README.arm-unaligned-accesses\n+PF_NO_UNALIGNED := $(call cc-option, -mstrict-align)\n+PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)\n+\n+PF_CPPFLAGS_ARMV8 := $(call cc-option, -march=armv8-a)\n+PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV8)\n+PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED)\ndiff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c\nnew file mode 100644\nindex 0000000..e06c3cc\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/cpu.c\n@@ -0,0 +1,43 @@\n+/*\n+ * (C) Copyright 2008 Texas Insturments\n+ *\n+ * (C) Copyright 2002\n+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>\n+ * Marius Groeger <mgroeger@sysgo.de>\n+ *\n+ * (C) Copyright 2002\n+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <command.h>\n+#include <asm/system.h>\n+#include <linux/compiler.h>\n+\n+int cleanup_before_linux(void)\n+{\n+\t/*\n+\t * this function is called just before we call linux\n+\t * it prepares the processor for linux\n+\t *\n+\t * disable interrupt and turn off caches etc ...\n+\t */\n+\tdisable_interrupts();\n+\n+\t/*\n+\t * Turn off I-cache and invalidate it\n+\t */\n+\ticache_disable();\n+\tinvalidate_icache_all();\n+\n+\t/*\n+\t * turn off D-cache\n+\t * dcache_disable() in turn flushes the d-cache and disables MMU\n+\t */\n+\tdcache_disable();\n+\tinvalidate_dcache_all();\n+\n+\treturn 0;\n+}\ndiff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S\nnew file mode 100644\nindex 0000000..b91a1b6\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/exceptions.S\n@@ -0,0 +1,113 @@\n+/*\n+ * (C) Copyright 2013\n+ * David Feng <fenghua@phytium.com.cn>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <asm-offsets.h>\n+#include <config.h>\n+#include <version.h>\n+#include <asm/ptrace.h>\n+#include <asm/macro.h>\n+#include <linux/linkage.h>\n+\n+/*\n+ * Enter Exception.\n+ * This will save the processor state that is ELR/X0~X30\n+ * to the stack frame.\n+ */\n+.macro\texception_entry\n+\tstp\tx29, x30, [sp, #-16]!\n+\tstp\tx27, x28, [sp, #-16]!\n+\tstp\tx25, x26, [sp, #-16]!\n+\tstp\tx23, x24, [sp, #-16]!\n+\tstp\tx21, x22, [sp, #-16]!\n+\tstp\tx19, x20, [sp, #-16]!\n+\tstp\tx17, x18, [sp, #-16]!\n+\tstp\tx15, x16, [sp, #-16]!\n+\tstp\tx13, x14, [sp, #-16]!\n+\tstp\tx11, x12, [sp, #-16]!\n+\tstp\tx9, x10, [sp, #-16]!\n+\tstp\tx7, x8, [sp, #-16]!\n+\tstp\tx5, x6, [sp, #-16]!\n+\tstp\tx3, x4, [sp, #-16]!\n+\tstp\tx1, x2, [sp, #-16]!\n+\n+\t/* Could be running at EL3/EL2/EL1 */\n+\tswitch_el x11, 3f, 2f, 1f\n+3:\tmrs\tx1, esr_el3\n+\tmrs\tx2, elr_el3\n+\tb\t0f\n+2:\tmrs\tx1, esr_el2\n+\tmrs\tx2, elr_el2\n+\tb\t0f\n+1:\tmrs\tx1, esr_el1\n+\tmrs\tx2, elr_el1\n+0:\n+\tstp\tx2, x0, [sp, #-16]!\n+\tmov\tx0, sp\n+.endm\n+\n+/*\n+ * Exception vectors.\n+ */\n+\t.align\t11\n+\t.globl\tvectors\n+vectors:\n+\t.align\t7\n+\tb\t_do_bad_sync\t/* Current EL Synchronous Thread */\n+\n+\t.align\t7\n+\tb\t_do_bad_irq\t/* Current EL IRQ Thread */\n+\n+\t.align\t7\n+\tb\t_do_bad_fiq\t/* Current EL FIQ Thread */\n+\n+\t.align\t7\n+\tb\t_do_bad_error\t/* Current EL Error Thread */\n+\n+\t.align\t7\n+\tb\t_do_sync\t/* Current EL Synchronous Handler */\n+\n+\t.align\t7\n+\tb\t_do_irq\t\t/* Current EL IRQ Handler */\n+\n+\t.align\t7\n+\tb\t_do_fiq\t\t/* Current EL FIQ Handler */\n+\n+\t.align\t7\n+\tb\t_do_error\t/* Current EL Error Handler */\n+\n+\n+_do_bad_sync:\n+\texception_entry\n+\tbl\tdo_bad_sync\n+\n+_do_bad_irq:\n+\texception_entry\n+\tbl\tdo_bad_irq\n+\n+_do_bad_fiq:\n+\texception_entry\n+\tbl\tdo_bad_fiq\n+\n+_do_bad_error:\n+\texception_entry\n+\tbl\tdo_bad_error\n+\n+_do_sync:\n+\texception_entry\n+\tbl\tdo_sync\n+\n+_do_irq:\n+\texception_entry\n+\tbl\tdo_irq\n+\n+_do_fiq:\n+\texception_entry\n+\tbl\tdo_fiq\n+\n+_do_error:\n+\texception_entry\n+\tbl\tdo_error\ndiff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c\nnew file mode 100644\nindex 0000000..223b95e\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/generic_timer.c\n@@ -0,0 +1,31 @@\n+/*\n+ * (C) Copyright 2013\n+ * David Feng <fenghua@phytium.com.cn>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <command.h>\n+#include <asm/system.h>\n+\n+/*\n+ * Generic timer implementation of get_tbclk()\n+ */\n+unsigned long get_tbclk(void)\n+{\n+\tunsigned long cntfrq;\n+\tasm volatile(\"mrs %0, cntfrq_el0\" : \"=r\" (cntfrq));\n+\treturn cntfrq;\n+}\n+\n+/*\n+ * Generic timer implementation of timer_read_counter()\n+ */\n+unsigned long timer_read_counter(void)\n+{\n+\tunsigned long cntpct;\n+\tisb();\n+\tasm volatile(\"mrs %0, cntpct_el0\" : \"=r\" (cntpct));\n+\treturn cntpct;\n+}\ndiff --git a/arch/arm/cpu/armv8/gic.S b/arch/arm/cpu/armv8/gic.S\nnew file mode 100644\nindex 0000000..599aa8f\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/gic.S\n@@ -0,0 +1,106 @@\n+/*\n+ * GIC Initialization Routines.\n+ *\n+ * (C) Copyright 2013\n+ * David Feng <fenghua@phytium.com.cn>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <asm-offsets.h>\n+#include <config.h>\n+#include <linux/linkage.h>\n+#include <asm/macro.h>\n+#include <asm/gic.h>\n+\n+\n+/*************************************************************************\n+ *\n+ * void gic_init(void) __attribute__((weak));\n+ *\n+ * Currently, this routine only initialize secure copy of GIC\n+ * with Security Extensions at EL3.\n+ *\n+ *************************************************************************/\n+WEAK(gic_init)\n+\tbranch_if_slave\tx0, 2f\n+\n+\t/* Initialize Distributor and SPIs */\n+\tldr\tx1, =GICD_BASE\n+\tmov\tw0, #0x3\t\t/* EnableGrp0 | EnableGrp1 */\n+\tstr\tw0, [x1, GICD_CTLR]\t/* Secure GICD_CTLR */\n+\tldr\tw0, [x1, GICD_TYPER]\n+\tand\tw2, w0, #0x1f\t\t/* ITLinesNumber */\n+\tcbz\tw2, 2f\t\t\t/* No SPIs */\n+\tadd\tx1, x1, (GICD_IGROUPRn + 4)\n+\tmov\tw0, #~0\t\t\t/* Config SPIs as Grp1 */\n+1:\tstr\tw0, [x1], #0x4\n+\tsub\tw2, w2, #0x1\n+\tcbnz\tw2, 1b\n+\n+\t/* Initialize SGIs and PPIs */\n+2:\tldr\tx1, =GICD_BASE\n+\tmov\tw0, #~0\t\t\t/* Config SGIs and PPIs as Grp1 */\n+\tstr\tw0, [x1, GICD_IGROUPRn]\t/* GICD_IGROUPR0 */\n+\tmov\tw0, #0x1\t\t/* Enable SGI 0 */\n+\tstr\tw0, [x1, GICD_ISENABLERn]\n+\n+\t/* Initialize Cpu Interface */\n+\tldr\tx1, =GICC_BASE\n+\tmov\tw0, #0x1e7\t\t/* Disable IRQ/FIQ Bypass & */\n+\t\t\t\t\t/* Enable Ack Group1 Interrupt & */\n+\t\t\t\t\t/* EnableGrp0 & EnableGrp1 */\n+\tstr\tw0, [x1, GICC_CTLR]\t/* Secure GICC_CTLR */\n+\n+\tmov\tw0, #0x1 << 7\t\t/* Non-Secure access to GICC_PMR */\n+\tstr\tw0, [x1, GICC_PMR]\n+\n+\tret\n+ENDPROC(gic_init)\n+\n+\n+/*************************************************************************\n+ *\n+ * void gic_send_sgi(u64 sgi) __attribute__((weak));\n+ *\n+ *************************************************************************/\n+WEAK(gic_send_sgi)\n+\tldr\tx1, =GICD_BASE\n+\tmov\tw2, #0x8000\n+\tmovk\tw2, #0x100, lsl #16\n+\torr\tw2, w2, w0\n+\tstr\tw2, [x1, GICD_SGIR]\n+\tret\n+ENDPROC(gic_send_sgi)\n+\n+\n+/*************************************************************************\n+ *\n+ * void wait_for_wakeup(void) __attribute__((weak));\n+ *\n+ * Wait for SGI 0 from master.\n+ *\n+ *************************************************************************/\n+WEAK(wait_for_wakeup)\n+\tldr\tx1, =GICC_BASE\n+0:\twfi\n+\tldr\tw0, [x1, GICC_AIAR]\n+\tstr\tw0, [x1, GICC_AEOIR]\n+\tcbnz\tw0, 0b\n+\tret\n+ENDPROC(wait_for_wakeup)\n+\n+\n+/*************************************************************************\n+ *\n+ * void smp_kick_all_cpus(void) __attribute__((weak));\n+ *\n+ *************************************************************************/\n+WEAK(smp_kick_all_cpus)\n+\t/* Kick secondary cpus up by SGI 0 interrupt */\n+\tmov\tx0, xzr\t\t\t/* SGI 0 */\n+\tmov\tx29, lr\t\t\t/* Save LR */\n+\tbl\tgic_send_sgi\n+\tmov\tlr, x29\t\t\t/* Restore LR */\n+\tret\n+ENDPROC(smp_kick_all_cpus)\ndiff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S\nnew file mode 100644\nindex 0000000..bcc2603\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/start.S\n@@ -0,0 +1,164 @@\n+/*\n+ * (C) Copyright 2013\n+ * David Feng <fenghua@phytium.com.cn>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <asm-offsets.h>\n+#include <config.h>\n+#include <version.h>\n+#include <linux/linkage.h>\n+#include <asm/macro.h>\n+#include <asm/armv8/mmu.h>\n+\n+/*************************************************************************\n+ *\n+ * Startup Code (reset vector)\n+ *\n+ *************************************************************************/\n+\n+.globl\t_start\n+_start:\n+\tb\treset\n+\n+\t.align 3\n+\n+.globl\t_TEXT_BASE\n+_TEXT_BASE:\n+\t.quad\tCONFIG_SYS_TEXT_BASE\n+\n+/*\n+ * These are defined in the linker script.\n+ */\n+.globl\t_end_ofs\n+_end_ofs:\n+\t.quad\t_end - _start\n+\n+.globl\t_bss_start_ofs\n+_bss_start_ofs:\n+\t.quad\t__bss_start - _start\n+\n+.globl\t_bss_end_ofs\n+_bss_end_ofs:\n+\t.quad\t__bss_end - _start\n+\n+reset:\n+\t/*\n+\t * Could be EL3/EL2/EL1, Initial State:\n+\t * Little Endian, MMU Disabled, i/dCache Disabled\n+\t */\n+\tadr\tx0, vectors\n+\tswitch_el x1, 3f, 2f, 1f\n+3:\tmsr\tvbar_el3, x0\n+\tmsr\tcptr_el3, xzr\t\t\t/* Enable FP/SIMD */\n+\tldr\tx0, =COUNTER_FREQUENCY\n+\tmsr\tcntfrq_el0, x0\t\t\t/* Initialize CNTFRQ */\n+\tb\t0f\n+2:\tmsr\tvbar_el2, x0\n+\tmov\tx0, #0x33ff\n+\tmsr\tcptr_el2, x0\t\t\t/* Enable FP/SIMD */\n+\tb\t0f\n+1:\tmsr\tvbar_el1, x0\n+\tmov\tx0, #3 << 20\n+\tmsr\tcpacr_el1, x0\t\t\t/* Enable FP/SIMD */\n+0:\n+\n+\t/* Cache/BPB/TLB Invalidate */\n+\tbl\t__asm_flush_dcache_all\t\t/* dCache clean&invalidate */\n+\tbl\t__asm_invalidate_icache_all\t/* iCache invalidate */\n+\tbl\t__asm_invalidate_tlb_all\t/* invalidate TLBs */\n+\n+\t/* Processor specific initialization */\n+\tbl\tlowlevel_init\n+\n+\tbranch_if_master x0, x1, master_cpu\n+\n+\t/*\n+\t * Slave CPUs\n+\t */\n+slave_cpu:\n+\twfe\n+\tldr\tx1, =CPU_RELEASE_ADDR\n+\tldr\tx0, [x1]\n+\tcbz\tx0, slave_cpu\n+\tbr\tx0\t\t\t/* branch to the given address */\n+\n+\t/*\n+\t * Master CPU\n+\t */\n+master_cpu:\n+\tbl\t_main\n+\n+/*-----------------------------------------------------------------------*/\n+\n+WEAK(lowlevel_init)\n+\t/* Initialize GIC Secure Bank Status */\n+\tmov\tx29, lr\t\t\t/* Save LR */\n+\tbl\tgic_init\n+\n+\tbranch_if_master x0, x1, 1f\n+\n+\t/*\n+\t * Slave should wait for master clearing spin table.\n+\t * This sync prevent salves observing incorrect\n+\t * value of spin table and jumping to wrong place.\n+\t */\n+\tbl\twait_for_wakeup\n+\n+\t/*\n+\t * All processors will enter EL2 and optionally EL1.\n+\t */\n+\tbl\tarmv8_switch_to_el2\n+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1\n+\tbl\tarmv8_switch_to_el1\n+#endif\n+\n+1:\n+\tmov\tlr, x29\t\t\t/* Restore LR */\n+\tret\n+ENDPROC(lowlevel_init)\n+\n+/*-----------------------------------------------------------------------*/\n+\n+ENTRY(c_runtime_cpu_setup)\n+\t/* If I-cache is enabled invalidate it */\n+#ifndef CONFIG_SYS_ICACHE_OFF\n+\tic\tiallu\t\t\t/* I+BTB cache invalidate */\n+\tisb\tsy\n+#endif\n+\n+#ifndef CONFIG_SYS_DCACHE_OFF\n+\t/*\n+\t * Setup MAIR and TCR.\n+\t */\n+\tldr\tx0, =MEMORY_ATTRIBUTES\n+\tldr\tx1, =TCR_FLAGS\n+\n+\tswitch_el x2, 3f, 2f, 1f\n+3:\torr\tx1, x1, TCR_EL3_IPS_BITS\n+\tmsr\tmair_el3, x0\n+\tmsr\ttcr_el3, x1\n+\tb\t0f\n+2:\torr\tx1, x1, TCR_EL2_IPS_BITS\n+\tmsr\tmair_el2, x0\n+\tmsr\ttcr_el2, x1\n+\tb\t0f\n+1:\torr\tx1, x1, TCR_EL1_IPS_BITS\n+\tmsr\tmair_el1, x0\n+\tmsr\ttcr_el1, x1\n+0:\n+#endif\n+\n+\t/* Relocate vBAR */\n+\tadr\tx0, vectors\n+\tswitch_el x1, 3f, 2f, 1f\n+3:\tmsr\tvbar_el3, x0\n+\tb\t0f\n+2:\tmsr\tvbar_el2, x0\n+\tb\t0f\n+1:\tmsr\tvbar_el1, x0\n+0:\n+\n+\tret\n+ENDPROC(c_runtime_cpu_setup)\ndiff --git a/arch/arm/cpu/armv8/tlb.S b/arch/arm/cpu/armv8/tlb.S\nnew file mode 100644\nindex 0000000..f840b04\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/tlb.S\n@@ -0,0 +1,34 @@\n+/*\n+ * (C) Copyright 2013\n+ * David Feng <fenghua@phytium.com.cn>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <asm-offsets.h>\n+#include <config.h>\n+#include <version.h>\n+#include <linux/linkage.h>\n+#include <asm/macro.h>\n+\n+/*\n+ * void __asm_invalidate_tlb_all(void)\n+ *\n+ * invalidate all tlb entries.\n+ */\n+ENTRY(__asm_invalidate_tlb_all)\n+\tswitch_el x9, 3f, 2f, 1f\n+3:\ttlbi\talle3\n+\tdsb\tsy\n+\tisb\n+\tb\t0f\n+2:\ttlbi\talle2\n+\tdsb\tsy\n+\tisb\n+\tb\t0f\n+1:\ttlbi\tvmalle1\n+\tdsb\tsy\n+\tisb\n+0:\n+\tret\n+ENDPROC(__asm_invalidate_tlb_all)\ndiff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S\nnew file mode 100644\nindex 0000000..e0a5946\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/transition.S\n@@ -0,0 +1,83 @@\n+/*\n+ * (C) Copyright 2013\n+ * David Feng <fenghua@phytium.com.cn>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <asm-offsets.h>\n+#include <config.h>\n+#include <version.h>\n+#include <linux/linkage.h>\n+#include <asm/macro.h>\n+\n+ENTRY(armv8_switch_to_el2)\n+\tswitch_el x0, 1f, 0f, 0f\n+0:\tret\n+1:\n+\tmov\tx0, #0x5b1\t/* Non-secure EL0/EL1 | HVC | 64bit EL2 */\n+\tmsr\tscr_el3, x0\n+\tmsr\tcptr_el3, xzr\t/* Disable coprocessor traps to EL3 */\n+\tmov\tx0, #0x33ff\n+\tmsr\tcptr_el2, x0\t/* Disable coprocessor traps to EL2 */\n+\n+\t/* Initialize SCTLR_EL2 */\n+\tmsr\tsctlr_el2, xzr\n+\n+\t/* Return to the EL2_SP2 mode from EL3 */\n+\tmov\tx0, sp\n+\tmsr\tsp_el2, x0\t/* Migrate SP */\n+\tmrs\tx0, vbar_el3\n+\tmsr\tvbar_el2, x0\t/* Migrate VBAR */\n+\tmov\tx0, #0x3c9\n+\tmsr\tspsr_el3, x0\t/* EL2_SP2 | D | A | I | F */\n+\tmsr\telr_el3, lr\n+\teret\n+ENDPROC(armv8_switch_to_el2)\n+\n+ENTRY(armv8_switch_to_el1)\n+\tswitch_el x0, 0f, 1f, 0f\n+0:\tret\n+1:\n+\t/* Initialize Generic Timers */\n+\tmrs\tx0, cnthctl_el2\n+\torr\tx0, x0, #0x3\t\t/* Enable EL1 access to timers */\n+\tmsr\tcnthctl_el2, x0\n+\tmsr\tcntvoff_el2, x0\n+\tmrs\tx0, cntkctl_el1\n+\torr\tx0, x0, #0x3\t\t/* Enable EL0 access to timers */\n+\tmsr\tcntkctl_el1, x0\n+\n+\t/* Initilize MPID/MPIDR registers */\n+\tmrs\tx0, midr_el1\n+\tmrs\tx1, mpidr_el1\n+\tmsr\tvpidr_el2, x0\n+\tmsr\tvmpidr_el2, x1\n+\n+\t/* Disable coprocessor traps */\n+\tmov\tx0, #0x33ff\n+\tmsr\tcptr_el2, x0\t\t/* Disable coprocessor traps to EL2 */\n+\tmsr\thstr_el2, xzr\t\t/* Disable coprocessor traps to EL2 */\n+\tmov\tx0, #3 << 20\n+\tmsr\tcpacr_el1, x0\t\t/* Enable FP/SIMD at EL1 */\n+\n+\t/* Initialize HCR_EL2 */\n+\tmov\tx0, #(1 << 31)\t\t/* 64bit EL1 */\n+\torr\tx0, x0, #(1 << 29)\t/* Disable HVC */\n+\tmsr\thcr_el2, x0\n+\n+\t/* SCTLR_EL1 initialization */\n+\tmov\tx0, #0x0800\n+\tmovk\tx0, #0x30d0, lsl #16\n+\tmsr\tsctlr_el1, x0\n+\n+\t/* Return to the EL1_SP1 mode from EL2 */\n+\tmov\tx0, sp\n+\tmsr\tsp_el1, x0\t\t/* Migrate SP */\n+\tmrs\tx0, vbar_el2\n+\tmsr\tvbar_el1, x0\t\t/* Migrate VBAR */\n+\tmov\tx0, #0x3c5\n+\tmsr\tspsr_el2, x0\t\t/* EL1_SP1 | D | A | I | F */\n+\tmsr\telr_el2, lr\n+\teret\n+ENDPROC(armv8_switch_to_el1)\ndiff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds\nnew file mode 100644\nindex 0000000..4c12222\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/u-boot.lds\n@@ -0,0 +1,89 @@\n+/*\n+ * (C) Copyright 2013\n+ * David Feng <fenghua@phytium.com.cn>\n+ *\n+ * (C) Copyright 2002\n+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+OUTPUT_FORMAT(\"elf64-littleaarch64\", \"elf64-littleaarch64\", \"elf64-littleaarch64\")\n+OUTPUT_ARCH(aarch64)\n+ENTRY(_start)\n+SECTIONS\n+{\n+\t. = 0x00000000;\n+\n+\t. = ALIGN(8);\n+\t.text :\n+\t{\n+\t\t*(.__image_copy_start)\n+\t\tCPUDIR/start.o (.text*)\n+\t\t*(.text*)\n+\t}\n+\n+\t. = ALIGN(8);\n+\t.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }\n+\n+\t. = ALIGN(8);\n+\t.data : {\n+\t\t*(.data*)\n+\t}\n+\n+\t. = ALIGN(8);\n+\n+\t. = .;\n+\n+\t. = ALIGN(8);\n+\t.u_boot_list : {\n+\t\tKEEP(*(SORT(.u_boot_list*)));\n+\t}\n+\n+\t. = ALIGN(8);\n+\n+\t.image_copy_end :\n+\t{\n+\t\t*(.__image_copy_end)\n+\t}\n+\n+\t. = ALIGN(8);\n+\n+\t.rel_dyn_start :\n+\t{\n+\t\t*(.__rel_dyn_start)\n+\t}\n+\n+\t.rela.dyn : {\n+\t\t*(.rela*)\n+\t}\n+\n+\t.rel_dyn_end :\n+\t{\n+\t\t*(.__rel_dyn_end)\n+\t}\n+\n+\t_end = .;\n+\n+\t. = ALIGN(8);\n+\n+\t.bss_start : {\n+\t\tKEEP(*(.__bss_start));\n+\t}\n+\n+\t.bss : {\n+\t\t*(.bss*)\n+\t\t . = ALIGN(8);\n+\t}\n+\n+\t.bss_end : {\n+\t\tKEEP(*(.__bss_end));\n+\t}\n+\n+\t/DISCARD/ : { *(.dynsym) }\n+\t/DISCARD/ : { *(.dynstr*) }\n+\t/DISCARD/ : { *(.dynamic*) }\n+\t/DISCARD/ : { *(.plt*) }\n+\t/DISCARD/ : { *(.interp*) }\n+\t/DISCARD/ : { *(.gnu*) }\n+}\ndiff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h\nnew file mode 100644\nindex 0000000..1193e76\n--- /dev/null\n+++ b/arch/arm/include/asm/armv8/mmu.h\n@@ -0,0 +1,111 @@\n+/*\n+ * (C) Copyright 2013\n+ * David Feng <fenghua@phytium.com.cn>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef _ASM_ARMV8_MMU_H_\n+#define _ASM_ARMV8_MMU_H_\n+\n+#ifdef __ASSEMBLY__\n+#define _AC(X, Y)\tX\n+#else\n+#define _AC(X, Y)\t(X##Y)\n+#endif\n+\n+#define UL(x)\t\t_AC(x, UL)\n+\n+/***************************************************************/\n+/*\n+ * The following definitions are related each other, shoud be\n+ * calculated specifically.\n+ */\n+#define VA_BITS\t\t\t(42)\t/* 42 bits virtual address */\n+\n+/* PAGE_SHIFT determines the page size */\n+#undef PAGE_SIZE\n+#define PAGE_SHIFT\t\t16\n+#define PAGE_SIZE\t\t(1 << PAGE_SHIFT)\n+#define PAGE_MASK\t\t(~(PAGE_SIZE-1))\n+\n+/*\n+ * section address mask and size definitions.\n+ */\n+#define SECTION_SHIFT\t\t29\n+#define SECTION_SIZE\t\t(UL(1) << SECTION_SHIFT)\n+#define SECTION_MASK\t\t(~(SECTION_SIZE-1))\n+/***************************************************************/\n+\n+/*\n+ * Memory types\n+ */\n+#define MT_DEVICE_NGNRNE\t0\n+#define MT_DEVICE_NGNRE\t\t1\n+#define MT_DEVICE_GRE\t\t2\n+#define MT_NORMAL_NC\t\t3\n+#define MT_NORMAL\t\t4\n+\n+#define MEMORY_ATTRIBUTES\t((0x00 << (MT_DEVICE_NGNRNE*8)) |\t\\\n+\t\t\t\t(0x04 << (MT_DEVICE_NGNRE*8)) |\t\t\\\n+\t\t\t\t(0x0c << (MT_DEVICE_GRE*8)) |\t\t\\\n+\t\t\t\t(0x44 << (MT_NORMAL_NC*8)) |\t\t\\\n+\t\t\t\t(UL(0xff) << (MT_NORMAL*8)))\n+\n+/*\n+ * Hardware page table definitions.\n+ *\n+ * Level 2 descriptor (PMD).\n+ */\n+#define PMD_TYPE_MASK\t\t(3 << 0)\n+#define PMD_TYPE_FAULT\t\t(0 << 0)\n+#define PMD_TYPE_TABLE\t\t(3 << 0)\n+#define PMD_TYPE_SECT\t\t(1 << 0)\n+\n+/*\n+ * Section\n+ */\n+#define PMD_SECT_S\t\t(3 << 8)\n+#define PMD_SECT_AF\t\t(1 << 10)\n+#define PMD_SECT_NG\t\t(1 << 11)\n+#define PMD_SECT_PXN\t\t(UL(1) << 53)\n+#define PMD_SECT_UXN\t\t(UL(1) << 54)\n+\n+/*\n+ * AttrIndx[2:0]\n+ */\n+#define PMD_ATTRINDX(t)\t\t((t) << 2)\n+#define PMD_ATTRINDX_MASK\t(7 << 2)\n+\n+/*\n+ * TCR flags.\n+ */\n+#define TCR_T0SZ(x)\t\t((64 - (x)) << 0)\n+#define TCR_IRGN_NC\t\t(0 << 8)\n+#define TCR_IRGN_WBWA\t\t(1 << 8)\n+#define TCR_IRGN_WT\t\t(2 << 8)\n+#define TCR_IRGN_WBNWA\t\t(3 << 8)\n+#define TCR_IRGN_MASK\t\t(3 << 8)\n+#define TCR_ORGN_NC\t\t(0 << 10)\n+#define TCR_ORGN_WBWA\t\t(1 << 10)\n+#define TCR_ORGN_WT\t\t(2 << 10)\n+#define TCR_ORGN_WBNWA\t\t(3 << 10)\n+#define TCR_ORGN_MASK\t\t(3 << 10)\n+#define TCR_SHARED_NON\t\t(0 << 12)\n+#define TCR_SHARED_OUTER\t(1 << 12)\n+#define TCR_SHARED_INNER\t(2 << 12)\n+#define TCR_TG0_4K\t\t(0 << 14)\n+#define TCR_TG0_64K\t\t(1 << 14)\n+#define TCR_TG0_16K\t\t(2 << 14)\n+#define TCR_EL1_IPS_BITS\t(UL(3) << 32)\t/* 42 bits physical address */\n+#define TCR_EL2_IPS_BITS\t(3 << 16)\t/* 42 bits physical address */\n+#define TCR_EL3_IPS_BITS\t(3 << 16)\t/* 42 bits physical address */\n+\n+/* PTWs cacheable, inner/outer WBWA and non-shareable */\n+#define TCR_FLAGS\t\t(TCR_TG0_64K |\t\t\\\n+\t\t\t\tTCR_SHARED_NON |\t\\\n+\t\t\t\tTCR_ORGN_WBWA |\t\t\\\n+\t\t\t\tTCR_IRGN_WBWA |\t\t\\\n+\t\t\t\tTCR_T0SZ(VA_BITS))\n+\n+#endif /* _ASM_ARMV8_MMU_H_ */\ndiff --git a/arch/arm/include/asm/byteorder.h b/arch/arm/include/asm/byteorder.h\nindex c3489f1..71a9966 100644\n--- a/arch/arm/include/asm/byteorder.h\n+++ b/arch/arm/include/asm/byteorder.h\n@@ -23,10 +23,22 @@\n # define __SWAB_64_THRU_32__\n #endif\n \n+#ifdef\tCONFIG_ARM64\n+\n+#ifdef __AARCH64EB__\n+#include <linux/byteorder/big_endian.h>\n+#else\n+#include <linux/byteorder/little_endian.h>\n+#endif\n+\n+#else\t/* CONFIG_ARM64 */\n+\n #ifdef __ARMEB__\n #include <linux/byteorder/big_endian.h>\n #else\n #include <linux/byteorder/little_endian.h>\n #endif\n \n+#endif\t/* CONFIG_ARM64 */\n+\n #endif\ndiff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h\nindex 6d60a4a..ddebbc8 100644\n--- a/arch/arm/include/asm/cache.h\n+++ b/arch/arm/include/asm/cache.h\n@@ -11,6 +11,8 @@\n \n #include <asm/system.h>\n \n+#ifndef CONFIG_ARM64\n+\n /*\n * Invalidate L2 Cache using co-proc instruction\n */\n@@ -28,6 +30,9 @@ void l2_cache_disable(void);\n void set_section_dcache(int section, enum dcache_option option);\n \n void dram_bank_mmu_setup(int bank);\n+\n+#endif\n+\n /*\n * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We\n * use that value for aligning DMA buffers unless the board config has specified\ndiff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h\nindex 99b703e..abf79e5 100644\n--- a/arch/arm/include/asm/config.h\n+++ b/arch/arm/include/asm/config.h\n@@ -9,4 +9,10 @@\n \n #define CONFIG_LMB\n #define CONFIG_SYS_BOOT_RAMDISK_HIGH\n+\n+#ifdef CONFIG_ARM64\n+#define CONFIG_PHYS_64BIT\n+#define CONFIG_STATIC_RELA\n+#endif\n+\n #endif\ndiff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h\nindex a0891cc..ac2b2bf 100644\n--- a/arch/arm/include/asm/gic.h\n+++ b/arch/arm/include/asm/gic.h\n@@ -1,19 +1,54 @@\n-#ifndef __GIC_V2_H__\n-#define __GIC_V2_H__\n+#ifndef __GIC_H__\n+#define __GIC_H__\n \n-/* register offsets for the ARM generic interrupt controller (GIC) */\n+/* Register offsets for the ARM generic interrupt controller (GIC) */\n \n #define GIC_DIST_OFFSET\t\t0x1000\n+#define GIC_CPU_OFFSET_A9\t0x0100\n+#define GIC_CPU_OFFSET_A15\t0x2000\n+\n+/* Distributor Registers */\n #define GICD_CTLR\t\t0x0000\n #define GICD_TYPER\t\t0x0004\n+#define GICD_IIDR\t\t0x0008\n+#define GICD_STATUSR\t\t0x0010\n+#define GICD_SETSPI_NSR\t\t0x0040\n+#define GICD_CLRSPI_NSR\t\t0x0048\n+#define GICD_SETSPI_SR\t\t0x0050\n+#define GICD_CLRSPI_SR\t\t0x0058\n+#define GICD_SEIR\t\t0x0068\n #define GICD_IGROUPRn\t\t0x0080\n-#define GICD_SGIR\t\t0x0F00\n+#define GICD_ISENABLERn\t\t0x0100\n+#define GICD_ICENABLERn\t\t0x0180\n+#define GICD_ISPENDRn\t\t0x0200\n+#define GICD_ICPENDRn\t\t0x0280\n+#define GICD_ISACTIVERn\t\t0x0300\n+#define GICD_ICACTIVERn\t\t0x0380\n+#define GICD_IPRIORITYRn\t0x0400\n+#define GICD_ITARGETSRn\t\t0x0800\n+#define GICD_ICFGR\t\t0x0c00\n+#define GICD_IGROUPMODRn\t0x0d00\n+#define GICD_NSACRn\t\t0x0e00\n+#define GICD_SGIR\t\t0x0f00\n+#define GICD_CPENDSGIRn\t\t0x0f10\n+#define GICD_SPENDSGIRn\t\t0x0f20\n+#define GICD_IROUTERn\t\t0x6000\n \n-#define GIC_CPU_OFFSET_A9\t0x0100\n-#define GIC_CPU_OFFSET_A15\t0x2000\n+/* Cpu Interface Memory Mapped Registers */\n #define GICC_CTLR\t\t0x0000\n #define GICC_PMR\t\t0x0004\n+#define GICC_BPR\t\t0x0008\n #define GICC_IAR\t\t0x000C\n #define GICC_EOIR\t\t0x0010\n+#define GICC_RPR\t\t0x0014\n+#define GICC_HPPIR\t\t0x0018\n+#define GICC_ABPR\t\t0x001c\n+#define GICC_AIAR\t\t0x0020\n+#define GICC_AEOIR\t\t0x0024\n+#define GICC_AHPPIR\t\t0x0028\n+#define GICC_APRn\t\t0x00d0\n+#define GICC_NSAPRn\t\t0x00e0\n+#define GICC_IIDR\t\t0x00fc\n+#define GICC_DIR\t\t0x1000\n \n-#endif\n+#endif /* __GIC_H__ */\ndiff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h\nindex e126436..60e8726 100644\n--- a/arch/arm/include/asm/global_data.h\n+++ b/arch/arm/include/asm/global_data.h\n@@ -47,6 +47,10 @@ struct arch_global_data {\n \n #include <asm-generic/global_data.h>\n \n-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm (\"r9\")\n+#ifdef CONFIG_ARM64\n+#define DECLARE_GLOBAL_DATA_PTR\t\tregister volatile gd_t *gd asm (\"x18\")\n+#else\n+#define DECLARE_GLOBAL_DATA_PTR\t\tregister volatile gd_t *gd asm (\"r9\")\n+#endif\n \n #endif /* __ASM_GBL_DATA_H */\ndiff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h\nindex 1fbc531..6a1f05a 100644\n--- a/arch/arm/include/asm/io.h\n+++ b/arch/arm/include/asm/io.h\n@@ -75,42 +75,45 @@ static inline phys_addr_t virt_to_phys(void * vaddr)\n #define __arch_putw(v,a)\t\t(*(volatile unsigned short *)(a) = (v))\n #define __arch_putl(v,a)\t\t(*(volatile unsigned int *)(a) = (v))\n \n-extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen)\n+extern inline void __raw_writesb(unsigned long addr, const void *data,\n+\t\t\t\t int bytelen)\n {\n \tuint8_t *buf = (uint8_t *)data;\n \twhile(bytelen--)\n \t\t__arch_putb(*buf++, addr);\n }\n \n-extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen)\n+extern inline void __raw_writesw(unsigned long addr, const void *data,\n+\t\t\t\t int wordlen)\n {\n \tuint16_t *buf = (uint16_t *)data;\n \twhile(wordlen--)\n \t\t__arch_putw(*buf++, addr);\n }\n \n-extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen)\n+extern inline void __raw_writesl(unsigned long addr, const void *data,\n+\t\t\t\t int longlen)\n {\n \tuint32_t *buf = (uint32_t *)data;\n \twhile(longlen--)\n \t\t__arch_putl(*buf++, addr);\n }\n \n-extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen)\n+extern inline void __raw_readsb(unsigned long addr, void *data, int bytelen)\n {\n \tuint8_t *buf = (uint8_t *)data;\n \twhile(bytelen--)\n \t\t*buf++ = __arch_getb(addr);\n }\n \n-extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen)\n+extern inline void __raw_readsw(unsigned long addr, void *data, int wordlen)\n {\n \tuint16_t *buf = (uint16_t *)data;\n \twhile(wordlen--)\n \t\t*buf++ = __arch_getw(addr);\n }\n \n-extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)\n+extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)\n {\n \tuint32_t *buf = (uint32_t *)data;\n \twhile(longlen--)\ndiff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h\nindex ff13f36..f77e4b8 100644\n--- a/arch/arm/include/asm/macro.h\n+++ b/arch/arm/include/asm/macro.h\n@@ -54,5 +54,58 @@\n \tbcs\t1b\n .endm\n \n+#ifdef CONFIG_ARM64\n+/*\n+ * Register aliases.\n+ */\n+lr\t.req\tx30\n+\n+/*\n+ * Branch according to exception level\n+ */\n+.macro\tswitch_el, xreg, el3_label, el2_label, el1_label\n+\tmrs\t\\xreg, CurrentEL\n+\tcmp\t\\xreg, 0xc\n+\tb.eq\t\\el3_label\n+\tcmp\t\\xreg, 0x8\n+\tb.eq\t\\el2_label\n+\tcmp\t\\xreg, 0x4\n+\tb.eq\t\\el1_label\n+.endm\n+\n+/*\n+ * Branch if current processor is a slave,\n+ * choose processor with all zero affinity value as the master.\n+ */\n+.macro\tbranch_if_slave, xreg, slave_label\n+\tmrs\t\\xreg, mpidr_el1\n+\ttst\t\\xreg, #0xff\t\t/* Test Affinity 0 */\n+\tb.ne\t\\slave_label\n+\tlsr\t\\xreg, \\xreg, #8\n+\ttst\t\\xreg, #0xff\t\t/* Test Affinity 1 */\n+\tb.ne\t\\slave_label\n+\tlsr\t\\xreg, \\xreg, #8\n+\ttst\t\\xreg, #0xff\t\t/* Test Affinity 2 */\n+\tb.ne\t\\slave_label\n+\tlsr\t\\xreg, \\xreg, #16\n+\ttst\t\\xreg, #0xff\t\t/* Test Affinity 3 */\n+\tb.ne\t\\slave_label\n+.endm\n+\n+/*\n+ * Branch if current processor is a master,\n+ * choose processor with all zero affinity value as the master.\n+ */\n+.macro\tbranch_if_master, xreg1, xreg2, master_label\n+\tmrs\t\\xreg1, mpidr_el1\n+\tlsr\t\\xreg2, \\xreg1, #32\n+\tlsl\t\\xreg1, \\xreg1, #40\n+\tlsr\t\\xreg1, \\xreg1, #40\n+\torr\t\\xreg1, \\xreg1, \\xreg2\n+\tcbz\t\\xreg1, \\master_label\n+.endm\n+\n+#endif /* CONFIG_ARM64 */\n+\n #endif /* __ASSEMBLY__ */\n #endif /* __ASM_ARM_MACRO_H__ */\ndiff --git a/arch/arm/include/asm/posix_types.h b/arch/arm/include/asm/posix_types.h\nindex c412486..9ba9add 100644\n--- a/arch/arm/include/asm/posix_types.h\n+++ b/arch/arm/include/asm/posix_types.h\n@@ -13,6 +13,8 @@\n #ifndef __ARCH_ARM_POSIX_TYPES_H\n #define __ARCH_ARM_POSIX_TYPES_H\n \n+#include <config.h>\n+\n /*\n * This file is generally used by user-level software, so you need to\n * be a little careful about namespace pollution etc. Also, we cannot\n@@ -28,9 +30,17 @@ typedef int\t\t\t__kernel_pid_t;\n typedef unsigned short\t\t__kernel_ipc_pid_t;\n typedef unsigned short\t\t__kernel_uid_t;\n typedef unsigned short\t\t__kernel_gid_t;\n+\n+#ifdef\tCONFIG_ARM64\n+typedef unsigned long\t\t__kernel_size_t;\n+typedef long\t\t\t__kernel_ssize_t;\n+typedef long\t\t\t__kernel_ptrdiff_t;\n+#else\t/* CONFIG_ARM64 */\n typedef unsigned int\t\t__kernel_size_t;\n typedef int\t\t\t__kernel_ssize_t;\n typedef int\t\t\t__kernel_ptrdiff_t;\n+#endif\t/* CONFIG_ARM64 */\n+\n typedef long\t\t\t__kernel_time_t;\n typedef long\t\t\t__kernel_suseconds_t;\n typedef long\t\t\t__kernel_clock_t;\ndiff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h\nindex a060ee6..21aef58 100644\n--- a/arch/arm/include/asm/proc-armv/ptrace.h\n+++ b/arch/arm/include/asm/proc-armv/ptrace.h\n@@ -10,6 +10,25 @@\n #ifndef __ASM_PROC_PTRACE_H\n #define __ASM_PROC_PTRACE_H\n \n+#ifdef CONFIG_ARM64\n+\n+#define PCMASK\t\t0\n+\n+#ifndef __ASSEMBLY__\n+\n+/*\n+ * This struct defines the way the registers are stored\n+ * on the stack during an exception.\n+ */\n+struct pt_regs {\n+\tunsigned long elr;\n+\tunsigned long regs[31];\n+};\n+\n+#endif\t/* __ASSEMBLY__ */\n+\n+#else\t/* CONFIG_ARM64 */\n+\n #define USR26_MODE\t0x00\n #define FIQ26_MODE\t0x01\n #define IRQ26_MODE\t0x02\n@@ -104,4 +123,6 @@ static inline int valid_user_regs(struct pt_regs *regs)\n \n #endif\t/* __ASSEMBLY__ */\n \n+#endif\t/* CONFIG_ARM64 */\n+\n #endif\ndiff --git a/arch/arm/include/asm/proc-armv/system.h b/arch/arm/include/asm/proc-armv/system.h\nindex cda8976..693d1f4 100644\n--- a/arch/arm/include/asm/proc-armv/system.h\n+++ b/arch/arm/include/asm/proc-armv/system.h\n@@ -13,6 +13,60 @@\n /*\n * Save the current interrupt enable state & disable IRQs\n */\n+#ifdef CONFIG_ARM64\n+\n+/*\n+ * Save the current interrupt enable state\n+ * and disable IRQs/FIQs\n+ */\n+#define local_irq_save(flags)\t\t\t\t\t\\\n+\t({\t\t\t\t\t\t\t\\\n+\tasm volatile(\t\t\t\t\t\t\\\n+\t\"mrs\t%0, daif\"\t\t\t\t\t\\\n+\t\"msr\tdaifset, #3\"\t\t\t\t\t\\\n+\t: \"=r\" (flags)\t\t\t\t\t\t\\\n+\t:\t\t\t\t\t\t\t\\\n+\t: \"memory\");\t\t\t\t\t\t\\\n+\t})\n+\n+/*\n+ * restore saved IRQ & FIQ state\n+ */\n+#define local_irq_restore(flags)\t\t\t\t\\\n+\t({\t\t\t\t\t\t\t\\\n+\tasm volatile(\t\t\t\t\t\t\\\n+\t\"msr\tdaif, %0\"\t\t\t\t\t\\\n+\t:\t\t\t\t\t\t\t\\\n+\t: \"r\" (flags)\t\t\t\t\t\t\\\n+\t: \"memory\");\t\t\t\t\t\t\\\n+\t})\n+\n+/*\n+ * Enable IRQs/FIQs\n+ */\n+#define local_irq_enable()\t\t\t\t\t\\\n+\t({\t\t\t\t\t\t\t\\\n+\tasm volatile(\t\t\t\t\t\t\\\n+\t\"msr\tdaifclr, #3\"\t\t\t\t\t\\\n+\t:\t\t\t\t\t\t\t\\\n+\t:\t\t\t\t\t\t\t\\\n+\t: \"memory\");\t\t\t\t\t\t\\\n+\t})\n+\n+/*\n+ * Disable IRQs/FIQs\n+ */\n+#define local_irq_disable()\t\t\t\t\t\\\n+\t({\t\t\t\t\t\t\t\\\n+\tasm volatile(\t\t\t\t\t\t\\\n+\t\"msr\tdaifset, #3\"\t\t\t\t\t\\\n+\t:\t\t\t\t\t\t\t\\\n+\t:\t\t\t\t\t\t\t\\\n+\t: \"memory\");\t\t\t\t\t\t\\\n+\t})\n+\n+#else\t/* CONFIG_ARM64 */\n+\n #define local_irq_save(x)\t\t\t\t\t\\\n \t({\t\t\t\t\t\t\t\\\n \t\tunsigned long temp;\t\t\t\t\\\n@@ -107,7 +161,10 @@\n \t: \"r\" (x)\t\t\t\t\t\t\\\n \t: \"memory\")\n \n-#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)\n+#endif\t/* CONFIG_ARM64 */\n+\n+#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \\\n+\tdefined(CONFIG_ARM64)\n /*\n * On the StrongARM, \"swp\" is terminally broken since it bypasses the\n * cache totally. This means that the cache becomes inconsistent, and,\ndiff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h\nindex 760345f..4178f8c 100644\n--- a/arch/arm/include/asm/system.h\n+++ b/arch/arm/include/asm/system.h\n@@ -1,6 +1,86 @@\n #ifndef __ASM_ARM_SYSTEM_H\n #define __ASM_ARM_SYSTEM_H\n \n+#ifdef CONFIG_ARM64\n+\n+/*\n+ * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions\n+ */\n+#define CR_M\t\t(1 << 0)\t/* MMU enable\t\t\t*/\n+#define CR_A\t\t(1 << 1)\t/* Alignment abort enable\t*/\n+#define CR_C\t\t(1 << 2)\t/* Dcache enable\t\t*/\n+#define CR_SA\t\t(1 << 3)\t/* Stack Alignment Check Enable\t*/\n+#define CR_I\t\t(1 << 12)\t/* Icache enable\t\t*/\n+#define CR_WXN\t\t(1 << 19)\t/* Write Permision Imply XN\t*/\n+#define CR_EE\t\t(1 << 25)\t/* Exception (Big) Endian\t*/\n+\n+#define PGTABLE_SIZE\t(0x10000)\n+\n+#ifndef __ASSEMBLY__\n+\n+#define isb()\t\t\t\t\\\n+\t({asm volatile(\t\t\t\\\n+\t\"isb\" : : : \"memory\");\t\t\\\n+\t})\n+\n+#define wfi()\t\t\t\t\\\n+\t({asm volatile(\t\t\t\\\n+\t\"wfi\" : : : \"memory\");\t\t\\\n+\t})\n+\n+static inline unsigned int current_el(void)\n+{\n+\tunsigned int el;\n+\tasm volatile(\"mrs %0, CurrentEL\" : \"=r\" (el) : : \"cc\");\n+\treturn el >> 2;\n+}\n+\n+static inline unsigned int get_sctlr(void)\n+{\n+\tunsigned int el, val;\n+\n+\tel = current_el();\n+\tif (el == 1)\n+\t\tasm volatile(\"mrs %0, sctlr_el1\" : \"=r\" (val) : : \"cc\");\n+\telse if (el == 2)\n+\t\tasm volatile(\"mrs %0, sctlr_el2\" : \"=r\" (val) : : \"cc\");\n+\telse\n+\t\tasm volatile(\"mrs %0, sctlr_el3\" : \"=r\" (val) : : \"cc\");\n+\n+\treturn val;\n+}\n+\n+static inline void set_sctlr(unsigned int val)\n+{\n+\tunsigned int el;\n+\n+\tel = current_el();\n+\tif (el == 1)\n+\t\tasm volatile(\"msr sctlr_el1, %0\" : : \"r\" (val) : \"cc\");\n+\telse if (el == 2)\n+\t\tasm volatile(\"msr sctlr_el2, %0\" : : \"r\" (val) : \"cc\");\n+\telse\n+\t\tasm volatile(\"msr sctlr_el3, %0\" : : \"r\" (val) : \"cc\");\n+\n+\tasm volatile(\"isb\");\n+}\n+\n+void __asm_flush_dcache_all(void);\n+void __asm_flush_dcache_range(u64 start, u64 end);\n+void __asm_invalidate_tlb_all(void);\n+void __asm_invalidate_icache_all(void);\n+\n+void armv8_switch_to_el2(void);\n+void armv8_switch_to_el1(void);\n+void gic_init(void);\n+void gic_send_sgi(unsigned long sgino);\n+void wait_for_wakeup(void);\n+void smp_kick_all_cpus(void);\n+\n+#endif\t/* __ASSEMBLY__ */\n+\n+#else /* CONFIG_ARM64 */\n+\n #ifdef __KERNEL__\n \n #define CPU_ARCH_UNKNOWN\t0\n@@ -45,6 +125,8 @@\n #define CR_AFE\t(1 << 29)\t/* Access flag enable\t\t\t*/\n #define CR_TE\t(1 << 30)\t/* Thumb exception enable\t\t*/\n \n+#define PGTABLE_SIZE\t\t(4096 * 4)\n+\n /*\n * This is used to ensure the compiler did actually allocate the register we\n * asked it for some inline assembly sequences. Apparently we can't trust\n@@ -132,4 +214,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop);\n \n #endif /* __KERNEL__ */\n \n+#endif /* CONFIG_ARM64 */\n+\n #endif\ndiff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h\nindex 71dc049..2326420 100644\n--- a/arch/arm/include/asm/types.h\n+++ b/arch/arm/include/asm/types.h\n@@ -39,7 +39,11 @@ typedef unsigned int u32;\n typedef signed long long s64;\n typedef unsigned long long u64;\n \n+#ifdef\tCONFIG_ARM64\n+#define BITS_PER_LONG 64\n+#else\t/* CONFIG_ARM64 */\n #define BITS_PER_LONG 32\n+#endif\t/* CONFIG_ARM64 */\n \n /* Dma addresses are 32-bits wide. */\n \ndiff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h\nindex 2b5fce8..cb81232 100644\n--- a/arch/arm/include/asm/u-boot.h\n+++ b/arch/arm/include/asm/u-boot.h\n@@ -44,6 +44,10 @@ typedef struct bd_info {\n #endif /* !CONFIG_SYS_GENERIC_BOARD */\n \n /* For image.h:image_check_target_arch() */\n+#ifndef CONFIG_ARM64\n #define IH_ARCH_DEFAULT IH_ARCH_ARM\n+#else\n+#define IH_ARCH_DEFAULT IH_ARCH_ARM64\n+#endif\n \n #endif\t/* _U_BOOT_H_ */\ndiff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h\nindex 44593a8..0a228fb 100644\n--- a/arch/arm/include/asm/unaligned.h\n+++ b/arch/arm/include/asm/unaligned.h\n@@ -8,7 +8,7 @@\n /*\n * Select endianness\n */\n-#ifndef __ARMEB__\n+#if __BYTE_ORDER == __LITTLE_ENDIAN\n #define get_unaligned\t__get_unaligned_le\n #define put_unaligned\t__put_unaligned_le\n #else\ndiff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile\nindex 679f19a..321997c 100644\n--- a/arch/arm/lib/Makefile\n+++ b/arch/arm/lib/Makefile\n@@ -17,14 +17,22 @@ lib-y\t+= _umodsi3.o\n lib-y\t+= div0.o\n endif\n \n-obj-y += crt0.o\n+ifdef CONFIG_ARM64\n+obj-y\t+= crt0_64.o\n+else\n+obj-y\t+= crt0.o\n+endif\n \n ifndef CONFIG_SPL_BUILD\n-obj-y += relocate.o\n+ifdef CONFIG_ARM64\n+obj-y\t+= relocate_64.o\n+else\n+obj-y\t+= relocate.o\n+endif\n ifndef CONFIG_SYS_GENERIC_BOARD\n obj-y\t+= board.o\n endif\n-obj-y += sections.o\n+obj-y\t+= sections.o\n \n obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o\n obj-$(CONFIG_CMD_BOOTM) += bootm.o\n@@ -35,11 +43,17 @@ else\n obj-$(CONFIG_SPL_FRAMEWORK) += spl.o\n endif\n \n+ifdef CONFIG_ARM64\n+obj-y\t+= interrupts_64.o\n+else\n obj-y\t+= interrupts.o\n+endif\n obj-y\t+= reset.o\n \n obj-y\t+= cache.o\n+ifndef CONFIG_ARM64\n obj-y\t+= cache-cp15.o\n+endif\n \n # For EABI conformant tool chains, provide eabi_compat()\n ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))\ndiff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c\nindex 34f50b0..c4904b4 100644\n--- a/arch/arm/lib/board.c\n+++ b/arch/arm/lib/board.c\n@@ -344,7 +344,7 @@ void board_init_f(ulong bootflag)\n \n #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))\n \t/* reserve TLB table */\n-\tgd->arch.tlb_size = 4096 * 4;\n+\tgd->arch.tlb_size = PGTABLE_SIZE;\n \taddr -= gd->arch.tlb_size;\n \n \t/* round down to next 64 kB limit */\n@@ -419,6 +419,7 @@ void board_init_f(ulong bootflag)\n \t}\n #endif\n \n+#ifndef CONFIG_ARM64\n \t/* setup stackpointer for exeptions */\n \tgd->irq_sp = addr_sp;\n #ifdef CONFIG_USE_IRQ\n@@ -431,6 +432,10 @@ void board_init_f(ulong bootflag)\n \n \t/* 8-byte alignment for ABI compliance */\n \taddr_sp &= ~0x07;\n+#else\t/* CONFIG_ARM64 */\n+\t/* 16-byte alignment for ABI compliance */\n+\taddr_sp &= ~0x0f;\n+#endif\t/* CONFIG_ARM64 */\n #else\n \taddr_sp += 128;\t/* leave 32 words for abort-stack */\n \tgd->irq_sp = addr_sp;\ndiff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c\nindex f476a89..77f1a5c 100644\n--- a/arch/arm/lib/bootm.c\n+++ b/arch/arm/lib/bootm.c\n@@ -196,6 +196,14 @@ static void do_nonsec_virt_switch(void)\n \t\tdebug(\"entered non-secure state\\n\");\n #endif\n #endif\n+\n+#ifdef CONFIG_ARM64\n+\tsmp_kick_all_cpus();\n+\tarmv8_switch_to_el2();\n+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1\n+\tarmv8_switch_to_el1();\n+#endif\n+#endif\n }\n \n /* Subcommand: PREP */\n@@ -240,6 +248,21 @@ static void boot_prep_linux(bootm_headers_t *images)\n /* Subcommand: GO */\n static void boot_jump_linux(bootm_headers_t *images, int flag)\n {\n+#ifdef CONFIG_ARM64\n+\tvoid (*kernel_entry)(void *fdt_addr);\n+\tint fake = (flag & BOOTM_STATE_OS_FAKE_GO);\n+\n+\tkernel_entry = (void (*)(void *fdt_addr))images->ep;\n+\n+\tdebug(\"## Transferring control to Linux (at address %lx)...\\n\",\n+\t\t(ulong) kernel_entry);\n+\tbootstage_mark(BOOTSTAGE_ID_RUN_OS);\n+\n+\tannounce_and_cleanup(fake);\n+\n+\tif (!fake)\n+\t\tkernel_entry(images->ft_addr);\n+#else\n \tunsigned long machid = gd->bd->bi_arch_number;\n \tchar *s;\n \tvoid (*kernel_entry)(int zero, int arch, uint params);\n@@ -266,6 +289,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)\n \n \tif (!fake)\n \t\tkernel_entry(0, machid, r2);\n+#endif\n }\n \n /* Main Entry point for arm bootm implementation\ndiff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S\nnew file mode 100644\nindex 0000000..7756396\n--- /dev/null\n+++ b/arch/arm/lib/crt0_64.S\n@@ -0,0 +1,113 @@\n+/*\n+ * crt0 - C-runtime startup Code for AArch64 U-Boot\n+ *\n+ * (C) Copyright 2013\n+ * David Feng <fenghua@phytium.com.cn>\n+ *\n+ * (C) Copyright 2012\n+ * Albert ARIBAUD <albert.u.boot@aribaud.net>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <config.h>\n+#include <asm-offsets.h>\n+#include <asm/macro.h>\n+#include <linux/linkage.h>\n+\n+/*\n+ * This file handles the target-independent stages of the U-Boot\n+ * start-up where a C runtime environment is needed. Its entry point\n+ * is _main and is branched into from the target's start.S file.\n+ *\n+ * _main execution sequence is:\n+ *\n+ * 1. Set up initial environment for calling board_init_f().\n+ * This environment only provides a stack and a place to store\n+ * the GD ('global data') structure, both located in some readily\n+ * available RAM (SRAM, locked cache...). In this context, VARIABLE\n+ * global data, initialized or not (BSS), are UNAVAILABLE; only\n+ * CONSTANT initialized data are available.\n+ *\n+ * 2. Call board_init_f(). This function prepares the hardware for\n+ * execution from system RAM (DRAM, DDR...) As system RAM may not\n+ * be available yet, , board_init_f() must use the current GD to\n+ * store any data which must be passed on to later stages. These\n+ * data include the relocation destination, the future stack, and\n+ * the future GD location.\n+ *\n+ * (the following applies only to non-SPL builds)\n+ *\n+ * 3. Set up intermediate environment where the stack and GD are the\n+ * ones allocated by board_init_f() in system RAM, but BSS and\n+ * initialized non-const data are still not available.\n+ *\n+ * 4. Call relocate_code(). This function relocates U-Boot from its\n+ * current location into the relocation destination computed by\n+ * board_init_f().\n+ *\n+ * 5. Set up final environment for calling board_init_r(). This\n+ * environment has BSS (initialized to 0), initialized non-const\n+ * data (initialized to their intended value), and stack in system\n+ * RAM. GD has retained values set by board_init_f(). Some CPUs\n+ * have some work left to do at this point regarding memory, so\n+ * call c_runtime_cpu_setup.\n+ *\n+ * 6. Branch to board_init_r().\n+ */\n+\n+ENTRY(_main)\n+\n+/*\n+ * Set up initial C runtime environment and call board_init_f(0).\n+ */\n+\tldr\tx0, =(CONFIG_SYS_INIT_SP_ADDR)\n+\tsub\tx0, x0, #GD_SIZE\t/* allocate one GD above SP */\n+\tbic\tsp, x0, #0xf\t/* 16-byte alignment for ABI compliance */\n+\tmov\tx18, sp\t\t\t/* GD is above SP */\n+\tmov\tx0, #0\n+\tbl\tboard_init_f\n+\n+/*\n+ * Set up intermediate environment (new sp and gd) and call\n+ * relocate_code(addr_moni). Trick here is that we'll return\n+ * 'here' but relocated.\n+ */\n+\tldr\tx0, [x18, #GD_START_ADDR_SP]\t/* x0 <- gd->start_addr_sp */\n+\tbic\tsp, x0, #0xf\t/* 16-byte alignment for ABI compliance */\n+\tldr\tx18, [x18, #GD_BD]\t\t/* x18 <- gd->bd */\n+\tsub\tx18, x18, #GD_SIZE\t\t/* new GD is below bd */\n+\n+\tadr\tlr, relocation_return\n+\tldr\tx9, [x18, #GD_RELOC_OFF]\t/* x9 <- gd->reloc_off */\n+\tadd\tlr, lr, x9\t/* new return address after relocation */\n+\tldr\tx0, [x18, #GD_RELOCADDR]\t/* x0 <- gd->relocaddr */\n+\tb\trelocate_code\n+\n+relocation_return:\n+\n+/*\n+ * Set up final (full) environment\n+ */\n+\tbl\tc_runtime_cpu_setup\t\t/* still call old routine */\n+\n+/*\n+ * Clear BSS section\n+ */\n+\tldr\tx0, =__bss_start\t\t/* this is auto-relocated! */\n+\tldr\tx1, =__bss_end\t\t\t/* this is auto-relocated! */\n+\tmov\tx2, #0\n+clear_loop:\n+\tstr\tx2, [x0]\n+\tadd\tx0, x0, #8\n+\tcmp\tx0, x1\n+\tb.lo\tclear_loop\n+\n+\t/* call board_init_r(gd_t *id, ulong dest_addr) */\n+\tmov\tx0, x18\t\t\t\t/* gd_t */\n+\tldr\tx1, [x18, #GD_RELOCADDR]\t/* dest_addr */\n+\tb\tboard_init_r\t\t\t/* PC relative jump */\n+\n+\t/* NOTREACHED - board_init_r() does not return */\n+\n+ENDPROC(_main)\ndiff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c\nnew file mode 100644\nindex 0000000..b476722\n--- /dev/null\n+++ b/arch/arm/lib/interrupts_64.c\n@@ -0,0 +1,120 @@\n+/*\n+ * (C) Copyright 2013\n+ * David Feng <fenghua@phytium.com.cn>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <linux/compiler.h>\n+\n+\n+int interrupt_init(void)\n+{\n+\treturn 0;\n+}\n+\n+void enable_interrupts(void)\n+{\n+\treturn;\n+}\n+\n+int disable_interrupts(void)\n+{\n+\treturn 0;\n+}\n+\n+void show_regs(struct pt_regs *regs)\n+{\n+\tint i;\n+\n+\tprintf(\"ELR: %lx\\n\", regs->elr);\n+\tprintf(\"LR: %lx\\n\", regs->regs[30]);\n+\tfor (i = 0; i < 29; i += 2)\n+\t\tprintf(\"x%-2d: %016lx x%-2d: %016lx\\n\",\n+\t\t i, regs->regs[i], i+1, regs->regs[i+1]);\n+\tprintf(\"\\n\");\n+}\n+\n+/*\n+ * do_bad_sync handles the impossible case in the Synchronous Abort vector.\n+ */\n+void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr)\n+{\n+\tprintf(\"Bad mode in \\\"Synchronous Abort\\\" handler, esr 0x%08x\\n\", esr);\n+\tshow_regs(pt_regs);\n+\tpanic(\"Resetting CPU ...\\n\");\n+}\n+\n+/*\n+ * do_bad_irq handles the impossible case in the Irq vector.\n+ */\n+void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr)\n+{\n+\tprintf(\"Bad mode in \\\"Irq\\\" handler, esr 0x%08x\\n\", esr);\n+\tshow_regs(pt_regs);\n+\tpanic(\"Resetting CPU ...\\n\");\n+}\n+\n+/*\n+ * do_bad_fiq handles the impossible case in the Fiq vector.\n+ */\n+void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr)\n+{\n+\tprintf(\"Bad mode in \\\"Fiq\\\" handler, esr 0x%08x\\n\", esr);\n+\tshow_regs(pt_regs);\n+\tpanic(\"Resetting CPU ...\\n\");\n+}\n+\n+/*\n+ * do_bad_error handles the impossible case in the Error vector.\n+ */\n+void do_bad_error(struct pt_regs *pt_regs, unsigned int esr)\n+{\n+\tprintf(\"Bad mode in \\\"Error\\\" handler, esr 0x%08x\\n\", esr);\n+\tshow_regs(pt_regs);\n+\tpanic(\"Resetting CPU ...\\n\");\n+}\n+\n+/*\n+ * do_sync handles the Synchronous Abort exception.\n+ */\n+void do_sync(struct pt_regs *pt_regs, unsigned int esr)\n+{\n+\tprintf(\"\\\"Synchronous Abort\\\" handler, esr 0x%08x\\n\", esr);\n+\tshow_regs(pt_regs);\n+\tpanic(\"Resetting CPU ...\\n\");\n+}\n+\n+/*\n+ * do_irq handles the Irq exception.\n+ */\n+void do_irq(struct pt_regs *pt_regs, unsigned int esr)\n+{\n+\tprintf(\"\\\"Irq\\\" handler, esr 0x%08x\\n\", esr);\n+\tshow_regs(pt_regs);\n+\tpanic(\"Resetting CPU ...\\n\");\n+}\n+\n+/*\n+ * do_fiq handles the Fiq exception.\n+ */\n+void do_fiq(struct pt_regs *pt_regs, unsigned int esr)\n+{\n+\tprintf(\"\\\"Fiq\\\" handler, esr 0x%08x\\n\", esr);\n+\tshow_regs(pt_regs);\n+\tpanic(\"Resetting CPU ...\\n\");\n+}\n+\n+/*\n+ * do_error handles the Error exception.\n+ * Errors are more likely to be processor specific,\n+ * it is defined with weak attribute and can be redefined\n+ * in processor specific code.\n+ */\n+void __weak do_error(struct pt_regs *pt_regs, unsigned int esr)\n+{\n+\tprintf(\"\\\"Error\\\" handler, esr 0x%08x\\n\", esr);\n+\tshow_regs(pt_regs);\n+\tpanic(\"Resetting CPU ...\\n\");\n+}\ndiff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S\nnew file mode 100644\nindex 0000000..7fba9e2\n--- /dev/null\n+++ b/arch/arm/lib/relocate_64.S\n@@ -0,0 +1,58 @@\n+/*\n+ * relocate - common relocation function for AArch64 U-Boot\n+ *\n+ * (C) Copyright 2013\n+ * Albert ARIBAUD <albert.u.boot@aribaud.net>\n+ * David Feng <fenghua@phytium.com.cn>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <asm-offsets.h>\n+#include <config.h>\n+#include <linux/linkage.h>\n+\n+/*\n+ * void relocate_code (addr_moni)\n+ *\n+ * This function relocates the monitor code.\n+ * x0 holds the destination address.\n+ */\n+ENTRY(relocate_code)\n+\t/*\n+\t * Copy u-boot from flash to RAM\n+\t */\n+\tldr\tx1, =__image_copy_start\t/* x1 <- SRC &__image_copy_start */\n+\tsubs\tx9, x0, x1\t\t/* x9 <- relocation offset */\n+\tb.eq\trelocate_done\t\t/* skip relocation */\n+\tldr\tx2, =__image_copy_end\t/* x2 <- SRC &__image_copy_end */\n+\n+copy_loop:\n+\tldp\tx10, x11, [x1], #16\t/* copy from source address [x1] */\n+\tstp\tx10, x11, [x0], #16\t/* copy to target address [x0] */\n+\tcmp\tx1, x2\t\t\t/* until source end address [x2] */\n+\tb.lo\tcopy_loop\n+\n+\t/*\n+\t * Fix .rela.dyn relocations\n+\t */\n+\tldr\tx2, =__rel_dyn_start\t/* x2 <- SRC &__rel_dyn_start */\n+\tldr\tx3, =__rel_dyn_end\t/* x3 <- SRC &__rel_dyn_end */\n+fixloop:\n+\tldp\tx0, x1, [x2], #16\t/* (x0,x1) <- (SRC location, fixup) */\n+\tldr\tx4, [x2], #8\t\t/* x4 <- addend */\n+\tand\tx1, x1, #0xffffffff\n+\tcmp\tx1, #1027\t\t/* relative fixup? */\n+\tbne\tfixnext\n+\n+\t/* relative fix: store addend plus offset at dest location */\n+\tadd\tx0, x0, x9\n+\tadd\tx4, x4, x9\n+\tstr\tx4, [x0]\n+fixnext:\n+\tcmp\tx2, x3\n+\tb.lo\tfixloop\n+\n+relocate_done:\n+\tret\n+ENDPROC(relocate_code)\ndiff --git a/common/image.c b/common/image.c\nindex b0ae58f..4145354 100644\n--- a/common/image.c\n+++ b/common/image.c\n@@ -81,6 +81,7 @@ static const table_entry_t uimage_arch[] = {\n \t{\tIH_ARCH_NDS32,\t\t\"nds32\",\t\"NDS32\",\t},\n \t{\tIH_ARCH_OPENRISC,\t\"or1k\",\t\t\"OpenRISC 1000\",},\n \t{\tIH_ARCH_SANDBOX,\t\"sandbox\",\t\"Sandbox\",\t},\n+\t{\tIH_ARCH_ARM64,\t\t\"arm64\",\t\"AArch64\",\t},\n \t{\t-1,\t\t\t\"\",\t\t\"\",\t\t},\n };\n \ndiff --git a/doc/README.arm64 b/doc/README.arm64\nnew file mode 100644\nindex 0000000..75586db\n--- /dev/null\n+++ b/doc/README.arm64\n@@ -0,0 +1,46 @@\n+U-boot for arm64\n+\n+Summary\n+=======\n+No hardware platform of arm64 is available now. The u-boot is\n+simulated on Foundation Model and Fast Model for ARMv8.\n+\n+Notes\n+=====\n+\n+1. Currenly, u-boot run at the highest exception level processor\n+ supported and jump to EL2 or optionally EL1 before enter OS.\n+\n+2. U-boot for arm64 is compiled with AArch64-gcc. AArch64-gcc\n+ use rela relocation format, a tool(tools/relocate-rela) by Scott Wood\n+ is used to encode the initial addend of rela to u-boot.bin. After running,\n+ the u-boot will be relocated to destination again.\n+\n+3. Fdt should be placed at a 2-megabyte boundary and within the first 512\n+ megabytes from the start of the kernel image. So, fdt_high should be\n+ defined specially.\n+ Please reference linux/Documentation/arm64/booting.txt for detail.\n+\n+4. Spin-table is used to wake up secondary processors. One location\n+ (or per processor location) is defined to hold the kernel entry point\n+ for secondary processors. It must be ensured that the location is\n+ accessible and zero immediately after secondary processor\n+ enter slave_cpu branch execution in start.S. The location address\n+ is encoded in cpu node of DTS. Linux kernel store the entry point\n+ of secondary processors to it and send event to wakeup secondary\n+ processors.\n+ Please reference linux/Documentation/arm64/booting.txt for detail.\n+\n+5. Generic board is supported.\n+\n+6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and\n+ aarch32 specific codes.\n+\n+Contributor\n+===========\n+ Tom Rini <trini@ti.com>\n+ Scott Wood <scottwood@freescale.com>\n+ York Sun <yorksun@freescale.com>\n+ Simon Glass <sjg@chromium.org>\n+ Sharma Bhupesh <bhupesh.sharma@freescale.com>\n+ Rob Herring <robherring2@gmail.com>\ndiff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c\nindex 8fb1765..fc5d7ef 100644\n--- a/examples/standalone/stubs.c\n+++ b/examples/standalone/stubs.c\n@@ -39,6 +39,20 @@ gd_t *global_data;\n \"\tbctr\\n\"\t\t\t\t\\\n \t: : \"i\"(offsetof(gd_t, jt)), \"i\"(XF_ ## x * sizeof(void *)) : \"r11\");\n #elif defined(CONFIG_ARM)\n+#ifdef CONFIG_ARM64\n+/*\n+ * x18 holds the pointer to the global_data, x9 is a call-clobbered\n+ * register\n+ */\n+#define EXPORT_FUNC(x) \\\n+\tasm volatile (\t\t\t\\\n+\"\t.globl \" #x \"\\n\"\t\t\\\n+#x \":\\n\"\t\t\t\t\\\n+\"\tldr\tx9, [x18, %0]\\n\"\t\t\\\n+\"\tldr\tx9, [x9, %1]\\n\"\t\t\\\n+\"\tbr\tx9\\n\"\t\t\\\n+\t: : \"i\"(offsetof(gd_t, jt)), \"i\"(XF_ ## x * sizeof(void *)) : \"x9\");\n+#else\n /*\n * r8 holds the pointer to the global_data, ip is a call-clobbered\n * register\n@@ -50,6 +64,7 @@ gd_t *global_data;\n \"\tldr\tip, [r8, %0]\\n\"\t\t\\\n \"\tldr\tpc, [ip, %1]\\n\"\t\t\\\n \t: : \"i\"(offsetof(gd_t, jt)), \"i\"(XF_ ## x * sizeof(void *)) : \"ip\");\n+#endif\n #elif defined(CONFIG_MIPS)\n /*\n * k0 ($26) holds the pointer to the global_data; t9 ($25) is a call-\ndiff --git a/include/image.h b/include/image.h\nindex ee6eb8d..7de2bb2 100644\n--- a/include/image.h\n+++ b/include/image.h\n@@ -156,6 +156,7 @@ struct lmb;\n #define IH_ARCH_SANDBOX\t\t19\t/* Sandbox architecture (test only) */\n #define IH_ARCH_NDS32\t 20\t/* ANDES Technology - NDS32 */\n #define IH_ARCH_OPENRISC 21\t/* OpenRISC 1000 */\n+#define IH_ARCH_ARM64\t\t22\t/* ARM64\t*/\n \n /*\n * Image Types\n", "prefixes": [ "U-Boot", "v15", "07/10" ] }