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GET /api/patches/232/?format=api
{ "id": 232, "url": "http://patchwork.ozlabs.org/api/patches/232/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1221083587-8091-2-git-send-email-yanok@emcraft.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1221083587-8091-2-git-send-email-yanok@emcraft.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1221083587-8091-2-git-send-email-yanok@emcraft.com/", "date": "2008-09-10T21:53:06", "name": "powerpc: add support for PAGE_SIZEs greater than 4KB for", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "6c2ce61ca4141e2f7d5f80e46d0ca748caf64e82", "submitter": { "id": 25, "url": "http://patchwork.ozlabs.org/api/people/25/?format=api", "name": "Ilya Yanok", "email": "yanok@emcraft.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1221083587-8091-2-git-send-email-yanok@emcraft.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/232/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/232/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork=ozlabs.org@ozlabs.org>", "X-Original-To": [ "patchwork@ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Delivered-To": [ "patchwork@ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Received": [ "from ozlabs.org (localhost [127.0.0.1])\n\tby ozlabs.org (Postfix) with ESMTP id E0474DE899\n\tfor <patchwork@ozlabs.org>; Thu, 11 Sep 2008 07:54:25 +1000 (EST)", "from ocean.emcraft.com (ocean.emcraft.com [213.221.7.182])\n\t(using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits))\n\t(Client did not present a certificate)\n\tby ozlabs.org (Postfix) with ESMTPS id 66E77DE6C7\n\tfor <linuxppc-dev@ozlabs.org>; Thu, 11 Sep 2008 07:54:05 +1000 (EST)", "from [172.17.0.9] (helo=localhost.localdomain)\n\tby ocean.emcraft.com with esmtp (Exim 4.43)\n\tid 1KdXcs-0007Kn-7g; Thu, 11 Sep 2008 01:53:38 +0400" ], "From": "Ilya Yanok <yanok@emcraft.com>", "To": "linuxppc-dev@ozlabs.org", "Subject": "[PATCH] powerpc: add support for PAGE_SIZEs greater than 4KB for", "Date": "Thu, 11 Sep 2008 01:53:06 +0400", "Message-Id": "<1221083587-8091-2-git-send-email-yanok@emcraft.com>", "X-Mailer": "git-send-email 1.5.6.5", "In-Reply-To": "<1221083587-8091-1-git-send-email-yanok@emcraft.com>", "References": "<1221083587-8091-1-git-send-email-yanok@emcraft.com>", "X-Spam-Score": "-4.3 (----)", "X-Spam-Report": "Spam detection software,\n\trunning on the system \"ocean.emcraft.com\", has\n\tidentified this incoming email as possible spam. The original message\n\thas been attached to this so you can view it (if it isn't spam) or\n\tlabel similar future email. If you have any questions, see\n\tthe administrator of that system for details.\n\tContent preview: This patch adds support for page sizes bigger than\n\t4KB (16KB/64KB/256KB) on PPC 44x. Signed-off-by: Yuri Tikhonov\n\t<yur@emcraft.com> Signed-off-by: Ilya Yanok <yanok@emcraft.com> ---\n\tarch/powerpc/Kconfig | 23 +++++++++\n\tarch/powerpc/include/asm/highmem.h\n\t| 8 +++- arch/powerpc/include/asm/page.h | 26 +++++++++-\n\tarch/powerpc/include/asm/page_32.h | 4 ++\n\tarch/powerpc/include/asm/ppc_page_asm.h | 75\n\t+++++++++++++++++++++++++++++++\n\tarch/powerpc/include/asm/thread_info.h\n\t| 4 ++ arch/powerpc/kernel/head_44x.S | 21 +++++---\n\tarch/powerpc/kernel/head_booke.h | 7 ++-\n\tarch/powerpc/kernel/misc_32.S |\n\t13 +++--- arch/powerpc/mm/pgtable_32.c | 2 +- 10 files changed, 162\n\tinsertions(+), 21 deletions(-) create mode 100644\n\tarch/powerpc/include/asm/ppc_page_asm.h [...] \n\tContent analysis details: (-4.3 points, 2.0 required)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-1.8 ALL_TRUSTED Passed through trusted hosts only via SMTP\n\t-2.6 BAYES_00 BODY: Bayesian spam probability is 0 to 1%\n\t[score: 0.0000]\n\t0.0 UPPERCASE_25_50 message body is 25-50% uppercase\n\t0.1 AWL AWL: From: address is in the auto white-list", "Cc": "Ilya Yanok <yanok@emcraft.com>, dzu@denx.de, wd@denx.de", "X-BeenThere": "linuxppc-dev@ozlabs.org", "X-Mailman-Version": "2.1.11", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List <linuxppc-dev.ozlabs.org>", "List-Unsubscribe": "<https://ozlabs.org/mailman/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://ozlabs.org/pipermail/linuxppc-dev>", "List-Post": "<mailto:linuxppc-dev@ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@ozlabs.org?subject=help>", "List-Subscribe": "<https://ozlabs.org/mailman/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@ozlabs.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "linuxppc-dev-bounces+patchwork=ozlabs.org@ozlabs.org", "Errors-To": "linuxppc-dev-bounces+patchwork=ozlabs.org@ozlabs.org" }, "content": "This patch adds support for page sizes bigger than 4KB (16KB/64KB/256KB) on\nPPC 44x.\n\nSigned-off-by: Yuri Tikhonov <yur@emcraft.com>\nSigned-off-by: Ilya Yanok <yanok@emcraft.com>", "diff": "diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig\nindex 587da5e..ca93157 100644\n--- a/arch/powerpc/Kconfig\n+++ b/arch/powerpc/Kconfig\n@@ -413,6 +413,29 @@ config PPC_64K_PAGES\n \t while on hardware with such support, it will be used to map\n \t normal application pages.\n \n+choice\n+\tprompt \"Page size\"\n+\tdepends on 44x && PPC32\n+\tdefault PPC32_4K_PAGES\n+\thelp\n+\t The PAGE_SIZE definition. Increasing the page size may\n+\t improve the system performance in some dedicated cases.\n+\t If unsure, set it to 4 KB.\n+\n+config PPC32_4K_PAGES\n+\tbool \"4k page size\"\n+\n+config PPC32_16K_PAGES\n+\tbool \"16k page size\"\n+\n+config PPC32_64K_PAGES\n+\tbool \"64k page size\"\n+\n+config PPC32_256K_PAGES\n+\tbool \"256k page size\"\n+\n+endchoice\n+\n config FORCE_MAX_ZONEORDER\n \tint \"Maximum zone order\"\n \tdefault \"9\" if PPC_64K_PAGES\ndiff --git a/arch/powerpc/include/asm/highmem.h b/arch/powerpc/include/asm/highmem.h\nindex 5d99b64..1aec96d 100644\n--- a/arch/powerpc/include/asm/highmem.h\n+++ b/arch/powerpc/include/asm/highmem.h\n@@ -38,9 +38,15 @@ extern pte_t *pkmap_page_table;\n * easily, subsequent pte tables have to be allocated in one physical\n * chunk of RAM.\n */\n+#if defined(CONFIG_PPC32_64K_PAGES) || defined(CONFIG_PPC32_256K_PAGES)\n+#define PKMAP_ORDER\t(27 - PAGE_SHIFT)\n+#define LAST_PKMAP\t(1 << PKMAP_ORDER)\n+#define PKMAP_BASE\t(FIXADDR_START - PAGE_SIZE*(LAST_PKMAP + 1))\n+#else\n #define LAST_PKMAP \t(1 << PTE_SHIFT)\n-#define LAST_PKMAP_MASK (LAST_PKMAP-1)\n #define PKMAP_BASE\t((FIXADDR_START - PAGE_SIZE*(LAST_PKMAP + 1)) & PMD_MASK)\n+#endif\n+#define LAST_PKMAP_MASK\t(LAST_PKMAP-1)\n #define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT)\n #define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))\n \ndiff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h\nindex e088545..1de90b4 100644\n--- a/arch/powerpc/include/asm/page.h\n+++ b/arch/powerpc/include/asm/page.h\n@@ -15,12 +15,17 @@\n #include <asm/types.h>\n \n /*\n- * On PPC32 page size is 4K. For PPC64 we support either 4K or 64K software\n+ * On regular PPC32 page size is 4K (but we support 4K/16K/64K/256K pages\n+ * on PPC44x). For PPC64 we support either 4K or 64K software\n * page size. When using 64K pages however, whether we are really supporting\n * 64K pages in HW or not is irrelevant to those definitions.\n */\n-#ifdef CONFIG_PPC_64K_PAGES\n+#if defined(CONFIG_PPC32_256K_PAGES)\n+#define PAGE_SHIFT\t\t18\n+#elif defined(CONFIG_PPC32_64K_PAGES) || defined(CONFIG_PPC_64K_PAGES)\n #define PAGE_SHIFT\t\t16\n+#elif defined(CONFIG_PPC32_16K_PAGES)\n+#define PAGE_SHIFT\t\t14\n #else\n #define PAGE_SHIFT\t\t12\n #endif\n@@ -140,11 +145,19 @@ typedef struct { pte_basic_t pte; } pte_t;\n /* 64k pages additionally define a bigger \"real PTE\" type that gathers\n * the \"second half\" part of the PTE for pseudo 64k pages\n */\n+#ifdef CONFIG_PPC64\n #ifdef CONFIG_PPC_64K_PAGES\n typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;\n #else\n typedef struct { pte_t pte; } real_pte_t;\n #endif\n+#else\n+#ifdef CONFIG_PPC32_4K_PAGES\n+typedef struct { pte_t pte; } real_pte_t;\n+#else\n+typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;\n+#endif\n+#endif /* !CONFIG_PPC64 */\n \n /* PMD level */\n #ifdef CONFIG_PPC64\n@@ -180,12 +193,19 @@ typedef pte_basic_t pte_t;\n #define pte_val(x)\t(x)\n #define __pte(x)\t(x)\n \n+#ifdef CONFIG_PPC64\n #ifdef CONFIG_PPC_64K_PAGES\n typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;\n #else\n typedef unsigned long real_pte_t;\n #endif\n-\n+#else\n+#ifdef CONFIG_PPC32_4K_PAGES\n+typedef unsigned long real_pte_t;\n+#else\n+typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;\n+#endif\n+#endif /* !PPC64 */\n \n #ifdef CONFIG_PPC64\n typedef unsigned long pmd_t;\ndiff --git a/arch/powerpc/include/asm/page_32.h b/arch/powerpc/include/asm/page_32.h\nindex ebfae53..d176270 100644\n--- a/arch/powerpc/include/asm/page_32.h\n+++ b/arch/powerpc/include/asm/page_32.h\n@@ -20,7 +20,11 @@\n */\n #ifdef CONFIG_PTE_64BIT\n typedef unsigned long long pte_basic_t;\n+#ifdef CONFIG_PPC32_256K_PAGES\n+#define PTE_SHIFT\t(PAGE_SHIFT - 7)\n+#else\n #define PTE_SHIFT\t(PAGE_SHIFT - 3)\t/* 512 ptes per page */\n+#endif\n #else\n typedef unsigned long pte_basic_t;\n #define PTE_SHIFT\t(PAGE_SHIFT - 2)\t/* 1024 ptes per page */\ndiff --git a/arch/powerpc/include/asm/ppc_page_asm.h b/arch/powerpc/include/asm/ppc_page_asm.h\nnew file mode 100644\nindex 0000000..e1250fa\n--- /dev/null\n+++ b/arch/powerpc/include/asm/ppc_page_asm.h\n@@ -0,0 +1,75 @@\n+/*\n+ * arch/powerpc/include/asm/ppc_page_asm.h\n+ *\n+ * 2007 (C) DENX Software Engineering.\n+ *\n+ * This file is licensed under the terms of the GNU General Public License\n+ * version 2. This program is licensed \"as is\" without any warranty of\n+ * any kind, whether express or implied.\n+ *\n+ * The page definitions used in the asm files ppc_44x.S and misc.S.\n+ * PAGE_SIZE = 4K and 64K are only supported on the PPC44x.\n+ *\n+ */\n+#ifndef PPC_PAGE_ASM_H\n+#define PPC_PAGE_ASM_H\n+\n+#include <asm/page.h>\n+\n+#if (PAGE_SHIFT == 12)\n+/*\n+ * PAGE_SIZE 4K\n+ * PAGE_SHIFT 12\n+ * PTE_SHIFT 9\n+ * PMD_SHIFT 21\n+ */\n+#define PPC44x_TLBE_SIZE\tPPC44x_TLB_4K\n+#define PPC44x_PGD_OFF_SH\t13 /*(32 - PMD_SHIFT + 2)*/\n+#define PPC44x_PGD_OFF_M1\t19 /*(PMD_SHIFT - 2)*/\n+#define PPC44x_PTE_ADD_SH\t23 /*32 - PMD_SHIFT + PTE_SHIFT + 3*/\n+#define PPC44x_PTE_ADD_M1\t20 /*32 - 3 - PTE_SHIFT*/\n+#define PPC44x_RPN_M2\t\t19 /*31 - PAGE_SHIFT*/\n+#elif (PAGE_SHIFT == 14)\n+/*\n+ * PAGE_SIZE 16K\n+ * PAGE_SHIFT 14\n+ * PTE_SHIFT 11\n+ * PMD_SHIFT 25\n+ */\n+#define PPC44x_TLBE_SIZE\tPPC44x_TLB_16K\n+#define PPC44x_PGD_OFF_SH\t9 /*(32 - PMD_SHIFT + 2)*/\n+#define PPC44x_PGD_OFF_M1\t23 /*(PMD_SHIFT - 2)*/\n+#define PPC44x_PTE_ADD_SH\t21 /*32 - PMD_SHIFT + PTE_SHIFT + 3*/\n+#define PPC44x_PTE_ADD_M1\t18 /*32 - 3 - PTE_SHIFT*/\n+#define PPC44x_RPN_M2\t\t17 /*31 - PAGE_SHIFT*/\n+#elif (PAGE_SHIFT == 16)\n+/*\n+ * PAGE_SIZE 64K\n+ * PAGE_SHIFT 16\n+ * PTE_SHIFT 13\n+ * PMD_SHIFT 29\n+ */\n+#define PPC44x_TLBE_SIZE\tPPC44x_TLB_64K\n+#define PPC44x_PGD_OFF_SH\t5 /*(32 - PMD_SHIFT + 2)*/\n+#define PPC44x_PGD_OFF_M1\t27 /*(PMD_SHIFT - 2)*/\n+#define PPC44x_PTE_ADD_SH\t19 /*32 - PMD_SHIFT + PTE_SHIFT + 3*/\n+#define PPC44x_PTE_ADD_M1\t16 /*32 - 3 - PTE_SHIFT*/\n+#define PPC44x_RPN_M2\t\t15 /*31 - PAGE_SHIFT*/\n+#elif (PAGE_SHIFT == 18)\n+/*\n+ * PAGE_SIZE 256K\n+ * PAGE_SHIFT 18\n+ * PTE_SHIFT 11\n+ * PMD_SHIFT 29\n+ */\n+#define PPC44x_TLBE_SIZE\tPPC44x_TLB_256K\n+#define PPC44x_PGD_OFF_SH\t5 /*(32 - PMD_SHIFT + 2)*/\n+#define PPC44x_PGD_OFF_M1\t27 /*(PMD_SHIFT - 2)*/\n+#define PPC44x_PTE_ADD_SH\t17 /*32 - PMD_SHIFT + PTE_SHIFT + 3*/\n+#define PPC44x_PTE_ADD_M1\t18 /*32 - 3 - PTE_SHIFT*/\n+#define PPC44x_RPN_M2\t\t13 /*31 - PAGE_SHIFT*/\n+#else\n+#error \"Unsupported PAGE_SIZE\"\n+#endif\n+\n+#endif\ndiff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h\nindex 9665a26..4e7cd1f 100644\n--- a/arch/powerpc/include/asm/thread_info.h\n+++ b/arch/powerpc/include/asm/thread_info.h\n@@ -15,8 +15,12 @@\n #ifdef CONFIG_PPC64\n #define THREAD_SHIFT\t\t14\n #else\n+#if defined(CONFIG_PPC32_256K_PAGES)\n+#define THREAD_SHIFT\t\t15\n+#else\n #define THREAD_SHIFT\t\t13\n #endif\n+#endif\n \n #define THREAD_SIZE\t\t(1 << THREAD_SHIFT)\n \ndiff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S\nindex f3a1ea9..c0a99a4 100644\n--- a/arch/powerpc/kernel/head_44x.S\n+++ b/arch/powerpc/kernel/head_44x.S\n@@ -36,6 +36,7 @@\n #include <asm/thread_info.h>\n #include <asm/ppc_asm.h>\n #include <asm/asm-offsets.h>\n+#include <asm/ppc_page_asm.h>\n #include \"head_booke.h\"\n \n \n@@ -391,12 +392,14 @@ interrupt_base:\n \trlwimi\tr13,r12,10,30,30\n \n \t/* Load the PTE */\n-\trlwinm \tr12, r10, 13, 19, 29\t/* Compute pgdir/pmd offset */\n+\t/* Compute pgdir/pmd offset */\n+\trlwinm r12, r10, PPC44x_PGD_OFF_SH, PPC44x_PGD_OFF_M1, 29\n \tlwzx\tr11, r12, r11\t\t/* Get pgd/pmd entry */\n \trlwinm.\tr12, r11, 0, 0, 20\t/* Extract pt base address */\n \tbeq\t2f\t\t\t/* Bail if no table */\n \n-\trlwimi\tr12, r10, 23, 20, 28\t/* Compute pte address */\n+\t/* Compute pte address */\n+\trlwimi r12, r10, PPC44x_PTE_ADD_SH, PPC44x_PTE_ADD_M1, 28\n \tlwz\tr11, 0(r12)\t\t/* Get high word of pte entry */\n \tlwz\tr12, 4(r12)\t\t/* Get low word of pte entry */\n \n@@ -485,12 +488,14 @@ tlb_44x_patch_hwater_D:\n \t/* Make up the required permissions */\n \tli\tr13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC\n \n-\trlwinm\tr12, r10, 13, 19, 29\t/* Compute pgdir/pmd offset */\n+\t/* Compute pgdir/pmd offset */\n+\trlwinm \tr12, r10, PPC44x_PGD_OFF_SH, PPC44x_PGD_OFF_M1, 29\n \tlwzx\tr11, r12, r11\t\t/* Get pgd/pmd entry */\n \trlwinm.\tr12, r11, 0, 0, 20\t/* Extract pt base address */\n \tbeq\t2f\t\t\t/* Bail if no table */\n \n-\trlwimi\tr12, r10, 23, 20, 28\t/* Compute pte address */\n+\t/* Compute pte address */\n+\trlwimi\tr12, r10, PPC44x_PTE_ADD_SH, PPC44x_PTE_ADD_M1, 28\n \tlwz\tr11, 0(r12)\t\t/* Get high word of pte entry */\n \tlwz\tr12, 4(r12)\t\t/* Get low word of pte entry */\n \n@@ -554,14 +559,14 @@ tlb_44x_patch_hwater_I:\n */\n finish_tlb_load:\n \t/* Combine RPN & ERPN an write WS 0 */\n-\trlwimi\tr11,r12,0,0,19\n+\trlwimi\tr11,r12,0,0,PPC44x_RPN_M2\n \ttlbwe\tr11,r13,PPC44x_TLB_XLAT\n \n \t/*\n \t * Create WS1. This is the faulting address (EPN),\n \t * page size, and valid flag.\n \t */\n-\tli\tr11,PPC44x_TLB_VALID | PPC44x_TLB_4K\n+\tli\tr11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE\n \trlwimi\tr10,r11,0,20,31\t\t\t/* Insert valid and page size*/\n \ttlbwe\tr10,r13,PPC44x_TLB_PAGEID\t/* Write PAGEID */\n \n@@ -634,12 +639,12 @@ _GLOBAL(set_context)\n * goes at the beginning of the data segment, which is page-aligned.\n */\n \t.data\n-\t.align\t12\n+\t.align\tPAGE_SHIFT\n \t.globl\tsdata\n sdata:\n \t.globl\tempty_zero_page\n empty_zero_page:\n-\t.space\t4096\n+\t.space\tPAGE_SIZE\n \n /*\n * To support >32-bit physical addresses, we use an 8KB pgdir.\ndiff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h\nindex fce2df9..4f802df 100644\n--- a/arch/powerpc/kernel/head_booke.h\n+++ b/arch/powerpc/kernel/head_booke.h\n@@ -20,7 +20,9 @@\n \tbeq\t1f;\t\t\t\t\t\t\t \\\n \tmfspr\tr1,SPRN_SPRG3;\t\t/* if from user, start at top of */\\\n \tlwz\tr1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\\\n-\taddi\tr1,r1,THREAD_SIZE;\t\t\t\t\t \\\n+\tlis\tr11,THREAD_SIZE@h;\t\t\t\t\t \\\n+\tori\tr11,r11,THREAD_SIZE@l;\t\t\t\t\t \\\n+\tadd\tr1,r1,r11;\t\t\t\t\t\t \\\n 1:\tsubi\tr1,r1,INT_FRAME_SIZE;\t/* Allocate an exception frame */\\\n \tmr\tr11,r1;\t\t\t\t\t\t\t \\\n \tstw\tr10,_CCR(r11); /* save various registers\t */\\\n@@ -112,7 +114,8 @@\n \tandi.\tr10,r10,MSR_PR;\t\t\t\t\t\t \\\n \tmfspr\tr11,SPRN_SPRG3;\t\t/* if from user, start at top of */\\\n \tlwz\tr11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\\\n-\taddi\tr11,r11,EXC_LVL_FRAME_OVERHEAD;\t/* allocate stack frame */\\\n+\taddis\tr11,r11,EXC_LVL_FRAME_OVERHEAD@ha; /* allocate stack frame */\\\n+\taddi\tr11,r11,EXC_LVL_FRAME_OVERHEAD@l; /* allocate stack frame */\\\n \tbeq\t1f;\t\t\t\t\t\t\t \\\n \t/* COMING FROM USER MODE */\t\t\t\t\t \\\n \tstw\tr9,_CCR(r11);\t\t/* save CR\t\t\t */\\\ndiff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S\nindex 7a6dfbc..97463ba 100644\n--- a/arch/powerpc/kernel/misc_32.S\n+++ b/arch/powerpc/kernel/misc_32.S\n@@ -29,6 +29,7 @@\n #include <asm/asm-offsets.h>\n #include <asm/processor.h>\n #include <asm/kexec.h>\n+#include <asm/ppc_page_asm.h>\n \n \t.text\n \n@@ -589,8 +590,8 @@ _GLOBAL(__flush_dcache_icache)\n BEGIN_FTR_SECTION\n \tblr\n END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)\n-\trlwinm\tr3,r3,0,0,19\t\t\t/* Get page base address */\n-\tli\tr4,4096/L1_CACHE_BYTES\t/* Number of lines in a page */\n+\trlwinm\tr3,r3,0,0,PPC44x_RPN_M2\t\t/* Get page base address */\n+\tli\tr4,PAGE_SIZE/L1_CACHE_BYTES\t/* Number of lines in a page */\n \tmtctr\tr4\n \tmr\tr6,r3\n 0:\tdcbst\t0,r3\t\t\t\t/* Write line to ram */\n@@ -630,8 +631,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)\n \trlwinm\tr0,r10,0,28,26\t\t\t/* clear DR */\n \tmtmsr\tr0\n \tisync\n-\trlwinm\tr3,r3,0,0,19\t\t\t/* Get page base address */\n-\tli\tr4,4096/L1_CACHE_BYTES\t/* Number of lines in a page */\n+\trlwinm\tr3,r3,0,0,PPC44x_RPN_M2\t\t/* Get page base address */\n+\tli\tr4,PAGE_SIZE/L1_CACHE_BYTES\t/* Number of lines in a page */\n \tmtctr\tr4\n \tmr\tr6,r3\n 0:\tdcbst\t0,r3\t\t\t\t/* Write line to ram */\n@@ -655,7 +656,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)\n * void clear_pages(void *page, int order) ;\n */\n _GLOBAL(clear_pages)\n-\tli\tr0,4096/L1_CACHE_BYTES\n+\tli\tr0,PAGE_SIZE/L1_CACHE_BYTES\n \tslw\tr0,r0,r4\n \tmtctr\tr0\n #ifdef CONFIG_8xx\n@@ -713,7 +714,7 @@ _GLOBAL(copy_page)\n \tdcbt\tr5,r4\n \tli\tr11,L1_CACHE_BYTES+4\n #endif /* MAX_COPY_PREFETCH */\n-\tli\tr0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH\n+\tli\tr0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH\n \tcrclr\t4*cr0+eq\n 2:\n \tmtctr\tr0\ndiff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c\nindex 2001abd..efaf46a 100644\n--- a/arch/powerpc/mm/pgtable_32.c\n+++ b/arch/powerpc/mm/pgtable_32.c\n@@ -400,7 +400,7 @@ void kernel_map_pages(struct page *page, int numpages, int enable)\n #endif /* CONFIG_DEBUG_PAGEALLOC */\n \n static int fixmaps;\n-unsigned long FIXADDR_TOP = 0xfffff000;\n+unsigned long FIXADDR_TOP = (-PAGE_SIZE);\n EXPORT_SYMBOL(FIXADDR_TOP);\n \n void __set_fixmap (enum fixed_addresses idx, phys_addr_t phys, pgprot_t flags)\n", "prefixes": [] }