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GET /api/patches/2237945/?format=api
{ "id": 2237945, "url": "http://patchwork.ozlabs.org/api/patches/2237945/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260513163356.3033159-12-shaju.abraham@nutanix.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260513163356.3033159-12-shaju.abraham@nutanix.com>", "list_archive_url": null, "date": "2026-05-13T16:33:54", "name": "[RFC,v1,11/13] target/arm: named_cpu_model: introduce named CPU models for selected CPUs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "221b489b02db8b58965cd2861ae55c136974695b", "submitter": { "id": 77003, "url": "http://patchwork.ozlabs.org/api/people/77003/?format=api", "name": "Shaju Abraham", "email": "shaju.abraham@nutanix.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260513163356.3033159-12-shaju.abraham@nutanix.com/mbox/", "series": [ { "id": 504187, "url": "http://patchwork.ozlabs.org/api/series/504187/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=504187", "date": "2026-05-13T16:33:48", "name": "named CPU models for ARM64 on KVM", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/504187/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2237945/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2237945/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nutanix.com header.i=@nutanix.com header.a=rsa-sha256\n header.s=proofpoint20171006 header.b=OARFURDk;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nutanix.com header.i=@nutanix.com header.a=rsa-sha256\n header.s=selector1 header.b=y98vnMZj;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nutanix.com; dmarc=pass action=none header.from=nutanix.com;\n dkim=pass header.d=nutanix.com; arc=none", "From": "Shaju Abraham <shaju.abraham@nutanix.com>", "To": "eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org,\n kvmarm@lists.linux.dev, peter.maydell@linaro.org,\n richard.henderson@linaro.org, cohuck@redhat.com, sebott@redhat.com,\n skolothumtho@nvidia.com, philmd@linaro.org", "Cc": "maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com,\n prerna.saxena@nutanix.com, jon@nutanix.com, jond@nutanix.com,\n Shaju Abraham <shaju.abraham@nutanix.com>,\n Khushit Shah <khushit.shah@nutanix.com>", "Subject": "[RFC PATCH v1 11/13] target/arm: named_cpu_model: introduce named CPU\n models for selected CPUs", "Date": "Wed, 13 May 2026 16:33:54 +0000", "Message-ID": "<20260513163356.3033159-12-shaju.abraham@nutanix.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260513163356.3033159-1-shaju.abraham@nutanix.com>", "References": "<20260513163356.3033159-1-shaju.abraham@nutanix.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "CY5PR10CA0003.namprd10.prod.outlook.com\n (2603:10b6:930:1c::30) To PH7PR02MB10160.namprd02.prod.outlook.com\n (2603:10b6:510:2e7::19)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "PH7PR02MB10160:EE_|SJ0PR02MB8813:EE_", "X-MS-Office365-Filtering-Correlation-Id": "094a4113-2449-4b99-2729-08deb10d804b", "x-proofpoint-crosstenant": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|7416014|376014|366016|1800799024|921020|18002099003|22082099003|56012099003|3023799003;", "X-Microsoft-Antispam-Message-Info": "\n 1L1xxN1VLvPgu31wQ11sIcf5ikRmwxidwrCAhig7x3BxnLufBYZmz/OpIYkpjCkQPtYbctpVLP8QAL/LOYOUdPpWg4VsLAKdBeKuYrHWfLn5amE+KNfCbV3+Z+GtoBCFzuOYVJOPM6HLJdxV5v9heFC5YWQbRp53p0/+auHXaPGU4rElV/pwFO5bVI4b6mtnaP1x52j3J94XB4hW69/tmE3Eg00gLkWRYlTteu7FGDK56eLJzQO1Z3QrH7s6U6e9/uEAoUtQswvEY/p+JMGl8g3mfjOWTcTe7gLAgU72+6P8R9XorIEdrKFkn1D0abXQE9DfFvI5KYmJ2ctAVRO3JgtUGI22wKMepFs+zXjsJzF/yBNMwKvkXm+YLO5agkEWrlzJ5/CRsQrDaNtoNzRKxK9yalv/2Ku7LaPsVVsvms3Wzb49zjdXnls+yvENAkjvp/j46yBKGTYyR/pj3IXI3JfDdvMIexvBvVPcl/ULsUzRxCaxBcJ1zTROzk2+34U1dHYvjHgGILN1q7YQPDzXaDIy7HqioF4MFwPHXzW1cKkj5w7qGvgwMM8PvgT96OSYgCggfrMcNCPl6LstIQj0K4D7cPAaxrPwIkLouq+n1LAq98OgDCnhwA0CQiQmIQBK5vLhqnhJ2GY12VjmP5vyvRVTJVS4W+5hQPSUzDfgimJzYVgdIdq30/05ptLqvBbqUhf0M5qhmzP6J1oXt8enFJ7XqL+mfHVffKjg/i3U57k=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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helo=mx0a-002c1b01.pphosted.com", "X-Spam_score_int": "-31", "X-Spam_score": "-3.2", "X-Spam_bar": "---", "X-Spam_report": "(-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Introduce a small named-CPU-model layer on top of the field-backed property\ninfrastructure. Each model is a flat table of (name, value) overrides and a\nparent pointer. At instance-init, the parent chain is walked root-first and\nevery level's properties are applied via QOM, so a child entry overrides\nits ancestors for the same name.\n\nFor example, the grace-v1 named model hierarchy is:\nkvm-base-v1 KVM-imposed quirks (chain root)\narm-v8_4-a-v1 ARMv8.4-A architectural mandate\narm-v9_0-a-v1 ARMv9.0-A architectural deltas\nneoverse-v2-v1 Neoverse V2\ngrace-v1 NVIDIA Grace\n\narm-v8_4-a-v1, arm-v9_0-a-v1:\nOnly features mandated by the corresponding ARM ARM\nrevision. No optional features.\n\nneoverse-v[12]-v1:\nReferrence manual derived feature values for the reference core. Values\ndiffer from reference core values based on what was exposed to the guest\nwith -cpu host.\n\ngrace-v1:\nSoC integration choices (crypto pin, cache hints,\nPAuth alg).\n\nmodel realization logic:\n1. arm_idregs_reset_to_defaults(cpu): Reset cpu->isar.idregs[] to the\n default values.\n2. Add all properties to the CPU Object\n3. arm_realize_model_chain(obj, model, &error_abort): Walk the parent chain\n from root first and apply all the properties.\n\nCo-authored-by: Khushit Shah <khushit.shah@nutanix.com>\nSigned-off-by: Shaju Abraham <shaju.abraham@nutanix.com>\n---\n hw/arm/virt.c | 8 ++\n target/arm/arm-cpu-models.c | 214 ++++++++++++++++++++++++++++++++\n target/arm/arm-cpu-models.h | 43 +++++++\n target/arm/arm-v8_4-a-v1.inc.h | 22 ++++\n target/arm/arm-v9_0-a-v1.inc.h | 28 +++++\n target/arm/grace-v1.inc.h | 17 +++\n target/arm/graviton3-v1.inc.h | 16 +++\n target/arm/kvm-base-v1.inc.h | 13 ++\n target/arm/meson.build | 5 +-\n target/arm/neoverse-v1-v1.inc.h | 64 ++++++++++\n target/arm/neoverse-v2-v1.inc.h | 64 ++++++++++\n 11 files changed, 493 insertions(+), 1 deletion(-)\n create mode 100644 target/arm/arm-cpu-models.c\n create mode 100644 target/arm/arm-cpu-models.h\n create mode 100644 target/arm/arm-v8_4-a-v1.inc.h\n create mode 100644 target/arm/arm-v9_0-a-v1.inc.h\n create mode 100644 target/arm/grace-v1.inc.h\n create mode 100644 target/arm/graviton3-v1.inc.h\n create mode 100644 target/arm/kvm-base-v1.inc.h\n create mode 100644 target/arm/neoverse-v1-v1.inc.h\n create mode 100644 target/arm/neoverse-v2-v1.inc.h", "diff": "diff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex 10b1954382..bbb5f0a241 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -4069,6 +4069,14 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)\n g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME(\"host\")));\n }\n }\n+ if (kvm_enabled() && target_aarch64()) {\n+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME(\"arm-v8_4-a-v1\")));\n+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME(\"arm-v9_0-a-v1\")));\n+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME(\"neoverse-v1-v1\")));\n+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME(\"neoverse-v2-v1\")));\n+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME(\"grace-v1\")));\n+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME(\"graviton3-v1\")));\n+ }\n g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME(\"max\")));\n \n return vct;\ndiff --git a/target/arm/arm-cpu-models.c b/target/arm/arm-cpu-models.c\nnew file mode 100644\nindex 0000000000..fff7522a64\n--- /dev/null\n+++ b/target/arm/arm-cpu-models.c\n@@ -0,0 +1,214 @@\n+/*\n+ * ARM named CPU model definitions.\n+ *\n+ * Each model is defined in its own .inc.h file using the ARM_PROP()\n+ * macro, listing only the properties that DIFFER from the parent\n+ * model. At realisation the parent chain is walked root-first and\n+ * every level's props are applied via QOM, so the leaf's values\n+ * naturally override its ancestors.\n+ *\n+ * Hierarchy (single-parent inheritance):\n+ *\n+ * kvm-base-v1 KVM-imposed quirks (chain root)\n+ * arm-v8_4-a-v1 ARMv8.4-A architectural mandate\n+ * arm-v9_0-a-v1 ARMv9.0-A architectural deltas\n+ * neoverse-v2-v1 Neoverse V2 (TRM 102375)\n+ * grace-v1 NVIDIA Grace\n+ * neoverse-v1-v1 Neoverse V1 (TRM 102649)\n+ * graviton3-v1 AWS Graviton3\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qapi/error.h\"\n+#include \"qemu/error-report.h\"\n+#include \"system/kvm.h\"\n+#include \"cpu.h\"\n+#include \"internals.h\"\n+#include \"kvm_arm.h\"\n+#include \"arm-cpu-models.h\"\n+#include \"arm-cpu-props.h\"\n+#include \"cpu-idregs.h\"\n+\n+static const ArmModelPropValue kvm_base_v1_props[] = {\n+#include \"kvm-base-v1.inc.h\"\n+};\n+\n+static const ArmModelPropValue armv8_4_a_v1_props[] = {\n+#include \"arm-v8_4-a-v1.inc.h\"\n+};\n+\n+static const ArmModelPropValue armv9_0_a_v1_props[] = {\n+#include \"arm-v9_0-a-v1.inc.h\"\n+};\n+\n+static const ArmModelPropValue neoverse_v1_v1_props[] = {\n+#include \"neoverse-v1-v1.inc.h\"\n+};\n+\n+static const ArmModelPropValue neoverse_v2_v1_props[] = {\n+#include \"neoverse-v2-v1.inc.h\"\n+};\n+\n+static const ArmModelPropValue grace_v1_props[] = {\n+#include \"grace-v1.inc.h\"\n+};\n+\n+static const ArmModelPropValue graviton3_v1_props[] = {\n+#include \"graviton3-v1.inc.h\"\n+};\n+\n+static const ArmNamedCpuModel arm_cpu_models[] = {\n+ {\n+ .name = \"kvm-base-v1\",\n+ .parent = NULL,\n+ .props = kvm_base_v1_props,\n+ },\n+ {\n+ .name = \"arm-v8_4-a-v1\",\n+ .parent = \"kvm-base-v1\",\n+ .props = armv8_4_a_v1_props,\n+ },\n+ {\n+ .name = \"neoverse-v1-v1\",\n+ .parent = \"arm-v8_4-a-v1\",\n+ .props = neoverse_v1_v1_props,\n+ },\n+ {\n+ .name = \"graviton3-v1\",\n+ .parent = \"neoverse-v1-v1\",\n+ .props = graviton3_v1_props,\n+ },\n+ {\n+ .name = \"arm-v9_0-a-v1\",\n+ .parent = \"arm-v8_4-a-v1\",\n+ .props = armv9_0_a_v1_props,\n+ },\n+ {\n+ .name = \"neoverse-v2-v1\",\n+ .parent = \"arm-v9_0-a-v1\",\n+ .props = neoverse_v2_v1_props,\n+ },\n+ {\n+ .name = \"grace-v1\",\n+ .parent = \"neoverse-v2-v1\",\n+ .props = grace_v1_props,\n+ },\n+};\n+\n+static ARMCPUInfo arm_named_cpu_infos[ARRAY_SIZE(arm_cpu_models)];\n+static const ArmNamedCpuModel *arm_find_model(const char *name)\n+{\n+ size_t i;\n+ for (i = 0; i < ARRAY_SIZE(arm_cpu_models); i++) {\n+ if (g_str_equal(arm_cpu_models[i].name, name)) {\n+ return &arm_cpu_models[i];\n+ }\n+ }\n+ return NULL;\n+}\n+\n+static void arm_apply_model_props(Object *obj, const ArmModelPropValue *props,\n+ Error **errp)\n+{\n+ const ArmModelPropValue *pv;\n+ ERRP_GUARD();\n+\n+ for (pv = props; pv->name; pv++) {\n+ switch (pv->type) {\n+ case ARM_MODEL_PROP_STR:\n+ object_property_set_str(obj, pv->name, pv->str, errp);\n+ break;\n+ case ARM_MODEL_PROP_BOOL:\n+ object_property_set_bool(obj, pv->name, pv->b, errp);\n+ break;\n+ case ARM_MODEL_PROP_NUM:\n+ object_property_set_uint(obj, pv->name, pv->num, errp);\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+ if (*errp) {\n+ error_prepend(errp, \"property '%s': \", pv->name);\n+ return;\n+ }\n+ }\n+}\n+\n+static void arm_realize_model_chain(Object *obj, const ArmNamedCpuModel *model,\n+ Error **errp)\n+{\n+ const ArmNamedCpuModel *cur, *parent;\n+ const ArmNamedCpuModel *chain[ARRAY_SIZE(arm_cpu_models)];\n+ size_t depth = 0;\n+ for (cur = model; cur; ) {\n+ if (depth >= ARRAY_SIZE(chain)) {\n+ error_setg(errp, \"model '%s': parent chain too deep \"\n+ \"(possible cycle)\", model->name);\n+ return;\n+ }\n+ chain[depth++] = cur;\n+\n+ if (!cur->parent) {\n+ break;\n+ }\n+ parent = arm_find_model(cur->parent);\n+ if (!parent) {\n+ error_setg(errp, \"model '%s': unknown parent '%s'\",\n+ cur->name, cur->parent);\n+ return;\n+ }\n+ cur = parent;\n+ }\n+\n+ while (depth--) {\n+ arm_apply_model_props(obj, chain[depth]->props, errp);\n+ if (*errp) {\n+ return;\n+ }\n+ }\n+}\n+\n+static void arm_named_cpu_initfn(Object *obj)\n+{\n+ ARMCPU *cpu = ARM_CPU(obj);\n+ ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);\n+ const ArmNamedCpuModel *model = arm_find_model(acc->info->name);\n+ if (!model) {\n+ error_report(\"'%s' CPU model entry not found)\",\n+ acc->info->name);\n+ return;\n+ }\n+\n+ if (!kvm_enabled()) {\n+ error_report(\"'%s' CPU model requires KVM (-accel kvm)\",\n+ acc->info->name);\n+ return;\n+ }\n+\n+ kvm_arm_set_cpu_features_from_host(cpu);\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {\n+ return;\n+ }\n+\n+ arm_idregs_reset_to_defaults(cpu);\n+\n+ aarch64_add_sve_properties(obj);\n+ aarch64_add_pauth_properties(obj);\n+ arm_add_cpu_props(obj);\n+\n+ arm_realize_model_chain(obj, model, &error_abort);\n+}\n+\n+void arm_register_named_cpu_models(void)\n+{\n+ size_t i;\n+ for (i = 0; i < ARRAY_SIZE(arm_cpu_models); i++) {\n+ arm_named_cpu_infos[i].name = arm_cpu_models[i].name;\n+ arm_named_cpu_infos[i].initfn = arm_named_cpu_initfn;\n+ arm_cpu_register(&arm_named_cpu_infos[i]);\n+ }\n+}\n+\n+type_init(arm_register_named_cpu_models)\ndiff --git a/target/arm/arm-cpu-models.h b/target/arm/arm-cpu-models.h\nnew file mode 100644\nindex 0000000000..830a9bdc4a\n--- /dev/null\n+++ b/target/arm/arm-cpu-models.h\n@@ -0,0 +1,43 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+/*\n+ * ARM named CPU model definitions - public API.\n+ */\n+#ifndef ARM_CPU_MODELS_H\n+#define ARM_CPU_MODELS_H\n+\n+#include \"qapi/error.h\"\n+#include \"qom/object.h\"\n+\n+typedef enum ArmModelPropType {\n+ ARM_MODEL_PROP_STR,\n+ ARM_MODEL_PROP_BOOL,\n+ ARM_MODEL_PROP_NUM,\n+} ArmModelPropType;\n+\n+typedef struct ArmModelPropValue {\n+ const char *name;\n+ ArmModelPropType type;\n+ bool b;\n+ uint64_t num;\n+ const char *str;\n+} ArmModelPropValue;\n+\n+typedef struct ArmNamedCpuModel {\n+ const char *name;\n+ const char *parent;\n+ const ArmModelPropValue *props;\n+} ArmNamedCpuModel;\n+\n+#define ARM_PROP_FIELD_STR str\n+#define ARM_PROP_FIELD_BOOL b\n+#define ARM_PROP_FIELD_NUM num\n+\n+#define ARM_PROP(_name, _type, _value) \\\n+ { .name = (_name), .type = ARM_MODEL_PROP_##_type, \\\n+ .ARM_PROP_FIELD_##_type = (_value) }\n+\n+#define ARM_PROP_END { .name = NULL }\n+\n+void arm_register_named_cpu_models(void);\n+\n+#endif /* ARM_CPU_MODELS_H */\ndiff --git a/target/arm/arm-v8_4-a-v1.inc.h b/target/arm/arm-v8_4-a-v1.inc.h\nnew file mode 100644\nindex 0000000000..1bad59ba2d\n--- /dev/null\n+++ b/target/arm/arm-v8_4-a-v1.inc.h\n@@ -0,0 +1,22 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+ARM_PROP(\"feat_CRC32\", STR, \"on\"),\n+ARM_PROP(\"feat_ATOMIC\", STR, \"on\"),\n+ARM_PROP(\"feat_HPDS\", STR, \"on\"),\n+ARM_PROP(\"feat_LO\", STR, \"on\"),\n+\n+ARM_PROP(\"feat_DPB\", STR, \"on\"),\n+ARM_PROP(\"feat_RAS\", STR, \"1.0\"),\n+ARM_PROP(\"feat_PAN\", STR, \"pan2\"),\n+ARM_PROP(\"feat_UAO\", STR, \"on\"),\n+ARM_PROP(\"feat_CNP\", STR, \"on\"),\n+ARM_PROP(\"feat_IESB\", STR, \"on\"),\n+\n+ARM_PROP(\"feat_DIT\", STR, \"on\"),\n+ARM_PROP(\"feat_DBG\", STR, \"v8p4\"),\n+ARM_PROP(\"feat_PMU\", STR, \"v3p4\"),\n+ARM_PROP(\"feat_TS\", STR, \"flagm\"),\n+ARM_PROP(\"feat_LRCPC\", STR, \"lrcpc2\"),\n+ARM_PROP(\"feat_AT\", STR, \"on\"),\n+ARM_PROP(\"hw_prop_IDS\", STR, \"0x18\"),\n+\n+ARM_PROP_END,\ndiff --git a/target/arm/arm-v9_0-a-v1.inc.h b/target/arm/arm-v9_0-a-v1.inc.h\nnew file mode 100644\nindex 0000000000..5ebe728133\n--- /dev/null\n+++ b/target/arm/arm-v9_0-a-v1.inc.h\n@@ -0,0 +1,28 @@\n+\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+ARM_PROP(\"feat_BT\", STR, \"on\"),\n+ARM_PROP(\"feat_CSV2\", STR, \"1.0\"),\n+ARM_PROP(\"feat_CSV3\", STR, \"on\"),\n+ARM_PROP(\"feat_DPB\", STR, \"dpb2\"),\n+ARM_PROP(\"feat_E0PD\", STR, \"on\"),\n+ARM_PROP(\"feat_SB\", STR, \"on\"),\n+ARM_PROP(\"feat_SPECRES\", STR, \"on\"),\n+ARM_PROP(\"feat_SSBS\", STR, \"ssbs2\"),\n+\n+ARM_PROP(\"feat_DoubleLock\", STR, \"off\"),\n+ARM_PROP(\"feat_FP\", STR, \"on\"),\n+ARM_PROP(\"feat_AdvSIMD\", STR, \"on\"),\n+ARM_PROP(\"feat_TS\", STR, \"flagm2\"),\n+ARM_PROP(\"feat_FRINTTS\", STR, \"on\"),\n+ARM_PROP(\"feat_RDM\", STR, \"on\"),\n+ARM_PROP(\"feat_DP\", STR, \"on\"),\n+ARM_PROP(\"feat_FHM\", STR, \"on\"),\n+ARM_PROP(\"feat_FCMA\", STR, \"on\"),\n+ARM_PROP(\"feat_JSCVT\", STR, \"on\"),\n+\n+ARM_PROP(\"feat_SVE\", STR, \"on\"),\n+ARM_PROP(\"feat_SEL2\", STR, \"on\"),\n+ARM_PROP(\"feat_VH\", STR, \"on\"),\n+ARM_PROP(\"feat_XNX\", STR, \"on\"),\n+\n+ARM_PROP_END,\ndiff --git a/target/arm/grace-v1.inc.h b/target/arm/grace-v1.inc.h\nnew file mode 100644\nindex 0000000000..048ebb993d\n--- /dev/null\n+++ b/target/arm/grace-v1.inc.h\n@@ -0,0 +1,17 @@\n+\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+ARM_PROP(\"cpu_revision\", NUM, 0x0),\n+\n+ARM_PROP(\"feat_AES\", STR, \"pmull\"),\n+ARM_PROP(\"feat_SHA1\", STR, \"on\"),\n+ARM_PROP(\"feat_SHA2\", STR, \"sha512\"),\n+ARM_PROP(\"feat_SHA3\", STR, \"on\"),\n+ARM_PROP(\"feat_SM3\", STR, \"on\"),\n+ARM_PROP(\"feat_SM4\", STR, \"on\"),\n+\n+ARM_PROP(\"hw_prop_IDC\", BOOL, true),\n+ARM_PROP(\"hw_prop_DIC\", BOOL, true),\n+\n+ARM_PROP(\"cpu_revidr\", NUM, 1),\n+\n+ARM_PROP_END,\ndiff --git a/target/arm/graviton3-v1.inc.h b/target/arm/graviton3-v1.inc.h\nnew file mode 100644\nindex 0000000000..9538c3e539\n--- /dev/null\n+++ b/target/arm/graviton3-v1.inc.h\n@@ -0,0 +1,16 @@\n+\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+ARM_PROP(\"feat_AES\", STR, \"pmull\"),\n+ARM_PROP(\"feat_SHA1\", STR, \"on\"),\n+ARM_PROP(\"feat_SHA2\", STR, \"sha512\"),\n+ARM_PROP(\"feat_SHA3\", STR, \"on\"),\n+ARM_PROP(\"feat_SM3\", STR, \"on\"),\n+ARM_PROP(\"feat_SM4\", STR, \"on\"),\n+ARM_PROP(\"feat_RNDR\", STR, \"on\"),\n+\n+ARM_PROP(\"hw_prop_IDC\", BOOL, true),\n+ARM_PROP(\"hw_prop_DIC\", BOOL, true),\n+\n+ARM_PROP(\"cpu_revidr\", NUM, 1),\n+\n+ARM_PROP_END,\ndiff --git a/target/arm/kvm-base-v1.inc.h b/target/arm/kvm-base-v1.inc.h\nnew file mode 100644\nindex 0000000000..e0bae90629\n--- /dev/null\n+++ b/target/arm/kvm-base-v1.inc.h\n@@ -0,0 +1,13 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+ARM_PROP(\"el0_mode\", STR, \"aarch64\"),\n+ARM_PROP(\"el1_mode\", STR, \"aarch64\"),\n+ARM_PROP(\"el2_mode\", STR, \"off\"),\n+ARM_PROP(\"el3_mode\", STR, \"off\"),\n+ARM_PROP(\"feat_GIC\", STR, \"on\"),\n+ARM_PROP(\"feat_AMU\", STR, \"off\"),\n+ARM_PROP(\"feat_MPAM\", STR, \"0.0\"),\n+ARM_PROP(\"feat_NV\", STR, \"0.0\"),\n+ARM_PROP(\"feat_MTE_FRAC\", STR, \"async\"),\n+ARM_PROP(\"hw_prop_CCIDX\", STR, \"32\"),\n+\n+ARM_PROP_END,\ndiff --git a/target/arm/meson.build b/target/arm/meson.build\nindex 01b1e91a1c..79a22eec3f 100644\n--- a/target/arm/meson.build\n+++ b/target/arm/meson.build\n@@ -22,7 +22,10 @@ arm_common_system_ss.add(files(\n 'arm-qmp-cmds.c',\n 'cpu-idregs.c',\n ))\n-arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'))\n+arm_system_ss.add(when: 'CONFIG_KVM',\n+ if_true: files('arm-cpu-models.c',\n+ 'hyp_gdbstub.c',\n+ 'kvm.c'))\n arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c'))\n \n arm_user_ss.add(files('cpu.c'))\ndiff --git a/target/arm/neoverse-v1-v1.inc.h b/target/arm/neoverse-v1-v1.inc.h\nnew file mode 100644\nindex 0000000000..5ded208a5e\n--- /dev/null\n+++ b/target/arm/neoverse-v1-v1.inc.h\n@@ -0,0 +1,64 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+ARM_PROP(\"cpu_implementer\", NUM, 0x41),\n+ARM_PROP(\"cpu_variant\", NUM, 0x1),\n+ARM_PROP(\"cpu_architecture\", NUM, 0xF),\n+ARM_PROP(\"cpu_partnum\", NUM, 0xD40),\n+ARM_PROP(\"cpu_revision\", NUM, 0x1),\n+\n+ARM_PROP(\"hw_prop_BRPS\", NUM, 0x5),\n+ARM_PROP(\"hw_prop_WRPs\", NUM, 0x3),\n+ARM_PROP(\"hw_prop_CTX_CMPs\", NUM, 0x1),\n+ARM_PROP(\"feat_DoubleLock\", STR, \"off\"),\n+\n+ARM_PROP(\"feat_RDM\", STR, \"on\"),\n+ARM_PROP(\"feat_DP\", STR, \"on\"),\n+ARM_PROP(\"feat_FHM\", STR, \"on\"),\n+\n+ARM_PROP(\"feat_DPB\", STR, \"dpb2\"),\n+ARM_PROP(\"feat_JSCVT\", STR, \"on\"),\n+ARM_PROP(\"feat_FCMA\", STR, \"on\"),\n+ARM_PROP(\"feat_BF16\", STR, \"on\"),\n+ARM_PROP(\"feat_DGH\", STR, \"on\"),\n+ARM_PROP(\"feat_I8MM\", STR, \"on\"),\n+\n+ARM_PROP(\"feat_FP\", STR, \"fp16\"),\n+ARM_PROP(\"feat_AdvSIMD\", STR, \"fp16\"),\n+ARM_PROP(\"feat_RAS\", STR, \"1.1_base\"),\n+ARM_PROP(\"feat_CSV2\", STR, \"1.0\"),\n+ARM_PROP(\"feat_CSV3\", STR, \"on\"),\n+\n+ARM_PROP(\"feat_SSBS\", STR, \"ssbs2\"),\n+\n+ARM_PROP(\"hw_prop_PARANGE\", STR, \"48\"),\n+ARM_PROP(\"hw_prop_ASIDBITS\", STR, \"16\"),\n+ARM_PROP(\"feat_BIGEND\", STR, \"on\"),\n+ARM_PROP(\"feat_SNSMEM\", STR, \"on\"),\n+ARM_PROP(\"hw_prop_TGRAN4\", STR, \"on\"),\n+ARM_PROP(\"hw_prop_TGRAN16\", STR, \"on\"),\n+ARM_PROP(\"hw_prop_TGRAN64\", STR, \"on\"),\n+ARM_PROP(\"hw_prop_TGRAN4_2\", STR, \"tgran4\"),\n+ARM_PROP(\"hw_prop_TGRAN16_2\", STR, \"tgran16\"),\n+ARM_PROP(\"hw_prop_TGRAN64_2\", STR, \"tgran64\"),\n+\n+ARM_PROP(\"feat_HAFDBS\", STR, \"dbm\"),\n+ARM_PROP(\"hw_prop_VMIDBITS\", STR, \"16\"),\n+ARM_PROP(\"feat_VH\", STR, \"on\"),\n+ARM_PROP(\"feat_HPDS\", STR, \"hpds2\"),\n+ARM_PROP(\"feat_XNX\", STR, \"on\"),\n+ARM_PROP(\"feat_SpecSEI\", STR, \"off\"),\n+\n+ARM_PROP(\"hw_prop_FWB\", STR, \"on\"),\n+ARM_PROP(\"feat_BBM\", STR, \"2\"),\n+ARM_PROP(\"feat_EVT\", STR, \"ttlbxs\"),\n+\n+ARM_PROP(\"feat_E2H0\", STR, \"on\"),\n+\n+ARM_PROP(\"hw_prop_IMInline\", NUM, 4),\n+ARM_PROP(\"hw_prop_L1IP\", STR, \"pipt\"),\n+ARM_PROP(\"hw_prop_DMInline\", NUM, 4),\n+ARM_PROP(\"hw_prop_ERG\", NUM, 4),\n+ARM_PROP(\"hw_prop_CWG\", NUM, 4),\n+\n+ARM_PROP(\"hw_prop_BS\", NUM, 0x4),\n+\n+ARM_PROP_END,\ndiff --git a/target/arm/neoverse-v2-v1.inc.h b/target/arm/neoverse-v2-v1.inc.h\nnew file mode 100644\nindex 0000000000..a32f80cd55\n--- /dev/null\n+++ b/target/arm/neoverse-v2-v1.inc.h\n@@ -0,0 +1,64 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+ARM_PROP(\"cpu_implementer\", NUM, 0x41),\n+ARM_PROP(\"cpu_variant\", NUM, 0x0),\n+ARM_PROP(\"cpu_architecture\", NUM, 0xF),\n+ARM_PROP(\"cpu_partnum\", NUM, 0xD4F),\n+ARM_PROP(\"cpu_revision\", NUM, 0x2),\n+\n+ARM_PROP(\"hw_prop_BRPS\", NUM, 0x5),\n+ARM_PROP(\"hw_prop_WRPs\", NUM, 0x3),\n+ARM_PROP(\"hw_prop_CTX_CMPs\", NUM, 0x1),\n+ARM_PROP(\"feat_PMU\", STR, \"v3p5\"),\n+\n+ARM_PROP(\"feat_TLB\", STR, \"range\"),\n+\n+ARM_PROP(\"feat_BF16\", STR, \"on\"),\n+ARM_PROP(\"feat_DGH\", STR, \"on\"),\n+ARM_PROP(\"feat_I8MM\", STR, \"on\"),\n+\n+ARM_PROP(\"feat_FP\", STR, \"fp16\"),\n+ARM_PROP(\"feat_AdvSIMD\", STR, \"fp16\"),\n+ARM_PROP(\"feat_RAS\", STR, \"1.1_base\"),\n+\n+/*\n+ * V2 silicon may report CSV2=2 (FEAT_CSV2_2) per TRM page 392, but\n+ * KVM clamps the guest-visible limit to 1.\n+ */\n+ARM_PROP(\"feat_CSV2\", STR, \"1.0\"),\n+\n+\n+ARM_PROP(\"hw_prop_PARANGE\", STR, \"48\"),\n+ARM_PROP(\"hw_prop_ASIDBITS\", STR, \"16\"),\n+ARM_PROP(\"feat_BIGEND\", STR, \"on\"),\n+ARM_PROP(\"feat_SNSMEM\", STR, \"on\"),\n+ARM_PROP(\"hw_prop_TGRAN16\", STR, \"on\"),\n+ARM_PROP(\"hw_prop_TGRAN64\", STR, \"on\"),\n+ARM_PROP(\"hw_prop_TGRAN4\", STR, \"on\"),\n+ARM_PROP(\"hw_prop_TGRAN16_2\", STR, \"on\"),\n+ARM_PROP(\"hw_prop_TGRAN64_2\", STR, \"on\"),\n+ARM_PROP(\"hw_prop_TGRAN4_2\", STR, \"on\"),\n+\n+ARM_PROP(\"feat_HAFDBS\", STR, \"dbm\"),\n+ARM_PROP(\"hw_prop_VMIDBITS\", STR, \"16\"),\n+ARM_PROP(\"feat_HPDS\", STR, \"hpds2\"),\n+ARM_PROP(\"feat_PAN\", STR, \"pan3\"),\n+ARM_PROP(\"feat_ECBHB\", STR, \"off\"),\n+ARM_PROP(\"feat_SpecSEI\", STR, \"off\"),\n+\n+ARM_PROP(\"hw_prop_FWB\", STR, \"on\"),\n+ARM_PROP(\"hw_prop_ST\", STR, \"48_47\"),\n+ARM_PROP(\"feat_TTL\", STR, \"on\"),\n+ARM_PROP(\"feat_BBM\", STR, \"2\"),\n+ARM_PROP(\"feat_EVT\", STR, \"ttlbxs\"),\n+ARM_PROP(\"feat_E2H0\", STR, \"on\"),\n+\n+\n+ARM_PROP(\"hw_prop_IMInline\", NUM, 4),\n+ARM_PROP(\"hw_prop_L1IP\", STR, \"pipt\"),\n+ARM_PROP(\"hw_prop_DMInline\", NUM, 4),\n+ARM_PROP(\"hw_prop_ERG\", NUM, 4),\n+ARM_PROP(\"hw_prop_CWG\", NUM, 4),\n+\n+ARM_PROP(\"hw_prop_BS\", NUM, 0x4),\n+\n+ARM_PROP_END,\n", "prefixes": [ "RFC", "v1", "11/13" ] }