Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2237942/?format=api
{ "id": 2237942, "url": "http://patchwork.ozlabs.org/api/patches/2237942/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260513163356.3033159-5-shaju.abraham@nutanix.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260513163356.3033159-5-shaju.abraham@nutanix.com>", "list_archive_url": null, "date": "2026-05-13T16:33:47", "name": "[RFC,v1,04/13] target/arm: named_cpu_model: generate tables for Arm64 ID registers and fields", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3846b364564d00ac365a53970e01d400668b2609", "submitter": { "id": 77003, "url": "http://patchwork.ozlabs.org/api/people/77003/?format=api", "name": "Shaju Abraham", "email": "shaju.abraham@nutanix.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260513163356.3033159-5-shaju.abraham@nutanix.com/mbox/", "series": [ { "id": 504187, "url": "http://patchwork.ozlabs.org/api/series/504187/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=504187", "date": "2026-05-13T16:33:48", "name": "named CPU models for ARM64 on KVM", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/504187/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2237942/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2237942/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nutanix.com header.i=@nutanix.com header.a=rsa-sha256\n header.s=proofpoint20171006 header.b=YsiK1ruw;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nutanix.com header.i=@nutanix.com header.a=rsa-sha256\n header.s=selector1 header.b=HEWS1fhM;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gFzc665w4z1y5L\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 14 May 2026 02:36:06 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wNCXn-0003Kw-6A; Wed, 13 May 2026 12:34:47 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <shaju.abraham@nutanix.com>)\n id 1wNCXe-0003JV-Av; Wed, 13 May 2026 12:34:39 -0400", "from mx0b-002c1b01.pphosted.com ([148.163.155.12])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <shaju.abraham@nutanix.com>)\n id 1wNCXc-0000go-8G; Wed, 13 May 2026 12:34:38 -0400", "from pps.filterd (m0127843.ppops.net [127.0.0.1])\n by mx0b-002c1b01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 64DGKfem738992; Wed, 13 May 2026 09:34:15 -0700", "from ch1pr05cu001.outbound.protection.outlook.com\n (mail-northcentralusazon11020086.outbound.protection.outlook.com\n [52.101.193.86])\n by mx0b-002c1b01.pphosted.com (PPS) with ESMTPS id 4e3nvap78e-1\n (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT);\n Wed, 13 May 2026 09:34:15 -0700 (PDT)", "from PH7PR02MB10160.namprd02.prod.outlook.com\n (2603:10b6:510:2e7::19) by CH3PR02MB9564.namprd02.prod.outlook.com\n (2603:10b6:610:120::21) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.23; Wed, 13 May\n 2026 16:34:13 +0000", "from PH7PR02MB10160.namprd02.prod.outlook.com\n ([fe80::4ed7:5c74:48e0:ff23]) by PH7PR02MB10160.namprd02.prod.outlook.com\n ([fe80::4ed7:5c74:48e0:ff23%7]) with mapi id 15.20.9891.021; Wed, 13 May 2026\n 16:34:13 +0000" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nutanix.com; h=\n cc:content-transfer-encoding:content-type:date:from:in-reply-to\n :message-id:mime-version:references:subject:to; s=\n proofpoint20171006; bh=MNinJibHwoWXGXhfMhUkYF30JTL8RYpn8K2IodxM6\n /Y=; b=YsiK1ruwfSpXNEoo5M0uKcNVZI7+UeAhhFEc1K1JWql2ZGPfQy2jKk1ZN\n YhlHj6g1hfCuBY2X/dOqRFaDjcCUlr2xVx0op5KGSTRBr6Nb6/0wEg3Hw6yypw/P\n SkgnILZ8Q1EjPNYpHsBnyF32wj2Xu2tiZsSwRngXt7ApQBDEbKpemH8wO9z20Ji3\n eD9OxLZOUzJhF2Z89qoiJ2Fj3uAAqu03eGyodfUTN0QQOObtx+VFERIumLS3flcd\n 32cijh0AWOucEqHJyFWwZc9paoJpr5zs2qsDXdpNjfy7r9BpbhO8mdmdat2eKPCL\n +SHdQFoxMaD8256iQKWDyN7ghwK+A==", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nutanix.com;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=MNinJibHwoWXGXhfMhUkYF30JTL8RYpn8K2IodxM6/Y=;\n b=HEWS1fhMMy5ZUIeUSheSh+z66rA7qSEXtVpinn/soru5ba7gEx6O/pyPeMCtcYgnb7UifP4YGQj8rrKP84lsUYDgosQqyUdaCv/ybj3iTczV0Mj7h1qtPhlmNLVXpW6toqrjGEZA8lKrBd2E6j+7T3J306Jg9YfZC56Vrf+GYrruI8+fFomWIJt0YTOQpc0AZiwF8ykgE39cr3avlDfFlYDCf3cqoR2n13FN71u715PyfxWFBarCFsozGu6tVwHARJrvaElbkTpSIVEvsEhlmzJTkZ5GAp9Xb29nJ23oJBmf1Uw4s90Rg5Z5CPE24YuLsndWiycTLqhA6zh4o4Kf9g==" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=g8+xhwOQe+ToKw+T1c9IPkL3sJemGRpYXsAoSzTu4ghUe8nlEOJzx6Pmqx96+WYPxVvtrodWbYck+xlbBYqz53zF7O+V4sK2cdZrfNcyzQvPtNRLAq9ZXlhQO5rfiUc3+HzSN1JQbX2cXjkDqYqVePDh75HzuvJATNQO123R4FB4ynqKQD1U2MogeCyShDigcSm0F5SeXsdovsa3QNRA7YwId0Nt+I/M/FGDuFUH9BnQCuU9uKFvhfiQiiHOHMZnbp5hnojS/L3ZwwrX2+D4HF+odRQF2rizjYYWbgZjco2CAP3k6GNha5caOzGauL0ZAo+4fWOZ+V4bzDK3Hu9gJQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=MNinJibHwoWXGXhfMhUkYF30JTL8RYpn8K2IodxM6/Y=;\n b=XydovDjkgMxOcKhfQYGCWl/n1eEd6X+CChLHa0rwvJVz4c0BgzhHrzndI5flG2FkNNOLWRyvQUkjgixpz4gRZPqJ6eiAhCzqnMy7k1LnwT3W+7zpSwgZM2YHqJWnvQoqcsRC1mec4acyKmlWW9eWOLCUqyl2/1APLm0AO1lSiOStnr5fOXCmneC6aQqdyjhg6BWxLdksRhRPcev0BkT0IP/DfLYdNiN1X20kK7gKZEWgBU04NAkRlTB2SGSIw+e+zvU710T71Pi0ZtlVI2w7emMI8Y9qlo0+i3aEh+Ychg46OIwOh3nNqKC+wX+vQvMihbfRUYF/fOEUsRg4orqQNA==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nutanix.com; dmarc=pass action=none header.from=nutanix.com;\n dkim=pass header.d=nutanix.com; arc=none", "From": "Shaju Abraham <shaju.abraham@nutanix.com>", "To": "eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org,\n kvmarm@lists.linux.dev, peter.maydell@linaro.org,\n richard.henderson@linaro.org, cohuck@redhat.com, sebott@redhat.com,\n skolothumtho@nvidia.com, philmd@linaro.org", "Cc": "maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com,\n prerna.saxena@nutanix.com, jon@nutanix.com, jond@nutanix.com,\n Shaju Abraham <shaju.abraham@nutanix.com>,\n Khushit Shah <khushit.shah@nutanix.com>", "Subject": "[RFC PATCH v1 04/13] target/arm: named_cpu_model: generate tables for\n Arm64 ID registers and fields", "Date": "Wed, 13 May 2026 16:33:47 +0000", "Message-ID": "<20260513163356.3033159-5-shaju.abraham@nutanix.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260513163356.3033159-1-shaju.abraham@nutanix.com>", "References": "<20260513163356.3033159-1-shaju.abraham@nutanix.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "CY5PR10CA0003.namprd10.prod.outlook.com\n (2603:10b6:930:1c::30) To PH7PR02MB10160.namprd02.prod.outlook.com\n (2603:10b6:510:2e7::19)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "PH7PR02MB10160:EE_|CH3PR02MB9564:EE_", "X-MS-Office365-Filtering-Correlation-Id": "824193c0-f4fa-4bb4-c23a-08deb10d77be", "x-proofpoint-crosstenant": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|7416014|376014|366016|1800799024|18002099003|22082099003|921020|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n 0Cz5yeqIey/hBlFuQiwZeBmHgRuzOfMEvYTsvaQJYPnjR4S6Ya44+pOCNsxFkM23kH0Gx/k0Oq+R8jo1fsQehY9S8XSpdZMzlWYD9dvfkZ0Ng8RZauhwxlQEed+bZ7tGLHKXht+KczQIgyXUmNgQOjzSVInREYgsSLpuBRU6ey7nYbh5Kvx075NjWalNGlyCwTRqv0bcJAX1WOzHb1mqgIkmVFAf+eLGRRqk92PtJjUWJClks8b+eoVHGNqfkeaRxfDvTnlxU73wjRzeHPvnGwLWhewMJTDt7fcWybKgaAkGZtDFlXyPcBgMfEVQY4YJe1qQn4eBySYulbcZjSaMQq907TXc9wMfUgg+6WxDywTXelz1jtvCHC/ro3mvJHKoP8iUvna3+MkZAHwPELKyYX87knEX2kSPVlry8JtPwvSH20Zz/UC385Tx0LmS82+LO1tRS7EGH3HmxkiehAmWmWNwssJlmSPtf2y+cYe0HYO5ty2DJoxHO9kPS4tVInM1AFKpS/QRYE0pYVXxw70dddwoeN17TCkkZI3LRS+h1yfwOyXdumS5KBl0GRP53pXR4uaqCKyUSMpV47oF5AXQ8BhJGAiw2cnyYqtolzCoHeZztJ0TSy5OAMf/pVvMLRWMYWGAqZveEWRf98W67sMc+7lCnUcoAx4vH4/uy2aJLcvgS3YX2feWAkxeVKXuj4KNLGjw22U5xH7pTbQRpCoMv1hdQgFuNLjBKC9oHT1R5Ko=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:PH7PR02MB10160.namprd02.prod.outlook.com; PTR:;\n CAT:NONE;\n SFS:(13230040)(7416014)(376014)(366016)(1800799024)(18002099003)(22082099003)(921020)(56012099003);\n DIR:OUT; SFP:1102;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n 7stOUQ1bTMcu+8GA4KD/ii0Nx5GLUiii+xIOHyrFNItNDSbuKuHk/qPlcv3G1ypWx9acuWkOXR34aDOPTG0fTvkl4CWwFsrdTBku+U6wcOt+q6ruGDqGf+LazsJ9VzTNKLZGcSIqAB/FSEVQrUACVVIzQrz3f3HkZnvn5IXHNBVwLDqpgMeMayygMtWPyWVAliOw2xb1tKO65mfODbHDRg7/ZO3v9Ich/4hdUG5mJyPx12GA1yDoFWdDl8K78+klIygDQAq6j47WUC1PqHmQAYuiSBOiMn/82qrOkk0gOg+vD/P8qMZcGE7eN2jgKAmdfTEXHRNfZYZ39dBYHDAnlrIQ7SgJIcflIt58+NMKO2wl2ZUCd6kOE/vKPe1gZdlFfpm0tjjtcYJJsx8LPuvcx7fyZSOJBEqo2K8jlHx03RUWbLwL6LJpGdqoPsbvgwaj73eAUCweJ3rGs1FZBOEjk0zCn6P7S+5mb/OXUHIzK6leykGiiChKf95D6T4V+Dpek8s/lAehkr8IhQ9CiOStJfPKDti3ISM5Fg0ZwBtTyVk8+VFmuOBQfpn99QeD3aKtRGGcwB0eotVs281/nCCm4wqy+P9jPsOGznkg3DVHYjB3r4WJyB8PlClzAUlwpMV6pfuY3XKWY5z8bGbovZP/zmwL5jUWjiP8quyjpanhSYPqfgTVJN0qVxzOR1ZYMu7m/KqRUzri2cKX1/XIn6h1596gSDtiXiVouBVv2YTvIr2JMnNNyirjoymZleXCXBNdK2P6A+JViHiXrCnOCBNOI2gjoJERVBkDwfvUMVKL81CcIPjxWDjiO7vPBVRNHy4ZXA7G3FY9LxusOsziEIC8GA9CtB+7dNzZy1dq0vw48oYt6fiG9UkmIbDK0/S9shuXY5DlkX6lpaYOwMaLJJVHavQ/g+X/nnBJv37RjGQuarmY7Cewza6ZGd9aVJyWHAwb8clVGW1f0+ELf6MNokPPMIKTfem3nEE2QSljHxLAwf8qRnZXGTe7qQLJxbaBfX+IRBDkqFVL6MLDrvFNxstHauIBMFblJ5GFj4pnc0xCF1SLM5c9InemYYbUlL0mvJnCJLaCPzDEmMJ+1wHZ0+G/0sFS3O6Pco3trzMln1Ll0k6B/n4wGSPTZxwzvOTfPla9NpU9qQhULszoULgn9xRU2oa2/q1BjKhT8BMAjVQQ+iX6xT34Hwrdt1BlAWWAc0t+ZSWxMEx7kMyYR+K+ydzAbcXwLuZwoSjMWXJbrsbxGhvCdEN+YCd9SZRbDdx53ZERtaAf4RfX73f+YaczSbyZqD7RshB48a6l304Rnh7dmc3T0U4HoQgfERkpS5GduX8xBBtSG4dG3v+9Y4zXGEgigDRar45IKngd1sQtNmNnXPuIGlrVTRSdAL8m5mK7XOuRAnTlyLfQwAadgJH7bQPJYR70FHJkWQha8HzafBRP2PhESU1QkNeG945iE8QKcWVXUunzjsdo9vE8xXaAAJovWfkFxcgOwrDbm4rrRGz5f/oeBozo82KIJl8OV4RsxgWi5yKu3s5GmpLUWB5FHp1+I44LPeJSEmvhvHDdE3Em2UgLq3tmu7U3Lk5HnzhNjLG+bTgjBxMWXecQvRdOPXpNcgmWknVxIf5O8LNHIWZ0isVRNtFMCFbMQY5yXJULqCznh53BZKNMZi5nlXwg6JKHERNut8m9dqIjIcgKntT0xRARtWsZjJQ8Qhda8Nget6+JhBxKyNxmbIFN0AmlA/7jGosqEcCnM7UNKcFHqAc0WdE=", "X-Exchange-RoutingPolicyChecked": "\n DHO3kEKaU7tbs9mtx2F6K0XYJPi8ewHxxUqWCGhxYs8OPrQmQbOh6I2qdOGTRANbVp7pF/F7XqqrGE2aqL8WjbvnxCdKAB8akEATAKzoA7UC9i4t6pnfvWMnSOPmx/sA/S8PiT4cVI3Niui78PU6MTAcreaN+TfxbXnPHffcO59jIvtTmDi5vYTv2dcrnWgTwc/OYKE5v5OSCqxujGjz1owdM938TknqCf3HayWxzEeMaUqSz1AXwOmsWccNS7iYDQ63kxZAWAVZ4/tKyoNSK+pcxbK4YNTqdw92pjIPgDtBUbEZNfFfCqXmgOuUnQQGNZgz5MH8k0XtJoafjms5Eg==", "X-OriginatorOrg": "nutanix.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 824193c0-f4fa-4bb4-c23a-08deb10d77be", "X-MS-Exchange-CrossTenant-AuthSource": "PH7PR02MB10160.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "13 May 2026 16:34:13.6572 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "bb047546-786f-4de1-bd75-24e5b6f79043", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n LPXEZWtZ/lseOWXsJY9O1x+Ife5F2dqswdbwicgBVzz1RkKCAD7jRzK4InDBZ4WRCWuBLCtQ+Dede8XDoQgE0SCZXZa+mwsO/mp9ggnIHSA=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR02MB9564", "X-Proofpoint-GUID": "WcYQlPoPtYk2FBTq5u6Kvj31mw5Tn9QL", "X-Proofpoint-ORIG-GUID": "WcYQlPoPtYk2FBTq5u6Kvj31mw5Tn9QL", "X-Authority-Analysis": "v=2.4 cv=apaCzyZV c=1 sm=1 tr=0 ts=6a04a807 cx=c_pps\n a=Ju9Zey7g8YyQpP5MZaDBLg==:117 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19\n a=z/mQ4Ysz8XfWz/Q5cLBRGdckG28=:19 a=lCpzRmAYbLLaTzLvsPZ7Mbvzbb8=:19\n a=xqWC_Br6kY4A:10 a=NGcC8JguVDcA:10 a=0kUYKlekyDsA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=VofLwUrZ8Iiv6rRUPXIb:22 a=dEe9Ve2bX-KnNSUMM2s9:22\n a=64Cc0HZtAAAA:8 a=PaGUs5NhgPxOKxUa52MA:9", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNTEzMDE2OCBTYWx0ZWRfX3em7pHyv0TDu\n xkpRGfWT4Bmo8HOV2hVKiO5x+9Oa40JB1M94DAPyVuWO9CeTy2Rn7L8IRZ48a5lBMmFYHDcQ8Tv\n DYuYlNoGY14qdgn92cz7Vc5NBUvqxECn+8flGBeUpqm+TGMQHm6dMTeX9q4lbG5nbRFSFSkaUI8\n pYXRF6FQ6V3o+SBpISnmzokg//+zAbdvSzGZaL6vlhP3RaMo+QQdofE3QBA8qOfPrOOuo77vCqD\n g2DYVGwHwUAK4066kTvVM+nVrQrTLVdh77rBjWFVyvT4jui39wLVQC3Rm2ptHg15M3cLMCk5zbs\n DNuEeZwaQMOrklhThpbW69diO9kUaEOpw/e8+VgNrgvPQOTR3V9wZJIFYLBq5H8+A27BLKnrIpj\n Fz0LqdFT85BfsUA5Lv2XMuN1+d8377zONqtsLOseEbTLwtNR4cPJTjkCInnxmrbMbKme7pqGhxt\n 9euaR1SCz/UN3E05BJg==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-05-13_01,2026-05-13_01,2025-10-01_01", "X-Proofpoint-Spam-Reason": "safe", "Received-SPF": "pass client-ip=148.163.155.12;\n envelope-from=shaju.abraham@nutanix.com; helo=mx0b-002c1b01.pphosted.com", "X-Spam_score_int": "-31", "X-Spam_score": "-3.2", "X-Spam_bar": "---", "X-Spam_report": "(-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Include cpu-idregs.h.inc multiple times with different definitions for the\nX-macros. This will generate tables for all Arm64 ID registers and their\nfields. Additionally, initialize the tables with all architecturally defined\nvalues. These tables will be consumed by the property layer in future\npatches.\n\nCo-authored-by: Khushit Shah <khushit.shah@nutanix.com>\nSigned-off-by: Shaju Abraham <shaju.abraham@nutanix.com>\n---\n target/arm/cpu-idregs.c | 124 ++++++++++++++++++++++++++++++++++++++++\n target/arm/cpu-idregs.h | 81 ++++++++++++++++++++++++++\n target/arm/meson.build | 1 +\n 3 files changed, 206 insertions(+)\n create mode 100644 target/arm/cpu-idregs.c", "diff": "diff --git a/target/arm/cpu-idregs.c b/target/arm/cpu-idregs.c\nnew file mode 100644\nindex 0000000000..8fced7d8d7\n--- /dev/null\n+++ b/target/arm/cpu-idregs.c\n@@ -0,0 +1,124 @@\n+/*\n+ * ARM ID register field table.\n+ *\n+ * Builds the per-id-register field descriptor arrays and the global\n+ * arm_idregs[] table.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+#include \"qemu/osdep.h\"\n+#include \"qemu/error-report.h\"\n+#include \"qapi/error.h\"\n+#include \"cpu.h\"\n+#include \"cpu-idregs.h\"\n+\n+/* generate an array of architecturely defined values for bitfields\n+ * in arch-value format*/\n+#define IDREG_START(reg)\n+#define IDREG_END(reg)\n+#define IDREG_FIELD_START(reg, field, shift, length, safe, defval) \\\n+ static const ArmIdRegArchVal reg##_##field##_arch_vals[] = {\n+#define IDREG_FIELD_ARCH_VAL(v, n) { (v), (n) },\n+#define IDREG_FIELD_ARCH_VAL_ANY { 0xffffffffUL, NULL },\n+#define IDREG_FIELD_END(reg, field) \\\n+ };\n+#include \"cpu-idregs.h.inc\"\n+#undef IDREG_START\n+#undef IDREG_END\n+#undef IDREG_FIELD_START\n+#undef IDREG_FIELD_ARCH_VAL\n+#undef IDREG_FIELD_ARCH_VAL_ANY\n+#undef IDREG_FIELD_END\n+/* generate an array of per-register ArmIdRegField[] descriptors */\n+#define IDREG_FIELD_ARCH_VAL(v, n)\n+#define IDREG_FIELD_ARCH_VAL_ANY\n+#define IDREG_FIELD_END(reg, field)\n+#define IDREG_START(reg) \\\n+ static ArmIdRegField reg##_fields[] = {\n+\n+#define IDREG_END(reg) \\\n+ };\n+\n+#define IDREG_FIELD_START(reg, field, _shift, _length, safe, defval) \\\n+ { \\\n+ .name = #field, \\\n+ .shift = (_shift), \\\n+ .length = (_length), \\\n+ .safe_rule = IDREG_SAFE_##safe, \\\n+ .default_val = (defval), \\\n+ .arch_vals = (ArmIdRegArchVal *)reg##_##field##_arch_vals, \\\n+ .arch_vals_count = ARRAY_SIZE(reg##_##field##_arch_vals), \\\n+ },\n+#include \"cpu-idregs.h.inc\"\n+#undef IDREG_START\n+#undef IDREG_END\n+#undef IDREG_FIELD_START\n+#undef IDREG_FIELD_ARCH_VAL\n+#undef IDREG_FIELD_END\n+\n+/* generate an array of top level ID registers */\n+#define IDREG_END(reg)\n+#define IDREG_FIELD_START(reg, field, shift, length, safe, defval)\n+#define IDREG_FIELD_ARCH_VAL(v, n)\n+#define IDREG_FIELD_ARCH_VAL_ANY\n+#define IDREG_FIELD_END(reg, field)\n+\n+#define IDREG_START(reg) \\\n+ [reg##_IDX] = { \\\n+ .name = #reg, \\\n+ .fields = reg##_fields, \\\n+ .fields_count = ARRAY_SIZE(reg##_fields), \\\n+ },\n+\n+ArmIdReg arm_idregs[NUM_ID_IDX] = {\n+#include \"cpu-idregs.h.inc\"\n+};\n+#undef IDREG_START\n+#undef IDREG_END\n+#undef IDREG_FIELD_START\n+#undef IDREG_FIELD_ARCH_VAL\n+#undef IDREG_FIELD_END\n+\n+\n+/* Per-register field position enums (0..N-1 inside each register). */\n+#define IDREG_START(reg) enum {\n+#define IDREG_END(reg) reg##_FIELD_POS__MAX };\n+#define IDREG_FIELD_START(reg, field, shift, length, safe, defval) \\\n+ reg##_FIELD_POS_##field,\n+#define IDREG_FIELD_ARCH_VAL(v, n)\n+#define IDREG_FIELD_ARCH_VAL_ANY\n+#define IDREG_FIELD_END(reg, field)\n+\n+#include \"cpu-idregs.h.inc\"\n+\n+#undef IDREG_FIELD_END\n+#undef IDREG_FIELD_ARCH_VAL_ANY\n+#undef IDREG_FIELD_ARCH_VAL\n+#undef IDREG_FIELD_START\n+#undef IDREG_END\n+#undef IDREG_START\n+\n+/* Flat ArmFieldIdx -> {reg, field slot, shift, length}. */\n+#define IDREG_START(reg)\n+#define IDREG_END(reg)\n+#define IDREG_FIELD_START(reg, field, _shift, _length, safe, defval) \\\n+ [ARM_FIELD_##reg##_##field] = { \\\n+ .reg_idx = reg##_IDX, \\\n+ .field_idx = reg##_FIELD_POS_##field, \\\n+ .shift = (_shift), \\\n+ .length = (_length), \\\n+ },\n+#define IDREG_FIELD_ARCH_VAL(v, n)\n+#define IDREG_FIELD_ARCH_VAL_ANY\n+#define IDREG_FIELD_END(reg, field)\n+\n+const ArmIdRegFieldLoc arm_field_locs[ARM_FIELD__MAX] = {\n+#include \"cpu-idregs.h.inc\"\n+};\n+\n+#undef IDREG_FIELD_END\n+#undef IDREG_FIELD_ARCH_VAL_ANY\n+#undef IDREG_FIELD_ARCH_VAL\n+#undef IDREG_FIELD_START\n+#undef IDREG_END\n+#undef IDREG_START\ndiff --git a/target/arm/cpu-idregs.h b/target/arm/cpu-idregs.h\nindex 403190cbd7..4e568e877d 100644\n--- a/target/arm/cpu-idregs.h\n+++ b/target/arm/cpu-idregs.h\n@@ -7,6 +7,8 @@\n #ifndef CPU_IDREGS_H\n #define CPU_IDREGS_H\n \n+#include \"cpu-sysregs.h\"\n+\n typedef enum ArmIdRegSafeRule {\n IDREG_SAFE_LOWER,\n IDREG_SAFE_HIGHER,\n@@ -37,5 +39,84 @@ typedef struct ArmIdReg {\n uint32_t fields_count;\n } ArmIdReg;\n \n+/* Map short register names to canonical _EL1/_EL0 IDX values */\n+#define ID_AA64ISAR0_IDX ID_AA64ISAR0_EL1_IDX\n+#define ID_AA64ISAR1_IDX ID_AA64ISAR1_EL1_IDX\n+#define ID_AA64ISAR2_IDX ID_AA64ISAR2_EL1_IDX\n+#define ID_AA64ISAR3_IDX ID_AA64ISAR3_EL1_IDX\n+#define ID_AA64PFR0_IDX ID_AA64PFR0_EL1_IDX\n+#define ID_AA64PFR1_IDX ID_AA64PFR1_EL1_IDX\n+#define ID_AA64PFR2_IDX ID_AA64PFR2_EL1_IDX\n+#define ID_AA64MMFR0_IDX ID_AA64MMFR0_EL1_IDX\n+#define ID_AA64MMFR1_IDX ID_AA64MMFR1_EL1_IDX\n+#define ID_AA64MMFR2_IDX ID_AA64MMFR2_EL1_IDX\n+#define ID_AA64MMFR3_IDX ID_AA64MMFR3_EL1_IDX\n+#define ID_AA64MMFR4_IDX ID_AA64MMFR4_EL1_IDX\n+#define ID_AA64DFR0_IDX ID_AA64DFR0_EL1_IDX\n+#define ID_AA64DFR1_IDX ID_AA64DFR1_EL1_IDX\n+#define ID_AA64ZFR0_IDX ID_AA64ZFR0_EL1_IDX\n+#define ID_AA64SMFR0_IDX ID_AA64SMFR0_EL1_IDX\n+#define ID_AA64AFR0_IDX ID_AA64AFR0_EL1_IDX\n+#define ID_AA64AFR1_IDX ID_AA64AFR1_EL1_IDX\n+#define ID_AA64FPFR0_IDX ID_AA64FPFR0_EL1_IDX\n+#define ID_PFR0_IDX ID_PFR0_EL1_IDX\n+#define ID_PFR1_IDX ID_PFR1_EL1_IDX\n+#define ID_PFR2_IDX ID_PFR2_EL1_IDX\n+#define ID_DFR0_IDX ID_DFR0_EL1_IDX\n+#define ID_DFR1_IDX ID_DFR1_EL1_IDX\n+#define ID_AFR0_IDX ID_AFR0_EL1_IDX\n+#define ID_MMFR0_IDX ID_MMFR0_EL1_IDX\n+#define ID_MMFR1_IDX ID_MMFR1_EL1_IDX\n+#define ID_MMFR2_IDX ID_MMFR2_EL1_IDX\n+#define ID_MMFR3_IDX ID_MMFR3_EL1_IDX\n+#define ID_MMFR4_IDX ID_MMFR4_EL1_IDX\n+#define ID_MMFR5_IDX ID_MMFR5_EL1_IDX\n+#define ID_ISAR0_IDX ID_ISAR0_EL1_IDX\n+#define ID_ISAR1_IDX ID_ISAR1_EL1_IDX\n+#define ID_ISAR2_IDX ID_ISAR2_EL1_IDX\n+#define ID_ISAR3_IDX ID_ISAR3_EL1_IDX\n+#define ID_ISAR4_IDX ID_ISAR4_EL1_IDX\n+#define ID_ISAR5_IDX ID_ISAR5_EL1_IDX\n+#define ID_ISAR6_IDX ID_ISAR6_EL1_IDX\n+#define MVFR0_IDX MVFR0_EL1_IDX\n+#define MVFR1_IDX MVFR1_EL1_IDX\n+#define MVFR2_IDX MVFR2_EL1_IDX\n+#define MIDR_IDX MIDR_EL1_IDX\n+#define REVIDR_IDX REVIDR_EL1_IDX\n+#define AIDR_IDX AIDR_EL1_IDX\n+#define DCZID_IDX DCZID_EL0_IDX\n+\n+/* ArmFieldIdx: per-field enum generated from cpu-idregs.h.inc */\n+#define IDREG_START(reg)\n+#define IDREG_END(reg)\n+#define IDREG_FIELD_START(reg, field, shift, length, safe, defval) \\\n+ ARM_FIELD_##reg##_##field,\n+#define IDREG_FIELD_ARCH_VAL(v, n)\n+#define IDREG_FIELD_ARCH_VAL_ANY\n+#define IDREG_FIELD_END(reg, field)\n+typedef enum ArmFieldIdx {\n+#include \"cpu-idregs.h.inc\"\n+ ARM_FIELD__MAX,\n+} ArmFieldIdx;\n+#undef IDREG_FIELD_END\n+#undef IDREG_FIELD_ARCH_VAL_ANY\n+#undef IDREG_FIELD_ARCH_VAL\n+#undef IDREG_FIELD_START\n+#undef IDREG_END\n+#undef IDREG_START\n+\n+typedef struct ArmIdRegFieldLoc {\n+ ARMIDRegisterIdx reg_idx;\n+ uint16_t field_idx;\n+ uint8_t shift;\n+ uint8_t length;\n+} ArmIdRegFieldLoc;\n+extern const ArmIdRegFieldLoc arm_field_locs[ARM_FIELD__MAX];\n+#define ARM_FIELD_REG(idx) (arm_field_locs[(idx)].reg_idx)\n+#define ARM_FIELD_REG_FIELD(idx) (arm_field_locs[(idx)].field_idx)\n+#define ARM_FIELD_SHIFT(idx) (arm_field_locs[(idx)].shift)\n+#define ARM_FIELD_LENGTH(idx) (arm_field_locs[(idx)].length)\n+#define ARM_FIELD_IDX(reg, field) ARM_FIELD_##reg##_##field\n \n+extern ArmIdReg arm_idregs[NUM_ID_IDX];\n #endif /* CPU_IDREGS_H */\ndiff --git a/target/arm/meson.build b/target/arm/meson.build\nindex 4723f9f170..64d1ec63ab 100644\n--- a/target/arm/meson.build\n+++ b/target/arm/meson.build\n@@ -19,6 +19,7 @@ arm_common_ss.add(files(\n \n arm_common_system_ss.add(files(\n 'arm-qmp-cmds.c',\n+ 'cpu-idregs.c',\n ))\n arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'))\n arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c'))\n", "prefixes": [ "RFC", "v1", "04/13" ] }