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GET /api/patches/2237939/?format=api
{ "id": 2237939, "url": "http://patchwork.ozlabs.org/api/patches/2237939/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260513163356.3033159-2-shaju.abraham@nutanix.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260513163356.3033159-2-shaju.abraham@nutanix.com>", "list_archive_url": null, "date": "2026-05-13T16:33:44", "name": "[RFC,v1,01/13] target/arm: named_cpu_model: define containers for ID registers and fields", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e588bb76fae56c567b3d7aea67bd728d84f6a016", "submitter": { "id": 77003, "url": "http://patchwork.ozlabs.org/api/people/77003/?format=api", "name": "Shaju Abraham", "email": "shaju.abraham@nutanix.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260513163356.3033159-2-shaju.abraham@nutanix.com/mbox/", "series": [ { "id": 504187, "url": "http://patchwork.ozlabs.org/api/series/504187/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=504187", "date": "2026-05-13T16:33:48", "name": "named CPU models for ARM64 on KVM", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/504187/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2237939/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2237939/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nutanix.com header.i=@nutanix.com header.a=rsa-sha256\n header.s=proofpoint20171006 header.b=Rxt0kW6b;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nutanix.com header.i=@nutanix.com header.a=rsa-sha256\n header.s=selector1 header.b=H2CQtvV8;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mx0b-002c1b01.pphosted.com", "X-Spam_score_int": "-31", "X-Spam_score": "-3.2", "X-Spam_bar": "---", "X-Spam_report": "(-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Define data structures for mapping the ARM ID registers and ID register\nfields.\n\nCo-authored-by: Khushit Shah <khushit.shah@nutanix.com>\nSigned-off-by: Shaju Abraham <shaju.abraham@nutanix.com>\n---\n target/arm/cpu-idregs.h | 41 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 41 insertions(+)\n create mode 100644 target/arm/cpu-idregs.h", "diff": "diff --git a/target/arm/cpu-idregs.h b/target/arm/cpu-idregs.h\nnew file mode 100644\nindex 0000000000..403190cbd7\n--- /dev/null\n+++ b/target/arm/cpu-idregs.h\n@@ -0,0 +1,41 @@\n+/*\n+ * ARM ID register field table -- shared declarations.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef CPU_IDREGS_H\n+#define CPU_IDREGS_H\n+\n+typedef enum ArmIdRegSafeRule {\n+ IDREG_SAFE_LOWER,\n+ IDREG_SAFE_HIGHER,\n+ IDREG_SAFE_HIGHER_OR_ZERO,\n+ IDREG_SAFE_SIGNED_LOWER,\n+ IDREG_SAFE_EXACT,\n+ IDREG_SAFE_ANY,\n+} ArmIdRegSafeRule;\n+\n+typedef struct ArmIdRegArchVal {\n+ uint64_t value;\n+ const char *name;\n+} ArmIdRegArchVal;\n+\n+typedef struct ArmIdRegField {\n+ const char *name;\n+ uint32_t shift;\n+ uint32_t length;\n+ ArmIdRegSafeRule safe_rule;\n+ uint64_t default_val;\n+ ArmIdRegArchVal *arch_vals;\n+ uint32_t arch_vals_count;\n+} ArmIdRegField;\n+\n+typedef struct ArmIdReg {\n+ const char *name;\n+ struct ArmIdRegField *fields;\n+ uint32_t fields_count;\n+} ArmIdReg;\n+\n+\n+#endif /* CPU_IDREGS_H */\n", "prefixes": [ "RFC", "v1", "01/13" ] }