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GET /api/patches/2232257/?format=api
{ "id": 2232257, "url": "http://patchwork.ozlabs.org/api/patches/2232257/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/1ea679dc-9e6f-4904-8455-ed688186d2bd@oss.qualcomm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1ea679dc-9e6f-4904-8455-ed688186d2bd@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-05-04T04:18:34", "name": "[V2,to-be-committed,RISC-V,PR,rtl-optimization/124766] Simplify x + y == y into x == 0", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3342786a0e51697505a1b3b0f8076c30853398d4", "submitter": { "id": 92310, "url": "http://patchwork.ozlabs.org/api/people/92310/?format=api", "name": "Jeffrey Law", "email": "jeffrey.law@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/1ea679dc-9e6f-4904-8455-ed688186d2bd@oss.qualcomm.com/mbox/", "series": [ { "id": 502611, "url": "http://patchwork.ozlabs.org/api/series/502611/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502611", "date": "2026-05-04T04:18:34", "name": "[V2,to-be-committed,RISC-V,PR,rtl-optimization/124766] Simplify x + y == y into x == 0", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502611/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232257/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232257/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=fQzL0Mi4;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=OuUeWA3Z;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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boundary=\"------------AoOpgg6xLVHQghE0Op2NOmDW\"", "Message-ID": "<1ea679dc-9e6f-4904-8455-ed688186d2bd@oss.qualcomm.com>", "Date": "Sun, 3 May 2026 22:18:34 -0600", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "Content-Language": "en-US", "From": "Jeffrey Law <jeffrey.law@oss.qualcomm.com>", "Subject": "[V2][to-be-committed][RISC-V][PR rtl-optimization/124766] Simplify x\n + y == y into x == 0", "To": "'GCC Patches' <gcc-patches@gcc.gnu.org>", "X-Proofpoint-ORIG-GUID": "6q7rC3LS91AnQOFEYq7Ge7DSSO8ZpM99", "X-Authority-Analysis": "v=2.4 cv=QqxuG1yd c=1 sm=1 tr=0 ts=69f81e1e cx=c_pps\n a=JYo30EpNSr/tUYqK9jHPoA==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=Ys_nlTsfSoNbGBeoM8gA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=F22s-0fX0AYkUdlLRoYA:9 a=B2y7HmGcmWMA:10 a=Fk4IpSoW4aLDllm1B1p-:22", "X-Proofpoint-GUID": "6q7rC3LS91AnQOFEYq7Ge7DSSO8ZpM99", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNTA0MDA0MiBTYWx0ZWRfX3hKs8zrFc0Cn\n 5fue8j/qsUtvifks2TSaO4n1NA9rO0LDrGe2aNsuhkiIsWiEt3H2uWZsQNJcNQQc1fnKOVyT0hT\n iUhC2tYGobxJNH1cPUJ0fjKCaIEKasAyrozg3rZzYxoywlM/lrhaCIPn4qjStW4mmvpkwf2ahjO\n WQIE8AIcgSHywYgRW51g+9WijNkd9ziRjeHDe7MU8tgHkr+b4/xfd/ft6N/ig+dmsAbiuown8wf\n n/sDqd9P4UUrowMtqndbz/85s0/5IBNWTa2ibMExo04TNQEG/7FwyS3AGSeODnVLUjWiTJJ45x7\n k5CqPZAaK6jGct5ZWNQznJcnO0bs/CjyhC70nZtaOB496/3Kx1IDfCzdv5vzCZNKg5Yat+IekSB\n aW7sOXxEg6XfdNSkz2L/cMVT6HxDOYV7wpE7LWCRbFuWzFutyZIZRSrn/Z+ZeY1VQnhpcH4t9HV\n zRDWBJxbiOIiutoby5A==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-05-04_02,2026-04-30_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 bulkscore=0 suspectscore=0 clxscore=1015 phishscore=0\n priorityscore=1501 malwarescore=0 spamscore=0 adultscore=0 lowpriorityscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605040042", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "So Richard S. noticed 3 issues in the V1 patch. Specifically it should \nhave been using rtx_equal_p rather than just testing pointer equality. \nThat's not a correctness issue, but could potentially allow the pattern \nto apply more often.\n\nSecond we should be checking for !side_effects_p on the operand we're \ndropping. Easy to fix.\n\nFinally there was a const0_rtx use that should have been CONST0_RTX. \nGiven how often I mention that one to others, I'm embarrassed I missed it.\n\nBootstrapped on x86 and retested on the various embedded platforms. \nBootstraps on riscv platforms, aarch64, armv7 and sh4eb are in flight.\n\n--\n\nSo this is derived from S_regmatch in spec2017, so fairly hot.\n\n\n\nlong\nfrob (unsigned short *y, long z)\n{\n long ret = (*y << 2) + z;\n if (ret != z)\n return 0;\n return ret;\n}\n\nIt generates this code on riscv:\n\n\n lhu a5,0(a0)\n sh2add a5,a5,a1\n sub a1,a1,a5\n czero.nez a0,a5,a1\n ret\n\nThat's not bad, but the sh2add and sub are not actually needed. This may \nlook familiar to a case Daniel was recently discussing, the major \ndifference are the types of the function args which I got wrong the \nfirst time I reduced this case.\n\nczero instructions check their condition for zero/nonzero status. So we \njust need to know if a1 has a zero/nonzero value at the czero \ninstruction. So working backwards\n\na1 = a1 - a5 // sub instruction\na1 = a1 - ((a5 << 2) + a1) // substitute from sh2add\na1 = a5 << 2 // a1 terms cancel out\n\nSo we just need the nonzero state of a5 << 2. Now since a5 was set by \nthe lhu instruction, the upper 48 bits are already known zero, so \ncritically we know the upper 2 bits are zero. Meaning that we can just \ntest a5 as set by the lhu instruction for zero/nonzero. The net is we \ncan generate this code instead:\n\n lhu a0,0(a0)\n czero.nez a0,a1,a0\n ret\n\n\nIt's a small, but visible instruction count savings and likely a small \nperformance improvement on most designs.\n\nSo the trick to get there is a small simplify-rtx improvement. We just \nneed to simplify\n(eq/ne (plus (x) (y)) (y)) -> (eq/ne (x) (0))\n\nAnd all the right things just happen. Bootstrapped and regression \ntested on a variety of native platforms including x86, aarch64, riscv \nand tested across the various embedded targets in my tester. I'll wait \nfor the RISC-V pre-commit CI tester to render a verdict before going \nforward.\n\nJeff\ncommit 13040879a85435edc05bef860cc8530f51a133b5\nAuthor: Jeff Law <jeffrey.law@oss.qualcomm.com>\nDate: Sun May 3 22:10:59 2026 -0600\n\n [V2][RISC-V][PR rtl-optimization/124766] Simplify x + y == y into x == 0\n \n So Richard S. noticed 3 issues in the V1 patch. Specifically it should have\n been using rtx_equal_p rather than just testing pointer equality. That's not a\n correctness issue, but could potentially allow the pattern to apply more often.\n \n Second we should be checking for !side_effects_p on the operand we're dropping.\n Easy to fix.\n \n Finally there was a const0_rtx use that should have been CONST0_RTX. Given how\n often I mention that one to others, I'm embarrassed I missed it.\n \n Bootstrapped on x86 and retested on the various embedded platforms. Bootstraps\n on riscv platforms, aarch64, armv7 and sh4eb are in flight.\n \n --\n \n So this is derived from S_regmatch in spec2017, so fairly hot.\n \n long\n frob (unsigned short *y, long z)\n {\n long ret = (*y << 2) + z;\n if (ret != z)\n return 0;\n return ret;\n }\n \n It generates this code on riscv:\n \n lhu a5,0(a0)\n sh2add a5,a5,a1\n sub a1,a1,a5\n czero.nez a0,a5,a1\n ret\n \n That's not bad, but the sh2add and sub are not actually needed. This may look\n familiar to a case Daniel was recently discussing, the major difference are the\n types of the function args which I got wrong the first time I reduced this\n case.\n \n czero instructions check their condition for zero/nonzero status. So we just\n need to know if a1 has a zero/nonzero value at the czero instruction. So\n working backwards:\n \n a1 = a1 - a5 // sub instruction\n a1 = a1 - ((a5 << 2) + a1) // substitute from sh2add\n a1 = a5 << 2 // a1 terms cancel out\n \n So we just need the nonzero state of a5 << 2. Now since a5 was set by the lhu\n instruction, the upper 48 bits are already known zero, so critically we know\n the upper 2 bits are zero. Meaning that we can just test a5 as set by the lhu\n instruction for zero/nonzero. The net is we can generate this code instead:\n \n lhu a0,0(a0)\n czero.nez a0,a1,a0\n ret\n \n It's a small, but visible instruction count savings and likely a small\n performance improvement on most designs.\n \n So the trick to get there is a small simplify-rtx improvement. We just need to\n simplify\n (eq/ne (plus (x) (y)) (y)) -> (eq/ne (x) (0))\n \n And all the right things just happen. Bootstrapped and regression tested on a\n variety of native platforms including x86, aarch64, riscv and tested across the\n various embedded targets in my tester. I'll wait for the RISC-V pre-commit CI\n tester to render a verdict before going forward.\n \n PR rtl-optimization/124766\n \n gcc/\n \n * simplify-rtx.cc (simplify_context::simplify_relational_operation_1):\n Simplify x + y == y constructs.\n \n gcc/testsuite/\n \n * gcc.target/riscv/pr124766.c: New test.", "diff": "diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc\nindex a87d91884df..bf625cdaf60 100644\n--- a/gcc/simplify-rtx.cc\n+++ b/gcc/simplify-rtx.cc\n@@ -6665,6 +6665,15 @@ simplify_context::simplify_relational_operation_1 (rtx_code code,\n return simplify_gen_relational (code, mode, cmp_mode, x, tem);\n }\n \n+ /* (eq/ne (plus (x) (y)) y) simplifies to (eq/ne x 0). */\n+ if ((code == EQ || code == NE)\n+ && op0code == PLUS\n+ && rtx_equal_p (XEXP (op0, 1), op1)\n+ && !side_effects_p (op1)\n+ && (INTEGRAL_MODE_P (cmp_mode) || flag_unsafe_math_optimizations))\n+ return simplify_gen_relational (code, mode, cmp_mode,\n+\t\t\t\t XEXP (op0, 0), CONST0_RTX (cmp_mode));\n+\n /* (ne:SI (zero_extract:SI FOO (const_int 1) BAR) (const_int 0))) is\n the same as (zero_extract:SI FOO (const_int 1) BAR). */\n scalar_int_mode int_mode, int_cmp_mode;\ndiff --git a/gcc/testsuite/gcc.target/riscv/pr124766.c b/gcc/testsuite/gcc.target/riscv/pr124766.c\nnew file mode 100644\nindex 00000000000..b16c31e8a9b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/pr124766.c\n@@ -0,0 +1,17 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv64gcbv_zicond -mabi=lp64d\" { target rv64 } } */\n+/* { dg-options \"-march=rv32gcbv_zicond -mabi=ilp32\" { target rv32 } } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\" } } */\n+\n+long\n+frob (unsigned short *y, long z)\n+{\n+ long ret = (*y << 2) + z;\n+ if (ret != z)\n+ return 0;\n+ return ret;\n+}\n+\n+/* { dg-final { scan-assembler-not \"sh2add\" } } */\n+/* { dg-final { scan-assembler-not \"sub\" } } */\n+\n", "prefixes": [ "V2", "to-be-committed", "RISC-V", "PR", "rtl-optimization/124766" ] }