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GET /api/patches/2232249/?format=api
{ "id": 2232249, "url": "http://patchwork.ozlabs.org/api/patches/2232249/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260504034510.3574-1-chen.zhongyao@zte.com.cn/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260504034510.3574-1-chen.zhongyao@zte.com.cn>", "list_archive_url": null, "date": "2026-05-04T03:45:10", "name": "[v3] RISC-V: Apply LMUL cost scaling to vector operations", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4ea28b03e0a1e9ba6eb62ac97e0550c5d03230a2", "submitter": { "id": 91632, "url": "http://patchwork.ozlabs.org/api/people/91632/?format=api", "name": "Zhongyao Chen", "email": "chenzhongyao.hit@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260504034510.3574-1-chen.zhongyao@zte.com.cn/mbox/", "series": [ { "id": 502605, "url": "http://patchwork.ozlabs.org/api/series/502605/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502605", "date": "2026-05-04T03:45:10", "name": "[v3] RISC-V: Apply LMUL cost scaling to vector operations", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502605/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232249/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232249/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Gs857bOC;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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The scaling\nis applied uniformly in adjust_stmt_cost for all vector operations.\n\nIn addition to VLA, VLS should also get the same LMUL cost scaling,\nbut doing so causes too many testsuite regressions currently,\nmostly because these tests also need expectation updates.\nThis is left for future work.\n\n\tPR target/122558\n\ngcc/ChangeLog:\n\n\t* config/riscv/riscv-vector-costs.cc (get_lmul_cost_scaling):\n\tNew function to calculate multiplicative scaling factors.\n\t(costs::adjust_stmt_cost): Apply LMUL scaling uniformly to all\n\tvector statements.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/autovec/pr122558.c: New test.\n\t* gcc.target/riscv/rvv/autovec/dyn-lmul-conv-1.c: Update expected\n\tdump counts after VLA LMUL cost scaling.\n\t* gcc.target/riscv/rvv/autovec/dyn-lmul-conv-2.c: Likewise.\n\t* gcc.target/riscv/rvv/autovec/partial/slp-16.c: Update expected dump\n\tcounts after LMUL cost scaling.\n\t* gcc.target/riscv/rvv/autovec/partial/slp-5.c: Likewise.\n\nSigned-off-by: Zhongyao Chen <chen.zhongyao@zte.com.cn>\n---\n gcc/config/riscv/riscv-vector-costs.cc | 50 +++++++++++++++++++\n .../riscv/rvv/autovec/dyn-lmul-conv-1.c | 5 +-\n .../riscv/rvv/autovec/dyn-lmul-conv-2.c | 3 +-\n .../riscv/rvv/autovec/partial/slp-16.c | 7 ++-\n .../riscv/rvv/autovec/partial/slp-5.c | 4 +-\n .../gcc.target/riscv/rvv/autovec/pr122558.c | 37 ++++++++++++++\n 6 files changed, 97 insertions(+), 9 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122558.c", "diff": "diff --git a/gcc/config/riscv/riscv-vector-costs.cc b/gcc/config/riscv/riscv-vector-costs.cc\nindex f582551eba7..e678e0de766 100644\n--- a/gcc/config/riscv/riscv-vector-costs.cc\n+++ b/gcc/config/riscv/riscv-vector-costs.cc\n@@ -1235,6 +1235,45 @@ segment_loadstore_group_size (enum vect_cost_for_stmt kind,\n return 0;\n }\n \n+/* Calculate LMUL-based cost scaling factor.\n+ Larger LMUL values process more data but have proportionally\n+ higher latency and register pressure.\n+\n+ Returns the cost scaling factor based on LMUL. For LMUL > 1,\n+ the factor represents the relative cost increase (2x, 4x, 8x).\n+ For LMUL <= 1, returns 1 (no scaling). */\n+static unsigned\n+get_lmul_cost_scaling (machine_mode mode)\n+{\n+ if (!riscv_vla_mode_p (mode))\n+ return 1;\n+\n+ enum vlmul_type vlmul = get_vlmul (mode);\n+\n+ /* Cost scaling based on LMUL and data processed.\n+ Larger LMUL values have proportionally higher latency:\n+ - m1 (LMUL_1): 1x (baseline)\n+ - m2 (LMUL_2): 2x (processes 2x data, ~2x latency)\n+ - m4 (LMUL_4): 4x (processes 4x data, ~4x latency)\n+ - m8 (LMUL_8): 8x (processes 8x data, ~8x latency)\n+ - mf2/mf4/mf8: 1x (fractional LMUL, already efficient) */\n+ switch (vlmul)\n+ {\n+ case LMUL_2:\n+ return 2;\n+ case LMUL_4:\n+ return 4;\n+ case LMUL_8:\n+ return 8;\n+ case LMUL_1:\n+ case LMUL_F2:\n+ case LMUL_F4:\n+ case LMUL_F8:\n+ default:\n+ return 1;\n+ }\n+}\n+\n /* Adjust vectorization cost after calling riscv_builtin_vectorization_cost.\n For some statement, we would like to further fine-grain tweak the cost on\n top of riscv_builtin_vectorization_cost handling which doesn't have any\n@@ -1379,6 +1418,17 @@ costs::adjust_stmt_cost (enum vect_cost_for_stmt kind, loop_vec_info loop,\n default:\n break;\n }\n+\n+ /* Apply LMUL cost scaling uniformly to all vector operations.\n+ Larger LMUL values have higher latency and register pressure,\n+ which affects performance regardless of loop structure. */\n+ if (vectype)\n+ {\n+ unsigned lmul_factor = get_lmul_cost_scaling (TYPE_MODE (vectype));\n+ if (lmul_factor > 1)\n+\tstmt_cost *= lmul_factor;\n+ }\n+\n return stmt_cost;\n }\n \ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-1.c\nindex b07bd86f76e..91d777a58a7 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-1.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-1.c\n@@ -37,6 +37,7 @@ void foo8x (long *restrict a, char *restrict b, int n)\n a[i] = b[i];\n }\n \n+/* { dg-final { scan-assembler-times \",m1,\" 3 } } */\n /* { dg-final { scan-assembler-times \",m2,\" 3 } } */\n-/* { dg-final { scan-assembler-times \",m4,\" 2 } } */\n-/* { dg-final { scan-assembler-times \",m8,\" 1 } } */\n+/* { dg-final { scan-assembler-times \",m4,\" 4 } } */\n+/* { dg-final { scan-assembler-times \",m8,\" 2 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-2.c\nindex c37e4dd63f2..468f061e3b1 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-2.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-2.c\n@@ -37,7 +37,8 @@ void foo8x (unsigned char *restrict a, unsigned long *restrict b, int n)\n a[i] = b[i];\n }\n \n-/* { dg-final { scan-assembler-times \",m1,\" 6 } } */\n+/* { dg-final { scan-assembler-times \",m1,\" 7 } } */\n /* { dg-final { scan-assembler-times \",m2,\" 3 } } */\n /* { dg-final { scan-assembler-times \",m4,\" 1 } } */\n+/* { dg-final { scan-assembler-times \",m8,\" 1 } } */\n /* { dg-final { scan-assembler-not \",mf2,\" } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c\nindex 1c7503b770e..b31453852b2 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c\n@@ -19,8 +19,7 @@ f (uint8_t *restrict a, uint8_t *restrict b, int n)\n }\n }\n \n-/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen\n- instead of SLP when rvv-autotec-max-lmul=m1. */\n-/* { dg-final { scan-tree-dump-times \"\\.VEC_PERM\" 1 \"optimized\" { xfail { any-opts \"-mrvv-max-lmul=m1\" } } } } */\n-/* { dg-final { scan-assembler {\\tvid\\.v} { xfail { any-opts \"-mrvv-max-lmul=m1\"} } } } */\n+/* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen instead of SLP. */\n+/* { dg-final { scan-tree-dump-times \"\\.VEC_PERM\" 1 \"optimized\" { xfail { any-opts \"-mrvv-max-lmul=m1\" \"-mrvv-max-lmul=m2\" \"-mrvv-max-lmul=m4\" \"-mrvv-max-lmul=m8\" } } } } */\n+/* { dg-final { scan-assembler {\\tvid\\.v} { xfail { any-opts \"-mrvv-max-lmul=m1\" \"-mrvv-max-lmul=m2\" \"-mrvv-max-lmul=m4\" \"-mrvv-max-lmul=m8\" } } } } */\n /* { dg-final { scan-assembler-not {\\tvmul} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c\nindex a10a7c831b1..2b2099d6e60 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c\n@@ -20,5 +20,5 @@ f (int8_t *restrict a, int8_t *restrict b, int n)\n }\n \n /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen\n- instead of SLP when rvv-autotec-max-lmul=m1. */\n-/* { dg-final { scan-tree-dump-times \"\\.VEC_PERM\" 1 \"optimized\" { xfail { any-opts \"-mrvv-max-lmul=m1\" } } } } */\n+ instead of SLP. */\n+/* { dg-final { scan-tree-dump-times \"\\.VEC_PERM\" 1 \"optimized\" { xfail { any-opts \"-mrvv-max-lmul=m1\" \"-mrvv-max-lmul=m2\" } } } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122558.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122558.c\nnew file mode 100644\nindex 00000000000..c9dbba64961\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122558.c\n@@ -0,0 +1,37 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3 -ftree-vectorize -mabi=lp64d -march=rv64gcv -mrvv-max-lmul=dynamic -fdump-tree-vect-all\" } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-O1\" \"-O2\" \"-Os\" \"-Og\" \"-Oz\" } } */\n+\n+#include <stdint-gcc.h>\n+\n+void dct( int16_t d[16], int16_t dct[16] )\n+{\n+ int16_t tmp[16];\n+ for( int i = 0; i < 4; i++ )\n+ {\n+ int s03 = d[i*4+0] + d[i*4+3];\n+ int s12 = d[i*4+1] + d[i*4+2];\n+ int d03 = d[i*4+0] - d[i*4+3];\n+ int d12 = d[i*4+1] - d[i*4+2];\n+ tmp[0*4+i] = s03 + s12;\n+ tmp[1*4+i] = 2*d03 + d12;\n+ tmp[2*4+i] = s03 - s12;\n+ tmp[3*4+i] = d03 - 2*d12;\n+ }\n+ for( int i = 0; i < 4; i++ )\n+ {\n+ int s03 = tmp[i*4+0] + tmp[i*4+3];\n+ int s12 = tmp[i*4+1] + tmp[i*4+2];\n+ int d03 = tmp[i*4+0] - tmp[i*4+3];\n+ int d12 = tmp[i*4+1] - tmp[i*4+2];\n+\n+ dct[i*4+0] = s03 + s12;\n+ dct[i*4+1] = 2*d03 + d12;\n+ dct[i*4+2] = s03 - s12;\n+ dct[i*4+3] = d03 - 2*d12;\n+ }\n+}\n+\n+/* { dg-final { scan-tree-dump \"LOOP VECTORIZED\" \"vect\" } } */\n+/* { dg-final { scan-tree-dump \"Choosing vector mode RVVMF2QI\" \"vect\" } } */\n+\n", "prefixes": [ "v3" ] }