Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2232248/?format=api
{ "id": 2232248, "url": "http://patchwork.ozlabs.org/api/patches/2232248/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260504033305.2283145-1-weichengc@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260504033305.2283145-1-weichengc@nvidia.com>", "list_archive_url": null, "date": "2026-05-04T03:33:05", "name": "[v2] phy: tegra: xusb: Fix per-pad high-speed termination calibration", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c06c2d102f022cdb23440e3cbe11a58005b1c202", "submitter": { "id": 92394, "url": "http://patchwork.ozlabs.org/api/people/92394/?format=api", "name": "Wei-Cheng Chen", "email": "weichengc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260504033305.2283145-1-weichengc@nvidia.com/mbox/", "series": [ { "id": 502604, "url": "http://patchwork.ozlabs.org/api/series/502604/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502604", "date": "2026-05-04T03:33:05", "name": "[v2] phy: tegra: xusb: Fix per-pad high-speed termination calibration", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502604/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232248/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232248/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-14150-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=GwEM8BFF;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-tegra+bounces-14150-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"GwEM8BFF\"", "smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.93.198.36", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com", "smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g86gF0mW2z1yJ9\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 04 May 2026 13:33:28 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 694A330067AE\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 4 May 2026 03:33:26 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 3877F1E834B;\n\tMon, 4 May 2026 03:33:26 +0000 (UTC)", "from CY7PR03CU001.outbound.protection.outlook.com\n (mail-westcentralusazon11010036.outbound.protection.outlook.com\n [40.93.198.36])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D9923594A;\n\tMon, 4 May 2026 03:33:24 +0000 (UTC)", "from MN2PR20CA0004.namprd20.prod.outlook.com (2603:10b6:208:e8::17)\n by CH8PR12MB9789.namprd12.prod.outlook.com (2603:10b6:610:260::17) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9870.25; Mon, 4 May\n 2026 03:33:19 +0000", "from BL02EPF0001A0FB.namprd03.prod.outlook.com\n (2603:10b6:208:e8:cafe::e3) by MN2PR20CA0004.outlook.office365.com\n (2603:10b6:208:e8::17) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9870.25 via Frontend Transport; Mon,\n 4 May 2026 03:33:19 +0000", "from mail.nvidia.com (216.228.117.160) by\n BL02EPF0001A0FB.mail.protection.outlook.com (10.167.242.102) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9891.9 via Frontend Transport; Mon, 4 May 2026 03:33:18 +0000", "from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 3 May\n 2026 20:33:08 -0700", "from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail203.nvidia.com\n (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 3 May\n 2026 20:33:08 -0700", "from 5b171f0-lcelt.nvidia.com (10.127.8.13) by mail.nvidia.com\n (10.129.68.10) with Microsoft SMTP Server id 15.2.2562.20 via Frontend\n Transport; Sun, 3 May 2026 20:33:06 -0700" ], "ARC-Seal": [ "i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777865606; cv=fail;\n b=etMZJfmECJ1lmwrBO9KCyIpLL+AkitkfarNqHzCIekDnno4nBzjN3/8NG5ZHRvSHikaItDZxcn/kIcEnIFa37Tiku9Wc6Drnj95ongxv5K6GzrfTspNJ2wZZL79qxADlVsnQJpiQso/jhOT6aw4beWYkIM++Rc2KeacFK4Tcs10=", "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=eSAtUxrZjZCvLuWoftgNSFpc5quXkJ538ICUG1RHjzDYqma/G4CyX7gIExV6o79enob6zefav1zC6ssMvyOMWmHw8GwteP4H+OK5RVjm/1Nzs60UpPzgIlnfxXtH3eZC6RUCzb5f8KW3PSm62vyrQhBZV/1X9zhcaCndx3QNZX2FlJwdzU2sL9i7IXTPxlWLR1PR2vAht7AVmDGnyUjq3BDd8yNstV5Q6ItPIep6luNSlIHoilMw76Xni/BoyjVjdCnPdJdSxV+s7biIrDu+s9yRtxG20l+GltamuBglaRQHPWioXeK/7wx+8S0M3EKL/UO8JKMsJBv2v+OIZHPXYg==" ], "ARC-Message-Signature": [ "i=2; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777865606; c=relaxed/simple;\n\tbh=KdyQfoLjZMt+CUCNGWoP+AAvdlXX9UGLD+SBgUa5Mew=;\n\th=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type;\n b=DO8fm7VB+ueEMcH3ghE0IJW/TyGaY/bcdzDGp2mMBggGWZN0pxQKV2/HUFHnJf1V/PcNxwYKfh7Lwzvu25Kce9RJAi3zFY71jIPo9ukEQqoDAfVOpAk1yNeYBDqWkhj+mZRsxdY1WgxpO7hYixVTSMf+TS6DZY8gHSvUO/RIWkQ=", "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=g62HCHwFmhveodrjNFbtdfxdftGDv4RY9jwyLaU96ic=;\n b=UzY/7rPnG0n546aP3k/ZP2EFpvIJdJOvF4TAiieUuaIYGDh+dP+uO5Yz7So4/4Yef7qrUsA//+eKuqc5rqO7FZHpgblYlewne/9GV1WE6pPc23XkzeFljigeUs4L3SfEs2NwLT4fJ2qpt9ADSDXE6fRafWza63GRoJHUmjaqGNmb0J5O/DTl9nC9f+297ZVlEBPoYGCTiD1iXrnNcZOfrPHwjcPALiucjDMb4M9hF+Bymn0lvv+RJH588Y5drDhQdOA9Bdx7BrCwqUG2Mbz3iOX4E/AfpBKeEaV3AWOA6LskbqzaRHTu6r5uZyqJI02HR+iMsEeJ9z5oR7FwHYknNw==" ], "ARC-Authentication-Results": [ "i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com;\n spf=fail smtp.mailfrom=nvidia.com;\n dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=GwEM8BFF; arc=fail smtp.client-ip=40.93.198.36", "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=g62HCHwFmhveodrjNFbtdfxdftGDv4RY9jwyLaU96ic=;\n b=GwEM8BFFEvPp0w7WtYmxVo27QBkKNKUnA/iIwzJE6IF9jYIl+18uxYJjRmhHdQ+jUGIf3WA/CyMHCnF2W6T9aJFQT6SACv8EacyOOVk/MzlCXVUWPG0h0ie+PBuEpsgY2PWdmlrgpxXc35rr38OQtIqH2livEA1kJjfneN4YoGRlhiUnUowXUzOXsLGGaf2xREhTpQEUoZKGg0DibDSbz21N0SP9FLrZcfSnRHIMMueeIMKztTmHdu37otSTFzprAirtSV57+wl/cvqXFJWOrb4AcxhE0GU/XTNVE4LwEkJQ5Ecx6xxe8teuzwRXcK92ChVmHxq4enksOdAe9GaZgg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Wei-Cheng Chen <weichengc@nvidia.com>", "To": "Vinod Koul <vkoul@kernel.org>, Jonathan Hunter <jonathanh@nvidia.com>, \"JC\n Kuo\" <jckuo@nvidia.com>, Neil Armstrong <neil.armstrong@linaro.org>, \"Thierry\n Reding\" <thierry.reding@kernel.org>", "CC": "Wayne Chang <waynec@nvidia.com>, WK Tsai <wtsai@nvidia.com>,\n\t<linux-phy@lists.infradead.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>", "Subject": "[PATCH v2] phy: tegra: xusb: Fix per-pad high-speed termination\n calibration", "Date": "Mon, 4 May 2026 11:33:05 +0800", "Message-ID": "<20260504033305.2283145-1-weichengc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A0FB:EE_|CH8PR12MB9789:EE_", "X-MS-Office365-Filtering-Correlation-Id": "d7a72528-2ef2-4b85-9e34-08dea98de2a2", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|36860700016|376014|82310400026|13003099007|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\t/2J2kjjWVmhr4eueQhFDitBmxaM37sXwRjJQTDLTkZIHsFWtdRG0LVzeaSn7LCIhBp3ulWdafrzxwFEdlG8TpeN5FXi67zaFJawdbsEamYQqBeLTZ59wuDMUIj89khyiazgWhUSB6Bx7X8W0xgQphJfMjbgXQSf2aIaVPM/rjs+ARypEDbSNySL4kG1KS20v+YSlV5ioDJ2mYI75LxSZN26ukHoTuBARocWIl7mLxG0zB6APo6P8w/qynu1/GDdO+mNDk4MwRpdWgyxDT+ya2dvUn1CDeawP5FHsZZ08ttAwXJxzjCQ1aFFVzp0ZTe09qeAEct5f9nZtInAjR2StwT1B96i+AekPejIsF+cTcsnTAJzOtPXMw9q58+ziQx3HilmyIDW6V5XXeVwHGrIJSgR0CL7VonIIKYUQoJD0KzgBRABsEblWSQGPNveSBJ3YAsbclWxiwj8gFKYjlN1tipHkI5Jljy2o8klzcK8rzWKf06/QNO4tPzIBovMGpwGkVpkPTXVhC2PRBV4eGnqu8tsHEEmfqBLaXMH09K3oFpCMuf00FwlckzAQBWrDqfwhndgVH/KtPXLJX9zdOz6i3EU9M8WkRs4vv0MHdbTVIjn6uxvnVX8b4SalaBH3tfGYXEFy+S7iOM26BST2p7SEXyjjrGy3Qw+AyxiMkhKbBfJDeJFza4/CEvXLfzIkNUIi2oZDvATk+l0uabP04E19J4GmwllYPDWCH/W448sqZxhB+61yqE5QS5mQyplt1DBG", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(376014)(82310400026)(13003099007)(18002099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t6/iBOcL3GfoQDk2MtkqCeIbRH1PwqcFc4knz2c8w3+B1VojtvuVrOQ1YcAZJmzXTcbKTsJOFoSIhNN9bS+tmoOMVsEGvvD38Ey1PTThGM+DgCHu3AVrqszDY3Ap7Ab7pFjsaFScI4bNTsjEz0uYzj58+e9aufZ8zETlhLB07r5ZhpUWiscunGCIizwpfXZtgh5C5Mch8wQ1B/WBhECIo9F46vs5CY3S535clam7F8edorfunwIqVtud8Mlou+3tHBPGzkhBNFDF9yEWUlQvUuClb4tfMqzs53E8F0PS62Q2uX26rj68BStYxOU23Yao9HkMsfdB+XUHbp+n8x2R8em4RJp3J5xyHHgXDsDy+KGgbXeNNfzi+816fI/CSWEXML8QABUTQDwe0Q7xxdQtYiMZczr75CVWa/KoJbchbFL1QA/Jga4EcvpMRRhzwurIp", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 May 2026 03:33:18.9039\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d7a72528-2ef2-4b85-9e34-08dea98de2a2", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBL02EPF0001A0FB.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH8PR12MB9789" }, "content": "From: Wayne Chang <waynec@nvidia.com>\n\nThe existing code reads a single hs_term_range_adj value from bit field\n[10:7] of FUSE_SKU_CALIB_0 and applies it to all USB2 pads uniformly.\nHowever, on SoCs that support per-pad termination, each pad has its own\nhs_term_range_adj field: pad 0 in FUSE_SKU_CALIB_0[10:7], and pads 1-3\nin FUSE_USB_CALIB_EXT_0 at bit offsets [8:5], [12:9], and [16:13]\nrespectively.\n\nFix the calibration by reading per-pad values from the appropriate fuse\nregisters. For SoCs that do not support per-pad termination, replicate\npad 0's value to all pads to maintain existing behavior.\n\nAdd a has_per_pad_term flag to the SoC data to indicate whether per-pad\ntermination values are available in FUSE_USB_CALIB_EXT_0.\n\nFixes: 1ef535c6ba8e (\"phy: tegra: xusb: Add Tegra194 support\")\nCc: stable@vger.kernel.org\nSigned-off-by: Wayne Chang <waynec@nvidia.com>\nSigned-off-by: Wei-Cheng Chen <weichengc@nvidia.com>\nReviewed-by: Jon Hunter <jonathanh@nvidia.com>\nTested-by: Jon Hunter <jonathanh@nvidia.com>\n---\nChanges in v2:\n- Rebased on v7.1-rc1 per Vinod's request. No functional changes;\n range-diff vs v1 confirms identical payload.\n- Carried over Jon's Reviewed-by and Tested-by tags from v1\n (https://lore.kernel.org/all/77285dd6-e240-4944-a034-a4bc3acf4052@nvidia.com/).\n\n drivers/phy/tegra/xusb-tegra186.c | 33 ++++++++++++++++++++++++-------\n drivers/phy/tegra/xusb.h | 1 +\n 2 files changed, 27 insertions(+), 7 deletions(-)\n\n\nbase-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731", "diff": "diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c\nindex 1ddf1126597..60156aea270 100644\n--- a/drivers/phy/tegra/xusb-tegra186.c\n+++ b/drivers/phy/tegra/xusb-tegra186.c\n@@ -20,8 +20,8 @@\n /* FUSE USB_CALIB registers */\n #define HS_CURR_LEVEL_PADX_SHIFT(x)\t((x) ? (11 + (x - 1) * 6) : 0)\n #define HS_CURR_LEVEL_PAD_MASK\t\t0x3f\n-#define HS_TERM_RANGE_ADJ_SHIFT\t\t7\n-#define HS_TERM_RANGE_ADJ_MASK\t\t0xf\n+#define HS_TERM_RANGE_ADJ_PADX_SHIFT(x)\t((x) ? (5 + (x - 1) * 4) : 7)\n+#define HS_TERM_RANGE_ADJ_PAD_MASK\t0xf\n #define HS_SQUELCH_SHIFT\t\t29\n #define HS_SQUELCH_MASK\t\t\t0x7\n \n@@ -253,7 +253,7 @@\n struct tegra_xusb_fuse_calibration {\n \tu32 *hs_curr_level;\n \tu32 hs_squelch;\n-\tu32 hs_term_range_adj;\n+\tu32 *hs_term_range_adj;\n \tu32 rpd_ctrl;\n };\n \n@@ -930,7 +930,7 @@ static int tegra186_utmi_phy_power_on(struct phy *phy)\n \n \tvalue = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));\n \tvalue &= ~TERM_RANGE_ADJ(~0);\n-\tvalue |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);\n+\tvalue |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj[index]);\n \tvalue &= ~RPD_CTRL(~0);\n \tvalue |= RPD_CTRL(priv->calib.rpd_ctrl);\n \tpadctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));\n@@ -1464,17 +1464,23 @@ static const char * const tegra186_usb3_functions[] = {\n static int\n tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)\n {\n+\tconst struct tegra_xusb_padctl_soc *soc = padctl->base.soc;\n \tstruct device *dev = padctl->base.dev;\n \tunsigned int i, count;\n \tu32 value, *level;\n+\tu32 *hs_term_range_adj;\n \tint err;\n \n-\tcount = padctl->base.soc->ports.usb2.count;\n+\tcount = soc->ports.usb2.count;\n \n \tlevel = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);\n \tif (!level)\n \t\treturn -ENOMEM;\n \n+\ths_term_range_adj = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);\n+\tif (!hs_term_range_adj)\n+\t\treturn -ENOMEM;\n+\n \terr = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);\n \tif (err)\n \t\treturn dev_err_probe(dev, err,\n@@ -1490,8 +1496,8 @@ tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)\n \n \tpadctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &\n \t\t\t\t\tHS_SQUELCH_MASK;\n-\tpadctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &\n-\t\t\t\t\t\tHS_TERM_RANGE_ADJ_MASK;\n+\ths_term_range_adj[0] = (value >> HS_TERM_RANGE_ADJ_PADX_SHIFT(0)) &\n+\t\t\t\tHS_TERM_RANGE_ADJ_PAD_MASK;\n \n \terr = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);\n \tif (err) {\n@@ -1503,6 +1509,17 @@ tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)\n \n \tpadctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;\n \n+\tfor (i = 1; i < count; i++) {\n+\t\tif (soc->has_per_pad_term)\n+\t\t\ths_term_range_adj[i] =\n+\t\t\t\t(value >> HS_TERM_RANGE_ADJ_PADX_SHIFT(i)) &\n+\t\t\t\tHS_TERM_RANGE_ADJ_PAD_MASK;\n+\t\telse\n+\t\t\ths_term_range_adj[i] = hs_term_range_adj[0];\n+\t}\n+\n+\tpadctl->calib.hs_term_range_adj = hs_term_range_adj;\n+\n \treturn 0;\n }\n \n@@ -1708,6 +1725,7 @@ const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = {\n \t.num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),\n \t.supports_gen2 = true,\n \t.poll_trk_completed = true,\n+\t.has_per_pad_term = true,\n };\n EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);\n \n@@ -1732,6 +1750,7 @@ const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc = {\n \t.trk_hw_mode = false,\n \t.trk_update_on_idle = true,\n \t.supports_lp_cfg_en = true,\n+\t.has_per_pad_term = true,\n };\n EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc);\n #endif\ndiff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h\nindex cd277d0ed9e..77609e54de6 100644\n--- a/drivers/phy/tegra/xusb.h\n+++ b/drivers/phy/tegra/xusb.h\n@@ -435,6 +435,7 @@ struct tegra_xusb_padctl_soc {\n \tbool trk_hw_mode;\n \tbool trk_update_on_idle;\n \tbool supports_lp_cfg_en;\n+\tbool has_per_pad_term;\n };\n \n struct tegra_xusb_padctl {\n", "prefixes": [ "v2" ] }