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GET /api/patches/2232158/?format=api
{ "id": 2232158, "url": "http://patchwork.ozlabs.org/api/patches/2232158/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503073541.790215-5-eric.auger@redhat.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260503073541.790215-5-eric.auger@redhat.com>", "list_archive_url": null, "date": "2026-05-03T07:33:24", "name": "[v4,04/17] arm/cpu: Add infra to handle generated ID register definitions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "de520bc21ce22c59baa00bb481eabc8ad63f2231", "submitter": { "id": 69187, "url": "http://patchwork.ozlabs.org/api/people/69187/?format=api", "name": "Eric Auger", "email": "eric.auger@redhat.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503073541.790215-5-eric.auger@redhat.com/mbox/", "series": [ { "id": 502569, "url": "http://patchwork.ozlabs.org/api/series/502569/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502569", "date": "2026-05-03T07:33:20", "name": "kvm/arm: Introduce a customizable aarch64 KVM host model", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/502569/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232158/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232158/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=Dy274kXF;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g7c7v2MvTz1yK4\n\tfor <incoming@patchwork.ozlabs.org>; Sun, 03 May 2026 17:38:03 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wJRNQ-00085w-I9; Sun, 03 May 2026 03:36:32 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <eric.auger@redhat.com>)\n id 1wJRNH-00085V-Ah\n for qemu-devel@nongnu.org; Sun, 03 May 2026 03:36:23 -0400", "from us-smtp-delivery-124.mimecast.com ([170.10.133.124])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <eric.auger@redhat.com>)\n id 1wJRNF-0003YT-PU\n for qemu-devel@nongnu.org; Sun, 03 May 2026 03:36:23 -0400", "from mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com\n (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by\n relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3,\n cipher=TLS_AES_256_GCM_SHA384) id us-mta-80-1tdrefN_OA6tJm76iHJILA-1; Sun,\n 03 May 2026 03:36:17 -0400", "from mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com\n (mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.93])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS\n id EFC4919560AA; Sun, 3 May 2026 07:36:15 +0000 (UTC)", "from laptop.redhat.com (unknown [10.44.48.25])\n by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP\n id 0F9C81800577; Sun, 3 May 2026 07:36:10 +0000 (UTC)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1777793781;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=qb3QW9P09q68kQSB3KrvBidDZUkt/y6oNpcfFLBp4WY=;\n b=Dy274kXFozzHeN6ySUXZ/AswStmmHaTtYdWP4nnjsoCgaqz2smN8jKxJE3kUe2U4K+DkrY\n 8TdaFr5cs0RYXUuWnTL4eU4VbQbUwjelkBDCjr1aFMk2ncPWYj3YsyjMJbO/da5gAD8Mg+\n PyG3Gy49QzrhPQpfXJblKXXKkWE4Od8=", "X-MC-Unique": "1tdrefN_OA6tJm76iHJILA-1", "X-Mimecast-MFC-AGG-ID": "1tdrefN_OA6tJm76iHJILA_1777793776", "From": "Eric Auger <eric.auger@redhat.com>", "To": "eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org,\n qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org,\n richard.henderson@linaro.org, cohuck@redhat.com, sebott@redhat.com,\n skolothumtho@nvidia.com, philmd@linaro.org", "Cc": "maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com,\n armbru@redhat.com, berrange@redhat.com, abologna@redhat.com,\n jdenemar@redhat.com", "Subject": "[PATCH v4 04/17] arm/cpu: Add infra to handle generated ID register\n definitions", "Date": "Sun, 3 May 2026 09:33:24 +0200", "Message-ID": "<20260503073541.790215-5-eric.auger@redhat.com>", "In-Reply-To": "<20260503073541.790215-1-eric.auger@redhat.com>", "References": "<20260503073541.790215-1-eric.auger@redhat.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Scanned-By": "MIMEDefang 3.4.1 on 10.30.177.93", "Received-SPF": "pass client-ip=170.10.133.124;\n envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com", "X-Spam_score_int": "12", "X-Spam_score": "1.2", "X-Spam_bar": "+", "X-Spam_report": "(1.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The known ID regs are populated in a new initialization function\nnamed initialize_cpu_sysreg_properties(). That code will be\nautomatically generated from AARCHMRS Registers.json. For the\ntime being let's just describe a single id reg, CTR_EL0. In this\ndescription we only care about non RES/RAZ fields, ie. named fields.\n\nThe registers are populated in an array indexed by ARMIDRegisterIdx\nand their fields are added in a sorted list.\n\n[CH: adapted to reworked register storage]\nSigned-off-by: Eric Auger <eric.auger@redhat.com>\nSigned-off-by: Cornelia Huck <cohuck@redhat.com>\n---\n target/arm/cpu-idregs.h | 59 ++++++++++++++++++++++++++++++\n target/arm/cpu-sysreg-properties.c | 30 +++++++++++++++\n target/arm/cpu64.c | 3 ++\n target/arm/meson.build | 3 +-\n 4 files changed, 94 insertions(+), 1 deletion(-)\n create mode 100644 target/arm/cpu-idregs.h\n create mode 100644 target/arm/cpu-sysreg-properties.c", "diff": "diff --git a/target/arm/cpu-idregs.h b/target/arm/cpu-idregs.h\nnew file mode 100644\nindex 0000000000..4a9034594d\n--- /dev/null\n+++ b/target/arm/cpu-idregs.h\n@@ -0,0 +1,59 @@\n+/*\n+ * handle ID registers and their fields\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+#ifndef ARM_CPU_CUSTOM_H\n+#define ARM_CPU_CUSTOM_H\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/error-report.h\"\n+#include \"cpu.h\"\n+#include \"cpu-sysregs.h\"\n+\n+typedef struct ARM64SysRegField {\n+ const char *name; /* name of the field, for instance CTR_EL0_IDC */\n+ ARMIDRegisterIdx index; /* parent register, e.g. CTR_EL0_IDX */\n+ int lower; /* lowest bit number of the field in the register */\n+ int upper; /* highest bit number */\n+} ARM64SysRegField;\n+\n+typedef struct ARM64SysReg {\n+ const char *name; /* name of the sysreg, for instance CTR_EL0 */\n+ ARMSysRegs sysreg;\n+ ARMIDRegisterIdx index; /* register index, e.g. CTR_EL0_IDX */\n+ GList *fields; /* list of named fields, excluding RES* */\n+} ARM64SysReg;\n+\n+void initialize_cpu_sysreg_properties(void);\n+\n+/*\n+ * List of exposed ID regs (automatically populated from AARCHMRS Registers.json)\n+ */\n+extern ARM64SysReg arm64_id_regs[NUM_ID_IDX];\n+\n+/* Allocate a new field and insert it at the head of the @reg list */\n+static inline GList *arm64_sysreg_add_field(ARM64SysReg *reg, const char *name,\n+ uint8_t min, uint8_t max) {\n+\n+ ARM64SysRegField *field = g_new0(ARM64SysRegField, 1);\n+\n+ field->name = name;\n+ field->lower = min;\n+ field->upper = max;\n+ field->index = reg->index;\n+\n+ reg->fields = g_list_append(reg->fields, field);\n+ return reg->fields;\n+}\n+\n+static inline ARM64SysReg *arm64_sysreg_get(ARMIDRegisterIdx index)\n+{\n+ ARM64SysReg *reg = &arm64_id_regs[index];\n+\n+ reg->index = index;\n+ reg->sysreg = id_register_sysreg[index];\n+ return reg;\n+}\n+\n+#endif\ndiff --git a/target/arm/cpu-sysreg-properties.c b/target/arm/cpu-sysreg-properties.c\nnew file mode 100644\nindex 0000000000..5cc06c8f24\n--- /dev/null\n+++ b/target/arm/cpu-sysreg-properties.c\n@@ -0,0 +1,30 @@\n+/*\n+ * QEMU ARM CPU SYSREG PROPERTIES\n+ * will be automatically generated\n+ *\n+ * Copyright (c) Red Hat, Inc. 2026\n+ *\n+ */\n+\n+ /* SPDX-License-Identifier: GPL-2.0-or-later */\n+\n+#include \"cpu-idregs.h\"\n+\n+ARM64SysReg arm64_id_regs[NUM_ID_IDX];\n+\n+void initialize_cpu_sysreg_properties(void)\n+{\n+ memset(arm64_id_regs, 0, sizeof(ARM64SysReg) * NUM_ID_IDX);\n+ /* CTR_EL0 */\n+ ARM64SysReg *CTR_EL0 = arm64_sysreg_get(CTR_EL0_IDX);\n+ CTR_EL0->name = \"CTR_EL0\";\n+ arm64_sysreg_add_field(CTR_EL0, \"TminLine\", 32, 37);\n+ arm64_sysreg_add_field(CTR_EL0, \"DIC\", 29, 29);\n+ arm64_sysreg_add_field(CTR_EL0, \"IDC\", 28, 28);\n+ arm64_sysreg_add_field(CTR_EL0, \"CWG\", 24, 27);\n+ arm64_sysreg_add_field(CTR_EL0, \"ERG\", 20, 23);\n+ arm64_sysreg_add_field(CTR_EL0, \"DminLine\", 16, 19);\n+ arm64_sysreg_add_field(CTR_EL0, \"L1Ip\", 14, 15);\n+ arm64_sysreg_add_field(CTR_EL0, \"IminLine\", 0, 3);\n+}\n+\ndiff --git a/target/arm/cpu64.c b/target/arm/cpu64.c\nindex a93ad2da5a..b940842d9e 100644\n--- a/target/arm/cpu64.c\n+++ b/target/arm/cpu64.c\n@@ -37,6 +37,7 @@\n #include \"hw/core/qdev-properties.h\"\n #include \"internals.h\"\n #include \"cpu-features.h\"\n+#include \"cpu-idregs.h\"\n \n /* convert between <register>_IDX and SYS_<register> */\n #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \\\n@@ -906,6 +907,8 @@ static void aarch64_cpu_register_types(void)\n {\n size_t i;\n \n+ initialize_cpu_sysreg_properties();\n+\n for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {\n arm_cpu_register(&aarch64_cpus[i]);\n }\ndiff --git a/target/arm/meson.build b/target/arm/meson.build\nindex 192ac7c31e..e2f740e48f 100644\n--- a/target/arm/meson.build\n+++ b/target/arm/meson.build\n@@ -9,7 +9,8 @@ arm_user_ss.add(files('gdbstub.c'))\n \n arm_ss.add(when: 'TARGET_AARCH64', if_true: files(\n 'cpu64.c',\n- 'gdbstub64.c'\n+ 'gdbstub64.c',\n+ 'cpu-sysreg-properties.c',\n ))\n \n arm_common_ss.add(files(\n", "prefixes": [ "v4", "04/17" ] }