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GET /api/patches/2232141/?format=api
{ "id": 2232141, "url": "http://patchwork.ozlabs.org/api/patches/2232141/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503015756.99176-2-54weasels@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260503015756.99176-2-54weasels@gmail.com>", "list_archive_url": null, "date": "2026-05-03T01:57:50", "name": "[1/7] target/m68k: Implement Physical Bus Error exception handling", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e115b3ff345adaa5afe78c5ba2c70bc4c7c00b24", "submitter": { "id": 93309, "url": "http://patchwork.ozlabs.org/api/people/93309/?format=api", "name": "54weasels", "email": "54weasels@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503015756.99176-2-54weasels@gmail.com/mbox/", "series": [ { "id": 502564, "url": "http://patchwork.ozlabs.org/api/series/502564/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502564", "date": "2026-05-03T01:57:51", "name": "m68k: Add Sun-3 Machine Emulation", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502564/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232141/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232141/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=lO03dlPb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-dy1-x132b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Sun, 03 May 2026 01:58:55 -0400", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The M68020 natively maps hardware Bus Error (BERR) timeouts into a Long Bus Cycle Fault (Format 0xB). This commit adds the memory exception routing to natively synthesize these EXCP_ACCESS cycle faults. It also implements the double-fault / watchdog reset behavior required for Sun-3 hardware diagnostics, properly handles FSAVE/FRESTORE for 68881 FPU stubs, and properly constructs the 84-byte internal bus fault frame.\n\nSigned-off-by: 54weasels <54weasels@gmail.com>\n---\n target/m68k/cpu.c | 5 +-\n target/m68k/cpu.h | 18 +++-\n target/m68k/helper.c | 130 ++++++++++++++++++++++++++++-\n target/m68k/op_helper.c | 176 ++++++++++++++++++++++++++--------------\n target/m68k/translate.c | 31 +++++--\n 5 files changed, 283 insertions(+), 77 deletions(-)", "diff": "diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c\nindex d849a4a90f..af375f0bce 100644\n--- a/target/m68k/cpu.c\n+++ b/target/m68k/cpu.c\n@@ -1,3 +1,4 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n /*\n * QEMU Motorola 68k CPU\n *\n@@ -51,8 +52,8 @@ static TCGTBCPUState m68k_get_tb_cpu_state(CPUState *cs)\n flags = (env->macsr >> 4) & TB_FLAGS_MACSR;\n if (env->sr & SR_S) {\n flags |= TB_FLAGS_MSR_S;\n- flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;\n- flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;\n+ flags |= (env->sfc << TB_FLAGS_SFC_S_BIT) & TB_FLAGS_SFC_S;\n+ flags |= (env->dfc << TB_FLAGS_DFC_S_BIT) & TB_FLAGS_DFC_S;\n }\n if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) {\n flags |= TB_FLAGS_TRACE;\ndiff --git a/target/m68k/cpu.h b/target/m68k/cpu.h\nindex 7911ab9de3..426ef6a6e1 100644\n--- a/target/m68k/cpu.h\n+++ b/target/m68k/cpu.h\n@@ -149,10 +149,18 @@ typedef struct CPUArchState {\n \n int pending_vector;\n int pending_level;\n+ bool nmi_pending;\n \n /* Fields up to this point are cleared by a CPU reset */\n struct {} end_reset_fields;\n \n+ /* Custom MMU intercept logic, if any (e.g. for Sun-3) */\n+ void *custom_mmu_opaque;\n+ int (*custom_mmu_get_physical_address)(void *env, hwaddr *physical,\n+ int *prot, vaddr address,\n+ int access_type,\n+ hwaddr *page_size);\n+\n /* Fields from here on are preserved across CPU reset. */\n uint64_t features;\n } CPUM68KState;\n@@ -601,12 +609,14 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,\n #define TB_FLAGS_MSR_S_BIT 13\n #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT)\n #define TB_FLAGS_SFC_S_BIT 14\n-#define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT)\n-#define TB_FLAGS_DFC_S_BIT 15\n-#define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT)\n-#define TB_FLAGS_TRACE 16\n+#define TB_FLAGS_SFC_S (7 << TB_FLAGS_SFC_S_BIT) /* 3 Bits reserved */\n+#define TB_FLAGS_DFC_S_BIT 17\n+#define TB_FLAGS_DFC_S (7 << TB_FLAGS_DFC_S_BIT) /* 3 Bits reserved */\n+#define TB_FLAGS_TRACE 20\n #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE)\n \n+#define MMU_MOVES_FC_BASE 2 /* mmu_idx 2-9 correspond to FC 0-7 */\n+\n void dump_mmu(CPUM68KState *env);\n \n #endif\ndiff --git a/target/m68k/helper.c b/target/m68k/helper.c\nindex 9bab184389..997c2616f4 100644\n--- a/target/m68k/helper.c\n+++ b/target/m68k/helper.c\n@@ -28,6 +28,7 @@\n #include \"system/memory.h\"\n #include \"gdbstub/helpers.h\"\n #include \"fpu/softfloat.h\"\n+#include \"qemu/log.h\"\n #include \"qemu/qemu-print.h\"\n \n #define SIGNBIT (1u << 31)\n@@ -280,8 +281,10 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)\n return;\n }\n break;\n- /* Unimplemented Registers */\n+ /* Dummy implementation for CAAR */\n case M68K_CR_CAAR:\n+ return;\n+ /* Unimplemented Registers */\n case M68K_CR_PCR:\n case M68K_CR_BUSCR:\n cpu_abort(env_cpu(env),\n@@ -384,8 +387,10 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)\n return env->mmu.ttr[M68K_DTTR1];\n }\n break;\n- /* Unimplemented Registers */\n+ /* Dummy implementation for CAAR */\n case M68K_CR_CAAR:\n+ return 0;\n+ /* Unimplemented Registers */\n case M68K_CR_PCR:\n case M68K_CR_BUSCR:\n cpu_abort(env_cpu(env), \"Unimplemented control register read 0x%x\\n\",\n@@ -915,6 +920,21 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n int access_type;\n target_ulong page_size;\n \n+ access_type = ACCESS_DATA | ACCESS_DEBUG;\n+ if (env->sr & SR_S) {\n+ access_type |= ACCESS_SUPER;\n+ }\n+\n+ if (env->custom_mmu_get_physical_address) {\n+ hwaddr custom_page_size;\n+ if (env->custom_mmu_get_physical_address(env, &phys_addr, &prot, addr,\n+ access_type,\n+ &custom_page_size) == 0) {\n+ return phys_addr;\n+ }\n+ return -1;\n+ }\n+\n if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {\n /* MMU disabled */\n return addr;\n@@ -944,6 +964,12 @@ void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector)\n CPUState *cs = CPU(cpu);\n CPUM68KState *env = &cpu->env;\n \n+ if (level == 7 && env->pending_level != 7) {\n+ env->nmi_pending = true;\n+ } else if (level != 7) {\n+ env->nmi_pending = false;\n+ }\n+\n env->pending_level = level;\n env->pending_vector = vector;\n if (level) {\n@@ -964,6 +990,106 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n int ret;\n target_ulong page_size;\n \n+ if (qemu_access_type == MMU_INST_FETCH) {\n+ access_type = ACCESS_CODE;\n+ } else {\n+ access_type = ACCESS_DATA;\n+ if (qemu_access_type == MMU_DATA_STORE) {\n+ access_type |= ACCESS_STORE;\n+ }\n+ }\n+\n+ /* Decode explicit Function Codes from moves instructions */\n+ if (mmu_idx >= MMU_MOVES_FC_BASE) {\n+ uint8_t fc = mmu_idx - MMU_MOVES_FC_BASE;\n+ access_type |= (fc << 8); /* Pack explicit FC into access type */\n+ if (fc != 1 && fc != 2) {\n+ access_type |= ACCESS_SUPER;\n+ }\n+ } else {\n+ /* Standard memory accesses map logically to normal M68K FCs */\n+ if (mmu_idx == MMU_KERNEL_IDX) {\n+ access_type |= ACCESS_SUPER;\n+ access_type |= ((qemu_access_type == MMU_INST_FETCH ? 6 : 5) << 8);\n+ } else {\n+ access_type |= ((qemu_access_type == MMU_INST_FETCH ? 2 : 1) << 8);\n+ }\n+ }\n+\n+ if (env->custom_mmu_get_physical_address) {\n+ hwaddr custom_page_size;\n+\n+ /* Delegate translation to external board-specific MMU if registered */\n+ ret = env->custom_mmu_get_physical_address(env, &physical, &prot,\n+ address, access_type,\n+ &custom_page_size);\n+\n+ if (likely(ret == 0)) {\n+ tlb_set_page(cs, address & TARGET_PAGE_MASK,\n+ physical & TARGET_PAGE_MASK, prot,\n+ mmu_idx, custom_page_size);\n+ return true;\n+ }\n+\n+ if (probe) {\n+ return false;\n+ }\n+\n+ /* page fault */\n+ cs->exception_index = EXCP_ACCESS;\n+ env->mmu.ar = address;\n+\n+ if (m68k_feature(env, M68K_FEATURE_M68040)) {\n+ env->mmu.ssw = M68K_ATC_040;\n+ switch (size) {\n+ case 1:\n+ env->mmu.ssw |= M68K_BA_SIZE_BYTE;\n+ break;\n+ case 2:\n+ env->mmu.ssw |= M68K_BA_SIZE_WORD;\n+ break;\n+ case 4:\n+ env->mmu.ssw |= M68K_BA_SIZE_LONG;\n+ break;\n+ }\n+ env->mmu.ssw |= M68K_TM_040_DATA;\n+ } else {\n+ /* M68020/030 Special Status Word (SSW) */\n+ uint16_t ssw = 0x0100; /* DF - Data Fault */\n+ switch (size) {\n+ case 1:\n+ ssw |= 0x0010;\n+ break;\n+ case 2:\n+ ssw |= 0x0020;\n+ break;\n+ case 3:\n+ ssw |= 0x0030;\n+ break;\n+ case 4:\n+ ssw |= 0x0000;\n+ break;\n+ }\n+ if (qemu_access_type != MMU_DATA_STORE) {\n+ ssw |= 0x0040; /* RW - Read */\n+ }\n+ /* Function Code */\n+ uint8_t fc;\n+ if (mmu_idx >= MMU_MOVES_FC_BASE) {\n+ fc = mmu_idx - MMU_MOVES_FC_BASE;\n+ } else {\n+ if (mmu_idx == MMU_KERNEL_IDX) {\n+ fc = (qemu_access_type == MMU_INST_FETCH) ? 6 : 5;\n+ } else {\n+ fc = (qemu_access_type == MMU_INST_FETCH) ? 2 : 1;\n+ }\n+ }\n+ ssw |= (fc & 7);\n+ env->mmu.ssw = ssw;\n+ }\n+ cpu_loop_exit_restore(cs, retaddr);\n+ }\n+\n if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {\n /* MMU disabled */\n tlb_set_page(cs, address & TARGET_PAGE_MASK,\ndiff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c\nindex 8148a8852e..84d5270767 100644\n--- a/target/m68k/op_helper.c\n+++ b/target/m68k/op_helper.c\n@@ -1,3 +1,4 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n /*\n * M68K helper routines\n *\n@@ -25,6 +26,7 @@\n #include \"qemu/plugin.h\"\n \n #if !defined(CONFIG_USER_ONLY)\n+#include \"system/runstate.h\"\n \n static void cf_rte(CPUM68KState *env)\n {\n@@ -73,6 +75,12 @@ throwaway:\n case 7:\n sp += 52;\n break;\n+ case 0xa: /* Short Bus Cycle Fault (Format 0xA) */\n+ sp += 32 - 8; /* 32 bytes total - 8 bytes header = 24 bytes */\n+ break;\n+ case 0xb: /* Long Bus Cycle Fault (Format 0xB) */\n+ sp += 92 - 8; /* 92 bytes total - 8 bytes header = 84 bytes */\n+ break;\n }\n }\n env->aregs[7] = sp;\n@@ -342,56 +350,80 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw)\n switch (cs->exception_index) {\n case EXCP_ACCESS:\n if (env->mmu.fault) {\n- cpu_abort(cs, \"DOUBLE MMU FAULT\\n\");\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"M68K: Double MMU Fault. Halting CPU and requesting reset.\\n\");\n+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);\n+ cs->halted = 1;\n+ cs->exception_index = EXCP_HLT;\n+ cpu_loop_exit(cs);\n }\n env->mmu.fault = true;\n- /* push data 3 */\n- sp -= 4;\n- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n- /* push data 2 */\n- sp -= 4;\n- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n- /* push data 1 */\n- sp -= 4;\n- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n- /* write back 1 / push data 0 */\n- sp -= 4;\n- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n- /* write back 1 address */\n- sp -= 4;\n- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n- /* write back 2 data */\n- sp -= 4;\n- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n- /* write back 2 address */\n- sp -= 4;\n- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n- /* write back 3 data */\n- sp -= 4;\n- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n- /* write back 3 address */\n- sp -= 4;\n- cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);\n- /* fault address */\n- sp -= 4;\n- cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);\n- /* write back 1 status */\n- sp -= 2;\n- cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n- /* write back 2 status */\n- sp -= 2;\n- cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n- /* write back 3 status */\n- sp -= 2;\n- cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n- /* special status word */\n- sp -= 2;\n- cpu_stw_be_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0);\n- /* effective address */\n- sp -= 4;\n- cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);\n-\n- do_stack_frame(env, &sp, 7, oldsr, 0, env->pc);\n+\n+ if (m68k_feature(env, M68K_FEATURE_M68040)) {\n+ /* push data 3 */\n+ sp -= 4;\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ /* push data 2 */\n+ sp -= 4;\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ /* push data 1 */\n+ sp -= 4;\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ /* write back 1 / push data 0 */\n+ sp -= 4;\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ /* write back 1 address */\n+ sp -= 4;\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ /* write back 2 data */\n+ sp -= 4;\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ /* write back 2 address */\n+ sp -= 4;\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ /* write back 3 data */\n+ sp -= 4;\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ /* write back 3 address */\n+ sp -= 4;\n+ cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);\n+ /* fault address */\n+ sp -= 4;\n+ cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);\n+ /* write back 1 status */\n+ sp -= 2;\n+ cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ /* write back 2 status */\n+ sp -= 2;\n+ cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ /* write back 3 status */\n+ sp -= 2;\n+ cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ /* special status word */\n+ sp -= 2;\n+ cpu_stw_be_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0);\n+ /* effective address */\n+ sp -= 4;\n+ cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);\n+\n+ do_stack_frame(env, &sp, 7, oldsr, 0, env->pc);\n+ } else {\n+ /* M68020 Long Bus Cycle Fault (Format 0xB) */\n+ /*\n+ * 84 bytes of internal state are pushed before the generic\n+ * 8-byte header\n+ */\n+ sp -= 84;\n+ for (int i = 0; i < 84; i += 4) {\n+ cpu_stl_be_mmuidx_ra(env, sp + i, 0, MMU_KERNEL_IDX, 0);\n+ }\n+ /* Offset 0x02 from internal frame: SSW */\n+ cpu_stw_be_mmuidx_ra(env, sp + 2, env->mmu.ssw, MMU_KERNEL_IDX, 0);\n+ /* Offset 0x08 from internal frame: Fault Address */\n+ cpu_stl_be_mmuidx_ra(env, sp + 8, env->mmu.ar, MMU_KERNEL_IDX, 0);\n+\n+ do_stack_frame(env, &sp, 0xb, oldsr, 0, env->pc);\n+ }\n env->mmu.fault = false;\n if (qemu_loglevel_mask(CPU_LOG_INT)) {\n qemu_log(\" \"\n@@ -437,7 +469,9 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw)\n \n env->aregs[7] = sp;\n /* Jump to vector. */\n+ env->mmu.fault = true;\n env->pc = cpu_ldl_be_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);\n+ env->mmu.fault = false;\n \n do_plugin_vcpu_interrupt_cb(cs, last_pc);\n }\n@@ -509,26 +543,46 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,\n if (access_type != MMU_DATA_STORE) {\n env->mmu.ssw |= M68K_RW_040;\n }\n-\n- env->mmu.ar = addr;\n-\n- cs->exception_index = EXCP_ACCESS;\n- cpu_loop_exit(cs);\n+ } else if (m68k_feature(env, M68K_FEATURE_M68020)) {\n+ /*\n+ * M68020 Long Bus Cycle Fault (Format 0xB).\n+ * The Motorola 68020 hardware intrinsically generates a physical\n+ * Bus Error exception whenever the system bus flags a transaction\n+ * timeout or failure (e.g., attempting to read an unpopulated bus\n+ * address). This natively injects the EXCP_ACCESS cycle to build\n+ * the generic 84-byte exception stack frame.\n+ */\n+ env->mmu.ssw = 0;\n+ if (access_type == MMU_INST_FETCH) {\n+ env->mmu.ssw |= 0x1000;\n+ } else if (access_type == MMU_DATA_STORE) {\n+ env->mmu.ssw |= 0x0040;\n+ } else {\n+ env->mmu.ssw |= 0x0080;\n+ }\n+ } else {\n+ /*\n+ * Older architectures (e.g. 68000) do not currently support\n+ * hardware-injected transaction failures in QEMU.\n+ */\n+ return;\n }\n+\n+ env->mmu.ar = addr;\n+ cs->exception_index = EXCP_ACCESS;\n+ cpu_loop_exit(cs);\n }\n \n bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request)\n {\n CPUM68KState *env = cpu_env(cs);\n \n- if (interrupt_request & CPU_INTERRUPT_HARD\n- && ((env->sr & SR_I) >> SR_I_SHIFT) < env->pending_level) {\n- /*\n- * Real hardware gets the interrupt vector via an IACK cycle\n- * at this point. Current emulated hardware doesn't rely on\n- * this, so we provide/save the vector when the interrupt is\n- * first signalled.\n- */\n+ if (env->nmi_pending) {\n+ env->nmi_pending = false;\n+ cs->exception_index = env->pending_vector;\n+ do_interrupt_m68k_hardirq(env);\n+ return true;\n+ } else if (((env->sr & SR_I) >> SR_I_SHIFT) < env->pending_level) {\n cs->exception_index = env->pending_vector;\n do_interrupt_m68k_hardirq(env);\n return true;\ndiff --git a/target/m68k/translate.c b/target/m68k/translate.c\nindex abc1c79f3c..d6fcd6c4d9 100644\n--- a/target/m68k/translate.c\n+++ b/target/m68k/translate.c\n@@ -1,3 +1,4 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n /*\n * m68k translation\n *\n@@ -163,10 +164,12 @@ static void do_writebacks(DisasContext *s)\n #define IS_USER(s) 1\n #else\n #define IS_USER(s) (!(s->base.tb->flags & TB_FLAGS_MSR_S))\n-#define SFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_SFC_S) ? \\\n- MMU_KERNEL_IDX : MMU_USER_IDX)\n-#define DFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_DFC_S) ? \\\n- MMU_KERNEL_IDX : MMU_USER_IDX)\n+#define SFC_INDEX(s) (MMU_MOVES_FC_BASE + \\\n+ (((s)->base.tb->flags & TB_FLAGS_SFC_S) >> \\\n+ TB_FLAGS_SFC_S_BIT))\n+#define DFC_INDEX(s) (MMU_MOVES_FC_BASE + \\\n+ (((s)->base.tb->flags & TB_FLAGS_DFC_S) >> \\\n+ TB_FLAGS_DFC_S_BIT))\n #endif\n \n typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);\n@@ -5364,11 +5367,19 @@ DISAS_INSN(frestore)\n gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);\n return;\n }\n- if (m68k_feature(s->env, M68K_FEATURE_M68040)) {\n+ if (m68k_feature(s->env, M68K_FEATURE_M68040) ||\n+ m68k_feature(s->env, M68K_FEATURE_FPU)) {\n SRC_EA(env, addr, OS_LONG, 0, NULL);\n- /* FIXME: check the state frame */\n+ if (m68k_feature(s->env, M68K_FEATURE_M68040)) {\n+ /* FIXME: check the state frame */\n+ } else {\n+ /*\n+ * 68881/68882 FRESTORE: read the state frame\n+ * (NULL frame is 4 bytes)\n+ */\n+ }\n } else {\n- disas_undef(env, s, insn);\n+ disas_undef_fpu(env, s, insn);\n }\n }\n \n@@ -5383,8 +5394,12 @@ DISAS_INSN(fsave)\n /* always write IDLE */\n TCGv idle = tcg_constant_i32(0x41000000);\n DEST_EA(env, insn, OS_LONG, idle, NULL);\n+ } else if (m68k_feature(s->env, M68K_FEATURE_FPU)) {\n+ /* 68881/68882 FSAVE: always write NULL frame */\n+ TCGv null_frame = tcg_constant_i32(0x00000000);\n+ DEST_EA(env, insn, OS_LONG, null_frame, NULL);\n } else {\n- disas_undef(env, s, insn);\n+ disas_undef_fpu(env, s, insn);\n }\n }\n #endif\n", "prefixes": [ "1/7" ] }