Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2232091/?format=api
{ "id": 2232091, "url": "http://patchwork.ozlabs.org/api/patches/2232091/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/720bfb24-09c1-4404-90a2-4601469cd5b5@oss.qualcomm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<720bfb24-09c1-4404-90a2-4601469cd5b5@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-05-02T14:57:02", "name": "[V2,to-be-committed,RISC-V,PR,tree-optimization/109038] Recognize shifts+rotate as simple shift in some cases", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6799b851a6e3ff17760c002769d21f6c7c2ce55b", "submitter": { "id": 92310, "url": "http://patchwork.ozlabs.org/api/people/92310/?format=api", "name": "Jeffrey Law", "email": "jeffrey.law@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/720bfb24-09c1-4404-90a2-4601469cd5b5@oss.qualcomm.com/mbox/", "series": [ { "id": 502538, "url": "http://patchwork.ozlabs.org/api/series/502538/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502538", "date": "2026-05-02T14:57:02", "name": "[V2,to-be-committed,RISC-V,PR,tree-optimization/109038] Recognize shifts+rotate as simple shift in some cases", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502538/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232091/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232091/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=Ea3K0zwT;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=hdqkNpXh;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=Ea3K0zwT;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=hdqkNpXh", "sourceware.org; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "sourceware.org;\n spf=pass smtp.mailfrom=oss.qualcomm.com", "server2.sourceware.org;\n arc=none smtp.remote-ip=205.220.180.131" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g79xb0D8Lz1yGq\n\tfor <incoming@patchwork.ozlabs.org>; Sun, 03 May 2026 00:57:38 +1000 (AEST)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id D91094B920F7\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 2 May 2026 14:57:36 +0000 (GMT)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n by sourceware.org (Postfix) with ESMTPS id 8FA084BB58CF\n for <gcc-patches@gcc.gnu.org>; Sat, 2 May 2026 14:57:07 +0000 (GMT)", "from pps.filterd (m0279869.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 642BSEQk1220555\n for <gcc-patches@gcc.gnu.org>; Sat, 2 May 2026 14:57:07 GMT", "from mail-dy1-f198.google.com (mail-dy1-f198.google.com\n [74.125.82.198])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dw895h66m-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <gcc-patches@gcc.gnu.org>; Sat, 02 May 2026 14:57:06 +0000 (GMT)", "by mail-dy1-f198.google.com with SMTP id\n 5a478bee46e88-2edfb206494so1360103eec.0\n for <gcc-patches@gcc.gnu.org>; Sat, 02 May 2026 07:57:06 -0700 (PDT)", "from [172.31.0.17] ([136.38.201.137])\n by smtp.gmail.com with ESMTPSA id\n 5a478bee46e88-2ee3bf6812asm8490038eec.28.2026.05.02.07.57.03\n for <gcc-patches@gcc.gnu.org>\n (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128);\n Sat, 02 May 2026 07:57:03 -0700 (PDT)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org D91094B920F7", "OpenDKIM Filter v2.11.0 sourceware.org 8FA084BB58CF" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org 8FA084BB58CF", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 8FA084BB58CF", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1777733827; cv=none;\n b=PG5tW90OOpuFi+mFImyNsYHZ4XU1M3E5Y+Eb9L5C9qpeRj+p74UjwfXRm0rIfilYWRcFdUSIk7slGMqLyh+ms3SbJfk4T770oFeiLMC81FEynagSgug3tS0rqQujzhXA3h8izGOtIF73ui6+AT6DKnyUrp8+GJAs4a5Vg7M+ipc=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1777733827; c=relaxed/simple;\n bh=EODNnM+VZIIJa/rkTppO95RLNGHrGNzOThZmdVxUJ28=;\n h=DKIM-Signature:DKIM-Signature:Message-ID:Date:MIME-Version:To:\n From:Subject;\n b=NQ9fA6kJuHt1SIcuBlILQdXUjC1f5Caop9+mKmFHtOJDCgvJryAaaZok4x1ABr5blbRXmqmrzaY1K3t103mUkSAdUDttpTCI+CI58Nl/r8+hXlUDq05ujizx5J4lq+sbSVdSqw+iggtVMjN1G+2U2p3s2qVcdvXdgUfWehICuRE=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n content-type:date:from:message-id:mime-version:subject:to; s=\n qcppdkim1; bh=0YhcWxzSkqQ0wqX5QOqiytkCSC87EAcnC0WvwhBnaYg=; b=Ea\n 3K0zwTHKJDgdAbUPAgX97pFJzTyBL1pRYrwRWLMcRpBsB0UiQF3CGevIzWbtum4k\n LQpxmaYvoDo1oat8z7QS0DUNJncX7+2wfjmsbzwEYKC0Ww2+b+KdluGZYvxGTrdA\n xbf6mAIKZc108D4Ptm7i+Be3JJhGrWyhppxMTleSsCZ/wDBbbpvVyVDzLluuvS0x\n VpBJa4AwEGAYtm1YutqqqdX7/fo4HifWlgTg9vD0lh/zTwnYSzaO2vruJtoumG46\n EtyKzEh+3v8x1TuP0x6KGY2DJ3uyuQ3w+wOKZ5kV879HaDvz/vJncN6ISqHlUuI0\n KQ6kX2Ws2mwv5AiBTg6g==", "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1777733826; x=1778338626; darn=gcc.gnu.org;\n h=subject:from:to:content-language:user-agent:mime-version:date\n :message-id:from:to:cc:subject:date:message-id:reply-to;\n bh=0YhcWxzSkqQ0wqX5QOqiytkCSC87EAcnC0WvwhBnaYg=;\n b=hdqkNpXhpSL0LwPdNeSCb5FOZg2Lo7t42xiygXR8c2JoTlhItzK2DnCgO53d0nL/Zw\n uESfAchlYHC2A4JWt0ObGNeSBO1D5kcvlyBDOQs5Y4PkY43wEvKzZzzAZ3XgXnwN/2eE\n QEnhuzLwIDSs06i4mJ+Oogr3QzIth2zgrejXSv0WcG1GVPeMBimA3d0grmOzKkBiswCf\n SD6dYjSlVVw6n5HXzIsX7lNOw0kCK/WwJYX8xUxvodWHLciwFOSI+ZrxuxK/g7rYSa2d\n 7V+oAYqJ8uAOI6smVQPqv8ZKcFDdaa+lIFCWFyO2yvkzxk0RoRiudse4NpbO5OC/MVQS\n r3lQ==" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777733826; x=1778338626;\n h=subject:from:to:content-language:user-agent:mime-version:date\n :message-id:x-gm-gg:x-gm-message-state:from:to:cc:subject:date\n :message-id:reply-to;\n bh=0YhcWxzSkqQ0wqX5QOqiytkCSC87EAcnC0WvwhBnaYg=;\n b=mOJfidlKqf2XWz3tBTGuZkr67CPUSNnoXUrkx1DGITurYdarVbVevoKx9tP4FPyZXM\n u3OBq0rqlnR4Z2EYvjP4lFbap+Irnx8z7ELOy996P/e7JDutgRkXZS7+2Qu0yfwCte4u\n PQcl7y+iV9lSs+HiiFlf26A1zmeFurqE4Q9QgvaITdhDWjpY6lLuoVJDdpnmM+PT0/P1\n rbDEF2xlk9VIMQZ0QC8Nn3d3R/wVZlu7tVVVOeju/XNEqFpITbA7/lj+Pedn1mehenhS\n L1BUo1X4ds3NP4xTMvax+Fse3TBTz2uelTLR8ju40lYH+y24nuJR32LMc0XlUZ7KhsEr\n /DqA==", "X-Gm-Message-State": "AOJu0Yy4ik9WLdmc8Ps202fzPi/El/S0svY0X3fNC0cS/ep0kd880mYY\n JkpIyp0gKhvEBcQ0FD/Ad3rJRVQU26f0JH/4KxRYuBpuzXrda9Bx9Mh0L8P4QU4EyT+5UhF28Iq\n p9be1wWaAkXJzCKzHKQAPlKW8iesoxXCzRUA3JNHV9oTodqp0MLc81f8zOLd4h/3nIgun", "X-Gm-Gg": "AeBDieuBvXZnnaYucsMQfQ5msGOf9GHYozcQr7HxInswMwDZPLa7gLw5flIv1i28SvM\n LYbJLYGNesWiAfAV8rI0d6bP8ddR4OJQhgwMS/pCxOfqMt+mWnnb5EmiSXBvV5vL+pzfCMIwqov\n KlxgaVJrhNSl7qMbSDDEn/olgzoIEbGoSIH/KSN+4+SkdWAa8VSd9L4mp8rhKrtbTdSPXz3Np1j\n 2KQS1WCfLhXjQzoar6EBo+LiV/ZHTxuyONyxzSts9IcsMRTspegMG5ZRBLncaXSpgaTEJ5J8ALX\n KDGlabxr1tesWk9ugskDcpoduoA3dJwC9lzgh0IW+APTm537YyiLXr0SAvF5vPEmlIMYw6AzsRM\n BULH8GF5WqXcqQXF1XZb3gIoZ7t64zFU04FEEm7HiPOOvOxrmWTUP0v41wmEn", "X-Received": [ "by 2002:a05:693c:2d83:b0:2ed:e16:6b4b with SMTP id\n 5a478bee46e88-2efba5a5b73mr1441079eec.33.1777733825245;\n Sat, 02 May 2026 07:57:05 -0700 (PDT)", "by 2002:a05:693c:2d83:b0:2ed:e16:6b4b with SMTP id\n 5a478bee46e88-2efba5a5b73mr1441061eec.33.1777733824359;\n Sat, 02 May 2026 07:57:04 -0700 (PDT)" ], "Content-Type": "multipart/mixed; boundary=\"------------6Yb3a0ioWeZc75oUL0d0aKp0\"", "Message-ID": "<720bfb24-09c1-4404-90a2-4601469cd5b5@oss.qualcomm.com>", "Date": "Sat, 2 May 2026 08:57:02 -0600", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "Content-Language": "en-US", "To": "'GCC Patches' <gcc-patches@gcc.gnu.org>", "From": "Jeffrey Law <jeffrey.law@oss.qualcomm.com>", "Subject": "[V2][to-be-committed][RISC-V][PR tree-optimization/109038] Recognize\n shifts+rotate as simple shift in some cases", "X-Authority-Analysis": "v=2.4 cv=F6BnsKhN c=1 sm=1 tr=0 ts=69f610c2 cx=c_pps\n a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=leENTQSJUyA7Li62aUsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=7HWjmwRNFuBC6MNrEPoA:9 a=B2y7HmGcmWMA:10 a=bBxd6f-gb0O0v-kibOvt:22", "X-Proofpoint-GUID": "gVbngZhwzi9ua6Vq35osh_DCdOCN_7CX", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNTAyMDE1MCBTYWx0ZWRfX3Zy1IRu6uYwk\n RelsAefgyJ7lYWSoge2kn4CC9ZixuEbKTiJT53Qi4CQh5ENhRj40QNxoRgSm7SSJml7NtztJgd3\n Ufi8Rc5Wy0W3tzRKrycUvzrSYozW8zos6niexRYSWf1mJmGjpIUcpD215HUJio3JDH/dPluMZDY\n 4bjy+i3R2kJevKlYOEWUXS/CHgbHEDm/FaW2nLhQBnY8hoQG7KCfXqq8zz89EyLLJxEsJZ0sgZ1\n AEj+vhCRZvD5DImKsD9xFdDe9q0R2u4ZjZrBWII5+JK0fu4aE4FQ8E6vG/CyVnRpSK4Dny5+Pya\n g0z9UXGRaUmDcx/N0luOqHBpVrrb05pvS1tI//n4jGi/4A+mIbTA/u9l3awhsZqqHOMlWuBohHd\n zJsVEyZhUNwNr3lhNqM5yDEQCTy5PvNhs9MtwZXIMQVTv9VYFrI8cq5Wt973gj+HqWLzooVY+Rj\n XiVq1LRoRnzZOzxDBHA==", "X-Proofpoint-ORIG-GUID": "gVbngZhwzi9ua6Vq35osh_DCdOCN_7CX", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-05-02_04,2026-04-30_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 phishscore=0 priorityscore=1501 suspectscore=0 impostorscore=0\n malwarescore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605020150", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Either the pre-commit CI system has gotten more flakey or I've been \nexceptionally good at finding windows where it doesn't have a good \nbaseline. Either way yesterday's patch for shifts+rotate -> shift \npattern didn't get tested. So re-posting to get it rolling again.\n\n--\n\nConsider this test from pr109038:\n\nunsigned\nfoo (unsigned int a)\n{\n unsigned int b = a & 0x00FFFFFF;\n unsigned int c = ((b & 0x000000FF) << 8\n | (b & 0x0000FF00) << 8\n | (b & 0x00FF0000) << 8\n | (b & 0xFF000000) >> 24);\n return c;\n}\n\nWe currently generate something like this for rv64gcbv:\n\n slli a0,a0,40\n srli a0,a0,40\n roriw a0,a0,24\n ret\n\nTwo key points. The first two shifts clear the upper 40 bits. The roriw \nis a rotation of the low 32 bits by 24 positions with a sign extension \nfrom bit 31 into bits 32..63.\n\nSo we're going to have bit 31 defining bits 32..63 after the rotation \nand the low 8 bits will be clear. So we can just do\n\n slliw a0,a0,8\n\n\n\nNote that doesn't even strictly need bitmanip, though the original \nsequence did. The mask is always going to be a consecutive run of on \nbits including bits 31..63. The number of bits off in the mask must be \n32 - rotate count. Put it all together and you get a nice slliw.\n\nEssentially it's a 3->1 combination, so a define_insn is sufficient.\n\nAn earlier version of this patch has been in my tester for weeks, so the \nusual testing has been performed. But that version was meaningfully \ndifferent (left a trailing andi and was impemented as a splitter). So I \nconsider most of that testing invalid. This version did go through \nriscv32-elf and riscv64-elf without regressions and I'll be waiting on \nthe upstream pre-commit to render a verdict.", "diff": "diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md\nindex c9561b0b6228..30046e1fb69e 100644\n--- a/gcc/config/riscv/bitmanip.md\n+++ b/gcc/config/riscv/bitmanip.md\n@@ -1441,3 +1441,25 @@ (define_split\n [(set (match_dup 4) (and:X (not:X (match_dup 2)) (match_dup 1)))\n (set (match_dup 0) (xor:X (match_dup 4) (match_dup 3)))])\n \n+\n+;; This would typically be a 3 instruction sequence. Two shifts plus\n+;; the rotate. But with bits 32..63 defined by value in bit 31, we can\n+;; use the sign extending shifts/rotates. And with the number of low bits\n+;; masked off by the AND matching the final shift count we can turn this mess\n+;; into simple \"w\" mode left shift.\n+(define_insn \"rotate_with_masking_to_shift\"\n+ [(set (match_operand:DI 0 \"register_operand\" \"=r\")\n+ (sign_extend:DI (and:SI (rotatert:SI (match_operand:SI 1 \"register_operand\" \"r\")\n+ (match_operand 2 \"const_int_operand\" \"i\"))\n+ (match_operand 3 \"consecutive_bits_operand\" \"i\"))))]\n+ \"(TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)\n+ && INTVAL (operands[2]) < 32\n+ && (INTVAL (operands[3]) & HOST_WIDE_INT_C (0xffffffff80000000)) == HOST_WIDE_INT_C (0xffffffff80000000)\n+ && ctz_hwi (INTVAL (operands[3])) == 32 - INTVAL (operands[2]))\"\n+{\n+ operands[2] = GEN_INT (32 - INTVAL (operands[2]));\n+ return \"slliw\\t%0,%1,%2\";\n+}\n+ [(set_attr \"type\" \"shift\")\n+ (set_attr \"mode\" \"DI\")])\n+\ndiff --git a/gcc/testsuite/gcc.target/riscv/pr109038.c b/gcc/testsuite/gcc.target/riscv/pr109038.c\nnew file mode 100644\nindex 000000000000..6a4e82673fb9\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/pr109038.c\n@@ -0,0 +1,21 @@\n+/* { dg-do compile } */\n+/* { dg-additional-options \"-march=rv64gcb_zicond -mabi=lp64d\" { target rv64 } } */\n+/* { dg-additional-options \"-march=rv32gcb_zicond -mabi=ilp32\" { target rv32 } } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\" } } */\n+\n+unsigned\n+foo (unsigned int a)\n+{\n+ unsigned int b = a & 0x00FFFFFF;\n+ unsigned int c = ((b & 0x000000FF) << 8\n+ | (b & 0x0000FF00) << 8\n+ | (b & 0x00FF0000) << 8\n+ | (b & 0xFF000000) >> 24);\n+ return c;\n+}\n+\n+/* These don't have the trailing \"w\" so that they work for\n+ both rv32 and rv64. */\n+/* { dg-final { scan-assembler-not \"srli\" } } */\n+/* { dg-final { scan-assembler-not \"rori\" } } */\n+/* { dg-final { scan-assembler-times \"sll\" 1 } } */\n", "prefixes": [ "V2", "to-be-committed", "RISC-V", "PR", "tree-optimization/109038" ] }