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GET /api/patches/2231492/?format=api
{ "id": 2231492, "url": "http://patchwork.ozlabs.org/api/patches/2231492/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260501-ls7a-bridge-fixes-v2-1-69fa93683805@rong.moe/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260501-ls7a-bridge-fixes-v2-1-69fa93683805@rong.moe>", "list_archive_url": null, "date": "2026-04-30T18:45:23", "name": "[v2] PCI: loongson: Do not ignore downstream devices on external bridges", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fb5791c7563d8e255b359775611cfde9048b9792", "submitter": { "id": 87882, "url": "http://patchwork.ozlabs.org/api/people/87882/?format=api", "name": "Rong Zhang", "email": "i@rong.moe" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260501-ls7a-bridge-fixes-v2-1-69fa93683805@rong.moe/mbox/", "series": [ { "id": 502360, "url": "http://patchwork.ozlabs.org/api/series/502360/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=502360", "date": "2026-04-30T18:45:23", "name": "[v2] PCI: loongson: Do not ignore downstream devices on external bridges", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502360/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231492/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231492/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-53534-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=rong.moe header.i=i@rong.moe header.a=rsa-sha256\n header.s=zmail2048 header.b=Tg69EmOI;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.232.135.74; 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arc=pass smtp.client-ip=136.143.188.15", "i=1; mx.zohomail.com;\n\tdkim=pass header.i=rong.moe;\n\tspf=pass smtp.mailfrom=i@rong.moe;\n\tdmarc=pass header.from=<i@rong.moe>" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1777574736;\n\ts=zmail2048; d=rong.moe; i=i@rong.moe;\n\th=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:To:To:Cc:Cc:Reply-To;\n\tbh=qhcUzWz+e0eHqHXsaKs+FfS0uIQ3j8wCK538/jEKh44=;\n\tb=Tg69EmOIcZR+jtONoO8C1q7jrxMY+8LLXBC//b6w/D0jipOxqkOlUUXYFvSzk1nK\n\t1Z0hRyVV8ZHVpwL9hNGg8I3fcK54EPX/08OMxsGB/XS23OiE0wbucZV6/0dH01h43jy\n\t2t16kM+2RdqE9sxJ2Z5FSX9fDsTnc+8ba42NurplT7VjhtQNKgcC2/h4LwAFpS4gjgv\n\t4uPseNJjWawzFJPPvZcf4eEcPrV/3Sa9JYMxfee6cb6c+4H0lYBWLt7HRM6+7bnUU9K\n\tPBYBVEN/5jYZF4zvGvGNTnUwIwbjy4yI8J3RcON9R0OC5Q8llwe9OC0ZBy+ELvCISyY\n\tvoKJP+lbHg==", "From": "Rong Zhang <i@rong.moe>", "Date": "Fri, 01 May 2026 02:45:23 +0800", "Subject": "[PATCH v2] PCI: loongson: Do not ignore downstream devices on\n external bridges", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260501-ls7a-bridge-fixes-v2-1-69fa93683805@rong.moe>", "X-B4-Tracking": "v=1; b=H4sIAEOj82kC/22NwQ6CMBBEf4Xs2ZpSoYIn/8NwaMsW1ig1XSQaw\n r9bMN48vszMmxkYIyHDKZsh4kRMYUigdhm43gwdCmoTg5JKy0JW4sZHI2ykNkWeXsiiMrUtC6O\n tVg7S7hFxC9Ls0nyZn/aKblxFa6MnHkN8b6dTvvZ+/vqPf8qFFAddSo+tz4135xiGbn8PCM2yL\n B8EFxLDwwAAAA==", "X-Change-ID": "20260408-ls7a-bridge-fixes-8a9b54a6b62c", "To": "Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Huacai Chen <chenhuacai@kernel.org>", "Cc": "linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n Jiaxun Yang <jiaxun.yang@flygoat.com>,\n \"Lain \\\"Fearyncess\\\" Yang\" <i@lain.vg>, Rong Zhang <i@rong.moe>", "X-Mailer": "b4 0.16-dev-7777e", "X-ZohoMailClient": "External" }, "content": "Loongson PCI host controllers have a hardware quirk that requires\nsoftware to ignore downstream devices with device number > 0 on the\ninternal bridges. The current implementation applies the workaround to\nall non-root buses, which breaks external bridges (e.g., PCIe switches)\nwith multiple downstream devices.\n\nFix it by only applying the workaround to internal bridges.\n\nTested on Loongson-LS3A4000-7A1000-NUC-SE, using AMD Promontory 21\nchipset add-in card [1].\n\n $ lspci -tnnnvvv\n -[0000:00]-+-00.0 Loongson Technology LLC 7A1000 Chipset Hyper Transport Bridge Controller [0014:7a00]\n +-00.1 Loongson Technology LLC 7A2000 Chipset Hyper Transport Bridge Controller [0014:7a10]\n +-03.0 Loongson Technology LLC 2K1000/2000 / 7A1000 Chipset Gigabit Ethernet Controller [0014:7a03]\n +-04.0 Loongson Technology LLC 2K1000 / 7A1000/2000 Chipset USB OHCI Controller [0014:7a24]\n +-04.1 Loongson Technology LLC 2K1000 / 7A1000/2000 Chipset USB EHCI Controller [0014:7a14]\n +-05.0 Loongson Technology LLC 2K1000 / 7A1000/2000 Chipset USB OHCI Controller [0014:7a24]\n +-05.1 Loongson Technology LLC 2K1000 / 7A1000/2000 Chipset USB EHCI Controller [0014:7a14]\n +-06.0 Loongson Technology LLC 7A1000 Chipset Vivante GC1000 GPU [0014:7a15]\n +-06.1 Loongson Technology LLC 2K1000 / 7A1000 Chipset Display Controller [0014:7a06]\n +-07.0 Loongson Technology LLC 2K1000/2000/3000 / 3B6000M / 7A1000/2000 Chipset HD Audio Controller [0014:7a07]\n +-08.0 Loongson Technology LLC 2K1000 / 7A1000 Chipset 3Gb/s SATA AHCI Controller [0014:7a08]\n +-08.1 Loongson Technology LLC 2K1000 / 7A1000 Chipset 3Gb/s SATA AHCI Controller [0014:7a08]\n +-08.2 Loongson Technology LLC 2K1000 / 7A1000 Chipset 3Gb/s SATA AHCI Controller [0014:7a08]\n +-09.0-[01]----00.0 Qualcomm Technologies, Inc QCNFA765 Wireless Network Adapter [17cb:1103]\n +-0a.0-[02]----00.0 Etron Technology, Inc. EJ188/EJ198 USB 3.0 Host Controller [1b6f:7052]\n +-0f.0-[03-08]----00.0-[04-08]--+-00.0-[05]----00.0 Shenzhen Longsys Electronics Co., Ltd. FORESEE XP1000 / Lexar Professional CFexpress Type B Gold series, NM620 PCIe NVME SSD (DRAM-less) [1d97:5216]\n | +-08.0-[06]----00.0 MAXIO Technology (Hangzhou) Ltd. NVMe SSD Controller MAP1202 (DRAM-less) [1e4b:1202]\n | +-0c.0-[07]----00.0 Advanced Micro Devices, Inc. [AMD] 600 Series Chipset USB 3.2 Controller [1022:43f7]\n | \\-0d.0-[08]----00.0 Advanced Micro Devices, Inc. [AMD] 600 Series Chipset SATA Controller [1022:43f6]\n \\-16.0 Loongson Technology LLC 7A1000 Chipset SPI Controller [0014:7a0b]\n\nFixes: 2410e3301fcc (\"PCI: loongson: Don't access non-existent devices\")\nLink: https://oshwhub.com/wesd/b650 [1]\nCo-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>\nSigned-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>\nCo-developed-by: Lain \"Fearyncess\" Yang <i@lain.vg>\nSigned-off-by: Lain \"Fearyncess\" Yang <i@lain.vg>\nSigned-off-by: Rong Zhang <i@rong.moe>\n---\nChanges in v2:\n- Squash into a single patch to prevent temporary build regressions,\n i.e., unused variable on non-MIPS builds (found by Sashiko)\n - https://sashiko.dev/#/patchset/20260409-ls7a-bridge-fixes-v1-0-3650fedf1afc%40rong.moe\n- Link to v1: https://patch.msgid.link/20260409-ls7a-bridge-fixes-v1-0-3650fedf1afc@rong.moe\n---\n drivers/pci/controller/pci-loongson.c | 31 ++++++++++++++++---------------\n 1 file changed, 16 insertions(+), 15 deletions(-)\n\n\n---\nbase-commit: 08d0d3466664000ba0670e0ef0d447f23459e0d4\nchange-id: 20260408-ls7a-bridge-fixes-8a9b54a6b62c\n\nThanks,\nRong", "diff": "diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c\nindex bc630ab8a283..de5e809a537d 100644\n--- a/drivers/pci/controller/pci-loongson.c\n+++ b/drivers/pci/controller/pci-loongson.c\n@@ -80,6 +80,18 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,\n DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,\n \t\t\tDEV_LS7A_LPC, system_bus_quirk);\n \n+static const struct pci_device_id loongson_internal_bridge_devids[] = {\n+\t{ PCI_VDEVICE(LOONGSON, DEV_LS2K_PCIE_PORT0) },\n+\t{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT0) },\n+\t{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT1) },\n+\t{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT2) },\n+\t{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT3) },\n+\t{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT4) },\n+\t{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT5) },\n+\t{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT6) },\n+\t{ 0, },\n+};\n+\n /*\n * Some Loongson PCIe ports have hardware limitations on their Maximum Read\n * Request Size. They can't handle anything larger than this. Sane\n@@ -92,24 +104,13 @@ static void loongson_set_min_mrrs_quirk(struct pci_dev *pdev)\n {\n \tstruct pci_bus *bus = pdev->bus;\n \tstruct pci_dev *bridge;\n-\tstatic const struct pci_device_id bridge_devids[] = {\n-\t\t{ PCI_VDEVICE(LOONGSON, DEV_LS2K_PCIE_PORT0) },\n-\t\t{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT0) },\n-\t\t{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT1) },\n-\t\t{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT2) },\n-\t\t{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT3) },\n-\t\t{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT4) },\n-\t\t{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT5) },\n-\t\t{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT6) },\n-\t\t{ 0, },\n-\t};\n \n \t/* look for the matching bridge */\n \twhile (!pci_is_root_bus(bus)) {\n \t\tbridge = bus->self;\n \t\tbus = bus->parent;\n \n-\t\tif (pci_match_id(bridge_devids, bridge)) {\n+\t\tif (pci_match_id(loongson_internal_bridge_devids, bridge)) {\n \t\t\tif (pcie_get_readrq(pdev) > 256) {\n \t\t\t\tpci_info(pdev, \"limiting MRRS to 256\\n\");\n \t\t\t\tpcie_set_readrq(pdev, 256);\n@@ -230,11 +231,11 @@ static void __iomem *pci_loongson_map_bus(struct pci_bus *bus,\n \tstruct loongson_pci *priv = pci_bus_to_loongson_pci(bus);\n \n \t/*\n-\t * Do not read more than one device on the bus other than\n-\t * the host bus.\n+\t * Do not read more than one device on the internal bridges.\n \t */\n \tif ((priv->data->flags & FLAG_DEV_FIX) && bus->self) {\n-\t\tif (!pci_is_root_bus(bus) && (device > 0))\n+\t\tif (!pci_is_root_bus(bus) && (device > 0) &&\n+\t\t pci_match_id(loongson_internal_bridge_devids, bus->self))\n \t\t\treturn NULL;\n \t}\n \n", "prefixes": [ "v2" ] }