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GET /api/patches/2231416/?format=api
{ "id": 2231416, "url": "http://patchwork.ozlabs.org/api/patches/2231416/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430172204.1006673-31-pbonzini@redhat.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430172204.1006673-31-pbonzini@redhat.com>", "list_archive_url": null, "date": "2026-04-30T17:21:36", "name": "[PULL,30/58] whpx: i386: kernel-irqchip=off fixes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "43c129a3bf01c246b07be19f74fa0e2a66f092e5", "submitter": { "id": 2701, "url": "http://patchwork.ozlabs.org/api/people/2701/?format=api", "name": "Paolo Bonzini", "email": "pbonzini@redhat.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430172204.1006673-31-pbonzini@redhat.com/mbox/", "series": [ { "id": 502347, "url": "http://patchwork.ozlabs.org/api/series/502347/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502347", "date": "2026-04-30T17:21:16", "name": "[PULL,01/58] pythondeps: bump to meson 1.11.1", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502347/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231416/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231416/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=CHE6oF9V;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=google header.b=GRHl9tyn;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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After fixing this,\nWindows boots with kernel-irqchip=off.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\nLink: https://lore.kernel.org/r/20260422214225.2242-9-mohamed@unpredictable.fr\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>\n---\n include/system/whpx-common.h | 1 +\n target/i386/whpx/whpx-all.c | 43 +++++-------------------------------\n 2 files changed, 7 insertions(+), 37 deletions(-)", "diff": "diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h\nindex 04289afd973..3406c20fec0 100644\n--- a/include/system/whpx-common.h\n+++ b/include/system/whpx-common.h\n@@ -4,6 +4,7 @@\n \n struct AccelCPUState {\n bool window_registered;\n+ int window_priority;\n bool interruptable;\n bool ready_for_pic_interrupt;\n uint64_t tpr;\ndiff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex 73e351d895d..d470c5b9d37 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -22,6 +22,8 @@\n #include \"qemu/main-loop.h\"\n #include \"hw/core/boards.h\"\n #include \"hw/intc/ioapic.h\"\n+#include \"hw/intc/i8259.h\"\n+#include \"hw/i386/x86.h\"\n #include \"hw/i386/apic_internal.h\"\n #include \"qemu/error-report.h\"\n #include \"qapi/error.h\"\n@@ -390,28 +392,6 @@ static int whpx_set_tsc(CPUState *cpu)\n return 0;\n }\n \n-/*\n- * The CR8 register in the CPU is mapped to the TPR register of the APIC,\n- * however, they use a slightly different encoding. Specifically:\n- *\n- * APIC.TPR[bits 7:4] = CR8[bits 3:0]\n- *\n- * This mechanism is described in section 10.8.6.1 of Volume 3 of Intel 64\n- * and IA-32 Architectures Software Developer's Manual.\n- *\n- * The functions below translate the value of CR8 to TPR and vice versa.\n- */\n-\n-static uint64_t whpx_apic_tpr_to_cr8(uint64_t tpr)\n-{\n- return tpr >> 4;\n-}\n-\n-static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8)\n-{\n- return cr8 << 4;\n-}\n-\n void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n {\n struct whpx_state *whpx = &whpx_global;\n@@ -440,7 +420,7 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n v86 = (env->eflags & VM_MASK);\n r86 = !(env->cr[0] & CR0_PE_MASK);\n \n- vcpu->tpr = whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state));\n+ vcpu->tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n vcpu->apic_base = cpu_get_apic_base(x86_cpu->apic_state);\n \n idx = 0;\n@@ -711,17 +691,6 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n hr);\n }\n \n- if (whpx_irqchip_in_kernel()) {\n- /*\n- * Fetch the TPR value from the emulated APIC. It may get overwritten\n- * below with the value from CR8 returned by\n- * WHvGetVirtualProcessorRegisters().\n- */\n- whpx_apic_get(x86_cpu->apic_state);\n- vcpu->tpr = whpx_apic_tpr_to_cr8(\n- cpu_get_apic_tpr(x86_cpu->apic_state));\n- }\n-\n idx = 0;\n \n /* Indexes for first 16 registers match between HV and QEMU definitions */\n@@ -770,7 +739,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n tpr = vcxt.values[idx++].Reg64;\n if (tpr != vcpu->tpr) {\n vcpu->tpr = tpr;\n- cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(tpr));\n+ cpu_set_apic_tpr(x86_cpu->apic_state, tpr);\n }\n \n /* 8 Debug Registers - Skipped */\n@@ -1775,7 +1744,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n }\n \n /* Sync the TPR to the CR8 if was modified during the intercept */\n- tpr = whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state));\n+ tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n if (tpr != vcpu->tpr) {\n vcpu->tpr = tpr;\n reg_values[reg_count].Reg64 = tpr;\n@@ -1822,7 +1791,7 @@ static void whpx_vcpu_post_run(CPUState *cpu)\n if (vcpu->tpr != tpr) {\n vcpu->tpr = tpr;\n bql_lock();\n- cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(vcpu->tpr));\n+ cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);\n bql_unlock();\n }\n \n", "prefixes": [ "PULL", "30/58" ] }