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GET /api/patches/2231397/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2231397,
    "url": "http://patchwork.ozlabs.org/api/patches/2231397/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260430162420.42839-14-18255117159@163.com/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260430162420.42839-14-18255117159@163.com>",
    "list_archive_url": null,
    "date": "2026-04-30T16:24:17",
    "name": "[RESEND,13/16] PCI: qcom: Use FIELD_MODIFY()",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "a67ce039e6dab3d85a4b0fe32a37718757f12628",
    "submitter": {
        "id": 89937,
        "url": "http://patchwork.ozlabs.org/api/people/89937/?format=api",
        "name": "Hans Zhang",
        "email": "18255117159@163.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260430162420.42839-14-18255117159@163.com/mbox/",
    "series": [
        {
            "id": 502340,
            "url": "http://patchwork.ozlabs.org/api/series/502340/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=502340",
            "date": "2026-04-30T16:24:06",
            "name": "PCI: Use FIELD_MODIFY() to simplify bitfield operations",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/502340/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2231397/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2231397/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "\n <linux-pci+bounces-53524-incoming=patchwork.ozlabs.org@vger.kernel.org>",
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        ],
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        "From": "Hans Zhang <18255117159@163.com>",
        "To": "bhelgaas@google.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tjingoohan1@gmail.com",
        "Cc": "robh@kernel.org,\n\ts32@nxp.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tHans Zhang <18255117159@163.com>",
        "Subject": "[RESEND PATCH 13/16] PCI: qcom: Use FIELD_MODIFY()",
        "Date": "Fri,  1 May 2026 00:24:17 +0800",
        "Message-Id": "<20260430162420.42839-14-18255117159@163.com>",
        "X-Mailer": "git-send-email 2.34.1",
        "In-Reply-To": "<20260430162420.42839-1-18255117159@163.com>",
        "References": "<20260430162420.42839-1-18255117159@163.com>",
        "Precedence": "bulk",
        "X-Mailing-List": "linux-pci@vger.kernel.org",
        "List-Id": "<linux-pci.vger.kernel.org>",
        "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>",
        "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-CM-TRANSID": "_____wA3Df0_gvNpcypXCg--.51103S7",
        "X-Coremail-Antispam": "1Uf129KBjvJXoWxZr45CFWrXFWDuFy3ury5CFg_yoW7Jw4Upa\n\t48t3Z7JF18tF4UurZIkanrur1F9FsxAw12kanxKanruasFyFZrWa90y3sxtrn7JF4UKFya\n\tk348AFW3GFySyrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n\t9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRP8nOUUUUU=",
        "X-CM-SenderInfo": "rpryjkyvrrlimvzbiqqrwthudrp/xtbCxAMIq2nzgkNcVAAA33"
    },
    "content": "Use FIELD_MODIFY() to remove open-coded bit manipulation.\nNo functional change intended.\n\nSigned-off-by: Hans Zhang <18255117159@163.com>\n---\n drivers/pci/controller/dwc/pcie-qcom-common.c | 40 +++++++------------\n drivers/pci/controller/dwc/pcie-qcom-ep.c     |  6 +--\n 2 files changed, 16 insertions(+), 30 deletions(-)",
    "diff": "diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c\nindex 5aa73c628737..0da73caf2011 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom-common.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom-common.c\n@@ -30,20 +30,15 @@ void qcom_pcie_common_set_equalization(struct dw_pcie *pci)\n \n \t\treg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);\n \t\treg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;\n-\t\treg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;\n-\t\treg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK,\n-\t\t\t  speed - PCIE_SPEED_8_0GT);\n+\t\tFIELD_MODIFY(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, &reg,\n+\t\t\t     speed - PCIE_SPEED_8_0GT);\n \t\tdw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg);\n \n \t\treg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF);\n-\t\treg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 |\n-\t\t\tGEN3_EQ_FMDC_N_EVALS |\n-\t\t\tGEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA |\n-\t\t\tGEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA);\n-\t\treg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) |\n-\t\t\tFIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) |\n-\t\t\tFIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, 0x5) |\n-\t\t\tFIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, 0x5);\n+\t\tFIELD_MODIFY(GEN3_EQ_FMDC_T_MIN_PHASE23, &reg, 0x1);\n+\t\tFIELD_MODIFY(GEN3_EQ_FMDC_N_EVALS, &reg, 0xd);\n+\t\tFIELD_MODIFY(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, &reg, 0x5);\n+\t\tFIELD_MODIFY(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, &reg, 0x5);\n \t\tdw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg);\n \n \t\treg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);\n@@ -61,14 +56,10 @@ void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci)\n \tu32 reg;\n \n \treg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF);\n-\treg &= ~(MARGINING_MAX_VOLTAGE_OFFSET |\n-\t\tMARGINING_NUM_VOLTAGE_STEPS |\n-\t\tMARGINING_MAX_TIMING_OFFSET |\n-\t\tMARGINING_NUM_TIMING_STEPS);\n-\treg |= FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) |\n-\t\tFIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) |\n-\t\tFIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) |\n-\t\tFIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10);\n+\tFIELD_MODIFY(MARGINING_MAX_VOLTAGE_OFFSET, &reg, 0x24);\n+\tFIELD_MODIFY(MARGINING_NUM_VOLTAGE_STEPS, &reg, 0x78);\n+\tFIELD_MODIFY(MARGINING_MAX_TIMING_OFFSET, &reg, 0x32);\n+\tFIELD_MODIFY(MARGINING_NUM_TIMING_STEPS, &reg, 0x10);\n \tdw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg);\n \n \treg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF);\n@@ -76,13 +67,10 @@ void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci)\n \t\tMARGINING_SAMPLE_REPORTING_METHOD |\n \t\tMARGINING_IND_LEFT_RIGHT_TIMING |\n \t\tMARGINING_VOLTAGE_SUPPORTED;\n-\treg &= ~(MARGINING_IND_UP_DOWN_VOLTAGE |\n-\t\tMARGINING_MAXLANES |\n-\t\tMARGINING_SAMPLE_RATE_TIMING |\n-\t\tMARGINING_SAMPLE_RATE_VOLTAGE);\n-\treg |= FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) |\n-\t\tFIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) |\n-\t\tFIELD_PREP(MARGINING_SAMPLE_RATE_VOLTAGE, 0x3f);\n+\treg &= ~MARGINING_IND_UP_DOWN_VOLTAGE;\n+\tFIELD_MODIFY(MARGINING_MAXLANES, &reg, pci->num_lanes);\n+\tFIELD_MODIFY(MARGINING_SAMPLE_RATE_TIMING, &reg, 0x3f);\n+\tFIELD_MODIFY(MARGINING_SAMPLE_RATE_VOLTAGE, &reg, 0x3f);\n \tdw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg);\n }\n EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_lane_margining);\ndiff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c\nindex 257c2bcb5f76..56184e6ca6e6 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c\n@@ -494,15 +494,13 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)\n \t/* Set the L0s Exit Latency to 2us-4us = 0x6 */\n \toffset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);\n \tval = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);\n-\tval &= ~PCI_EXP_LNKCAP_L0SEL;\n-\tval |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6);\n+\tFIELD_MODIFY(PCI_EXP_LNKCAP_L0SEL, &val, 0x6);\n \tdw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);\n \n \t/* Set the L1 Exit Latency to be 32us-64 us = 0x6 */\n \toffset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);\n \tval = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);\n-\tval &= ~PCI_EXP_LNKCAP_L1EL;\n-\tval |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6);\n+\tFIELD_MODIFY(PCI_EXP_LNKCAP_L1EL, &val, 0x6);\n \tdw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);\n \n \tdw_pcie_dbi_ro_wr_dis(pci);\n",
    "prefixes": [
        "RESEND",
        "13/16"
    ]
}