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GET /api/patches/2231325/?format=api
{ "id": 2231325, "url": "http://patchwork.ozlabs.org/api/patches/2231325/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260430154159.3649425-2-alfie.richards@arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430154159.3649425-2-alfie.richards@arm.com>", "list_archive_url": null, "date": "2026-04-30T15:41:58", "name": "[1/2] aarch64: Add new fp->int conversion intrinsics", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f8379b4e6ce03ae25e836816cff572ee3b5c9434", "submitter": { "id": 88864, "url": "http://patchwork.ozlabs.org/api/people/88864/?format=api", "name": "Alfie Richards", "email": "alfie.richards@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260430154159.3649425-2-alfie.richards@arm.com/mbox/", "series": [ { "id": 502331, "url": "http://patchwork.ozlabs.org/api/series/502331/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502331", "date": "2026-04-30T15:41:57", "name": "AArch64 new fp->int conversions and fprcvt", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502331/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231325/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231325/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ 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<alfie.richards@arm.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "<alex.coplan@arm.com>, <alice.carlotti@arm.com>,\n <andrew.pinski@oss.qualcomm.com>, <ktkachov@nvidia.com>,\n <richard.earnshaw@arm.com>, <tamar.christina@arm.com>,\n <wilco.dijkstra@arm.com>, Alfie Richards <alfie.richards@arm.com>", "Subject": "[PATCH 1/2] aarch64: Add new fp->int conversion intrinsics", "Date": "Thu, 30 Apr 2026 15:41:58 +0000", "Message-ID": "<20260430154159.3649425-2-alfie.richards@arm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260430154159.3649425-1-alfie.richards@arm.com>", "References": "<20260430154159.3649425-1-alfie.richards@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n DB5PEPF00014B8E:EE_|DU0PR08MB8347:EE_|AM4PEPF00027A67:EE_|AM0PR08MB5524:EE_", "X-MS-Office365-Filtering-Correlation-Id": "b34f74e9-14de-43f3-7fc7-08dea6cf3913", "x-checkrecipientrouted": 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b34f74e9-14de-43f3-7fc7-08dea6cf3913", "X-MS-Exchange-CrossTenant-Id": "f34e5979-57d9-4aaa-ad4d-b122a662184d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n AM4PEPF00027A67.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Adds intrinsics for the following conversions:\n- float32_t -> uint64_t\n- float32_t -> int64_t\n- float64_t -> uint32_t\n- float64_t -> int32_t\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64-simd-builtins.def: (lround): Add new\n\tforms for new conversions.\n\t(lroundu): Likewise.\n\t(lceil): Likewise.\n\t(lceilu): Likewise.\n\t(lfloor): Likewise.\n\t(lflooru): Likewise.\n\t(lfrintn): Likewise.\n\t(lfrintnu): Likewise.\n\t* config/aarch64/arm_neon.h (vcvtd_s32_f64): New intrinsic.\n\t(vcvtd_s32_f64): Likewise.\n\t(vcvtd_u32_f64): Likewise.\n\t(vcvts_s64_f32): Likewise.\n\t(vcvts_u64_f32): Likewise.\n\t(vcvtad_s32_f64): Likewise.\n\t(vcvtad_u32_f64): Likewise.\n\t(vcvtas_s64_f32): Likewise.\n\t(vcvtas_u64_f32): Likewise.\n\t(vcvtmd_s32_f64): Likewise.\n\t(vcvtmd_u32_f64): Likewise.\n\t(vcvtms_s64_f32): Likewise.\n\t(vcvtms_u64_f32): Likewise.\n\t(vcvtnd_s32_f64): Likewise.\n\t(vcvtnd_u32_f64): Likewise.\n\t(vcvtns_s64_f32): Likewise.\n\t(vcvtns_u64_f32): Likewise.\n\t(vcvtpd_s32_f64): Likewise.\n\t(vcvtpd_u32_f64): Likewise.\n\t(vcvtps_s64_f32): Likewise.\n\t(vcvtps_u64_f32): Likewise.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/acle/fcvt_intrinsics.c: New test.\n---\n gcc/config/aarch64/aarch64-simd-builtins.def | 16 ++\n gcc/config/aarch64/arm_neon.h | 139 +++++++++++++++\n .../gcc.target/aarch64/acle/fcvt_intrinsics.c | 166 ++++++++++++++++++\n 3 files changed, 321 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/fcvt_intrinsics.c", "diff": "diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def\nindex 8677df3f488..1b09191a0c0 100644\n--- a/gcc/config/aarch64/aarch64-simd-builtins.def\n+++ b/gcc/config/aarch64/aarch64-simd-builtins.def\n@@ -577,6 +577,8 @@\n /* Implemented by l<fcvt_pattern><su_optab><GPF_F16:mode><GPI:mode>2. */\n BUILTIN_GPI_I16 (UNOP, lroundhf, 2, FP)\n VAR1 (UNOP, lroundsf, 2, FP, si)\n+ VAR1 (UNOP, lroundsf, 2, FP, di)\n+ VAR1 (UNOP, lrounddf, 2, FP, si)\n VAR1 (UNOP, lrounddf, 2, FP, di)\n \n VAR1 (UNOPUS, lrounduv4hf, 2, FP, v4hi)\n@@ -586,6 +588,8 @@\n VAR1 (UNOPUS, lrounduv2df, 2, FP, v2di)\n BUILTIN_GPI_I16 (UNOPUS, lrounduhf, 2, FP)\n VAR1 (UNOPUS, lroundusf, 2, FP, si)\n+ VAR1 (UNOPUS, lroundusf, 2, FP, di)\n+ VAR1 (UNOPUS, lroundudf, 2, FP, si)\n VAR1 (UNOPUS, lroundudf, 2, FP, di)\n \n VAR1 (UNOP, lceilv4hf, 2, FP, v4hi)\n@@ -594,6 +598,8 @@\n VAR1 (UNOP, lceilv4sf, 2, FP, v4si)\n VAR1 (UNOP, lceilv2df, 2, FP, v2di)\n BUILTIN_GPI_I16 (UNOP, lceilhf, 2, FP)\n+ VAR1 (UNOP, lceilsf, 2, FP, di)\n+ VAR1 (UNOP, lceildf, 2, FP, si)\n \n VAR1 (UNOPUS, lceiluv4hf, 2, FP, v4hi)\n VAR1 (UNOPUS, lceiluv8hf, 2, FP, v8hi)\n@@ -602,6 +608,8 @@\n VAR1 (UNOPUS, lceiluv2df, 2, FP, v2di)\n BUILTIN_GPI_I16 (UNOPUS, lceiluhf, 2, FP)\n VAR1 (UNOPUS, lceilusf, 2, FP, si)\n+ VAR1 (UNOPUS, lceilusf, 2, FP, di)\n+ VAR1 (UNOPUS, lceiludf, 2, FP, si)\n VAR1 (UNOPUS, lceiludf, 2, FP, di)\n \n VAR1 (UNOP, lfloorv4hf, 2, FP, v4hi)\n@@ -610,6 +618,8 @@\n VAR1 (UNOP, lfloorv4sf, 2, FP, v4si)\n VAR1 (UNOP, lfloorv2df, 2, FP, v2di)\n BUILTIN_GPI_I16 (UNOP, lfloorhf, 2, FP)\n+ VAR1 (UNOP, lfloorsf, 2, FP, di)\n+ VAR1 (UNOP, lfloordf, 2, FP, si)\n \n VAR1 (UNOPUS, lflooruv4hf, 2, FP, v4hi)\n VAR1 (UNOPUS, lflooruv8hf, 2, FP, v8hi)\n@@ -618,6 +628,8 @@\n VAR1 (UNOPUS, lflooruv2df, 2, FP, v2di)\n BUILTIN_GPI_I16 (UNOPUS, lflooruhf, 2, FP)\n VAR1 (UNOPUS, lfloorusf, 2, FP, si)\n+ VAR1 (UNOPUS, lfloorusf, 2, FP, di)\n+ VAR1 (UNOPUS, lfloorudf, 2, FP, si)\n VAR1 (UNOPUS, lfloorudf, 2, FP, di)\n \n VAR1 (UNOP, lfrintnv4hf, 2, FP, v4hi)\n@@ -627,6 +639,8 @@\n VAR1 (UNOP, lfrintnv2df, 2, FP, v2di)\n BUILTIN_GPI_I16 (UNOP, lfrintnhf, 2, FP)\n VAR1 (UNOP, lfrintnsf, 2, FP, si)\n+ VAR1 (UNOP, lfrintnsf, 2, FP, di)\n+ VAR1 (UNOP, lfrintndf, 2, FP, si)\n VAR1 (UNOP, lfrintndf, 2, FP, di)\n \n VAR1 (UNOPUS, lfrintnuv4hf, 2, FP, v4hi)\n@@ -636,6 +650,8 @@\n VAR1 (UNOPUS, lfrintnuv2df, 2, FP, v2di)\n BUILTIN_GPI_I16 (UNOPUS, lfrintnuhf, 2, FP)\n VAR1 (UNOPUS, lfrintnusf, 2, FP, si)\n+ VAR1 (UNOPUS, lfrintnusf, 2, FP, di)\n+ VAR1 (UNOPUS, lfrintnudf, 2, FP, si)\n VAR1 (UNOPUS, lfrintnudf, 2, FP, di)\n \n /* Implemented by <optab><fcvt_target><VDQF:mode>2. */\ndiff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h\nindex 82cf94b5173..883d5c31591 100644\n--- a/gcc/config/aarch64/arm_neon.h\n+++ b/gcc/config/aarch64/arm_neon.h\n@@ -10033,6 +10033,13 @@ vcvtd_s64_f64 (float64_t __a)\n return (int64_t) __a;\n }\n \n+__extension__ extern __inline int32_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtd_s32_f64 (float64_t __a)\n+{\n+ return (int32_t) __a;\n+}\n+\n __extension__ extern __inline uint64_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvtd_u64_f64 (float64_t __a)\n@@ -10040,6 +10047,13 @@ vcvtd_u64_f64 (float64_t __a)\n return (uint64_t) __a;\n }\n \n+__extension__ extern __inline uint32_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtd_u32_f64 (float64_t __a)\n+{\n+ return (uint32_t) __a;\n+}\n+\n __extension__ extern __inline int32_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvts_s32_f32 (float32_t __a)\n@@ -10047,6 +10061,13 @@ vcvts_s32_f32 (float32_t __a)\n return (int32_t) __a;\n }\n \n+__extension__ extern __inline int64_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvts_s64_f32 (float32_t __a)\n+{\n+ return (int64_t) __a;\n+}\n+\n __extension__ extern __inline uint32_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvts_u32_f32 (float32_t __a)\n@@ -10054,6 +10075,13 @@ vcvts_u32_f32 (float32_t __a)\n return (uint32_t) __a;\n }\n \n+__extension__ extern __inline uint64_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvts_u64_f32 (float32_t __a)\n+{\n+ return (uint64_t) __a;\n+}\n+\n __extension__ extern __inline int32x2_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvt_s32_f32 (float32x2_t __a)\n@@ -10119,6 +10147,13 @@ vcvtad_s64_f64 (float64_t __a)\n return __builtin_aarch64_lrounddfdi (__a);\n }\n \n+__extension__ extern __inline int32_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtad_s32_f64 (float64_t __a)\n+{\n+ return __builtin_aarch64_lrounddfsi (__a);\n+}\n+\n __extension__ extern __inline uint64_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvtad_u64_f64 (float64_t __a)\n@@ -10126,6 +10161,13 @@ vcvtad_u64_f64 (float64_t __a)\n return __builtin_aarch64_lroundudfdi_us (__a);\n }\n \n+__extension__ extern __inline uint32_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtad_u32_f64 (float64_t __a)\n+{\n+ return __builtin_aarch64_lroundudfsi_us (__a);\n+}\n+\n __extension__ extern __inline int32_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvtas_s32_f32 (float32_t __a)\n@@ -10133,6 +10175,13 @@ vcvtas_s32_f32 (float32_t __a)\n return __builtin_aarch64_lroundsfsi (__a);\n }\n \n+__extension__ extern __inline int64_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtas_s64_f32 (float32_t __a)\n+{\n+ return __builtin_aarch64_lroundsfdi (__a);\n+}\n+\n __extension__ extern __inline uint32_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvtas_u32_f32 (float32_t __a)\n@@ -10140,6 +10189,13 @@ vcvtas_u32_f32 (float32_t __a)\n return __builtin_aarch64_lroundusfsi_us (__a);\n }\n \n+__extension__ extern __inline uint64_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtas_u64_f32 (float32_t __a)\n+{\n+ return __builtin_aarch64_lroundusfdi_us (__a);\n+}\n+\n __extension__ extern __inline int32x2_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvta_s32_f32 (float32x2_t __a)\n@@ -10205,6 +10261,13 @@ vcvtmd_s64_f64 (float64_t __a)\n return __builtin_llfloor (__a);\n }\n \n+__extension__ extern __inline int32_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtmd_s32_f64 (float64_t __a)\n+{\n+ return __builtin_aarch64_lfloordfsi (__a);\n+}\n+\n __extension__ extern __inline uint64_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvtmd_u64_f64 (float64_t __a)\n@@ -10212,6 +10275,13 @@ vcvtmd_u64_f64 (float64_t __a)\n return __builtin_aarch64_lfloorudfdi_us (__a);\n }\n \n+__extension__ extern __inline uint32_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtmd_u32_f64 (float64_t __a)\n+{\n+ return __builtin_aarch64_lfloorudfsi_us (__a);\n+}\n+\n __extension__ extern __inline int32_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvtms_s32_f32 (float32_t __a)\n@@ -10219,6 +10289,13 @@ vcvtms_s32_f32 (float32_t __a)\n return __builtin_ifloorf (__a);\n }\n \n+__extension__ extern __inline int64_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtms_s64_f32 (float32_t __a)\n+{\n+ return __builtin_aarch64_lfloorsfdi (__a);\n+}\n+\n __extension__ extern __inline uint32_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvtms_u32_f32 (float32_t __a)\n@@ -10226,6 +10303,13 @@ vcvtms_u32_f32 (float32_t __a)\n return __builtin_aarch64_lfloorusfsi_us (__a);\n }\n \n+__extension__ extern __inline uint64_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtms_u64_f32 (float32_t __a)\n+{\n+ return __builtin_aarch64_lfloorusfdi_us (__a);\n+}\n+\n __extension__ extern __inline int32x2_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvtm_s32_f32 (float32x2_t __a)\n@@ -10291,6 +10375,13 @@ vcvtnd_s64_f64 (float64_t __a)\n return __builtin_aarch64_lfrintndfdi (__a);\n }\n \n+__extension__ extern __inline int64_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtnd_s32_f64 (float64_t __a)\n+{\n+ return __builtin_aarch64_lfrintndfsi (__a);\n+}\n+\n __extension__ extern __inline uint64_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvtnd_u64_f64 (float64_t __a)\n@@ -10298,6 +10389,13 @@ vcvtnd_u64_f64 (float64_t __a)\n return __builtin_aarch64_lfrintnudfdi_us (__a);\n }\n \n+__extension__ extern __inline uint32_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtnd_u32_f64 (float64_t __a)\n+{\n+ return __builtin_aarch64_lfrintnudfsi_us (__a);\n+}\n+\n __extension__ extern __inline int32_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvtns_s32_f32 (float32_t __a)\n@@ -10305,12 +10403,25 @@ vcvtns_s32_f32 (float32_t __a)\n return __builtin_aarch64_lfrintnsfsi (__a);\n }\n \n+__extension__ extern __inline int64_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtns_s64_f32 (float32_t __a)\n+{\n+ return __builtin_aarch64_lfrintnsfdi (__a);\n+}\n+\n __extension__ extern __inline uint32_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvtns_u32_f32 (float32_t __a)\n {\n return __builtin_aarch64_lfrintnusfsi_us (__a);\n }\n+__extension__ extern __inline uint64_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtns_u64_f32 (float32_t __a)\n+{\n+ return __builtin_aarch64_lfrintnusfdi_us (__a);\n+}\n \n __extension__ extern __inline int32x2_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n@@ -10377,6 +10488,13 @@ vcvtpd_s64_f64 (float64_t __a)\n return __builtin_llceil (__a);\n }\n \n+__extension__ extern __inline int32_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtpd_s32_f64 (float64_t __a)\n+{\n+ return __builtin_aarch64_lceildfsi (__a);\n+}\n+\n __extension__ extern __inline uint64_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvtpd_u64_f64 (float64_t __a)\n@@ -10384,6 +10502,13 @@ vcvtpd_u64_f64 (float64_t __a)\n return __builtin_aarch64_lceiludfdi_us (__a);\n }\n \n+__extension__ extern __inline uint32_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtpd_u32_f64 (float64_t __a)\n+{\n+ return __builtin_aarch64_lceiludfsi_us (__a);\n+}\n+\n __extension__ extern __inline int32_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvtps_s32_f32 (float32_t __a)\n@@ -10391,6 +10516,13 @@ vcvtps_s32_f32 (float32_t __a)\n return __builtin_iceilf (__a);\n }\n \n+__extension__ extern __inline int64_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtps_s64_f32 (float32_t __a)\n+{\n+ return __builtin_aarch64_lceilsfdi (__a);\n+}\n+\n __extension__ extern __inline uint32_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvtps_u32_f32 (float32_t __a)\n@@ -10398,6 +10530,13 @@ vcvtps_u32_f32 (float32_t __a)\n return __builtin_aarch64_lceilusfsi_us (__a);\n }\n \n+__extension__ extern __inline uint64_t\n+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n+vcvtps_u64_f32 (float32_t __a)\n+{\n+ return __builtin_aarch64_lceilusfdi_us (__a);\n+}\n+\n __extension__ extern __inline int32x2_t\n __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n vcvtp_s32_f32 (float32x2_t __a)\ndiff --git a/gcc/testsuite/gcc.target/aarch64/acle/fcvt_intrinsics.c b/gcc/testsuite/gcc.target/aarch64/acle/fcvt_intrinsics.c\nnew file mode 100644\nindex 00000000000..ff81d340f35\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/acle/fcvt_intrinsics.c\n@@ -0,0 +1,166 @@\n+/* { dg-do compile } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" } } */\n+\n+#include <arm_acle.h>\n+#include <arm_neon.h>\n+\n+#define CONVERT_INTRINSIC(T_FROM, T_TO, INTRINSIC) \\\n+ void convert_##INTRINSIC (T_FROM *from, T_TO *to) \\\n+ { \\\n+ T_FROM from_val = *from; \\\n+ T_TO to_val = INTRINSIC (from_val); \\\n+ *to = to_val; \\\n+ }\n+\n+CONVERT_INTRINSIC (float32_t, int64_t, vcvts_s64_f32)\n+/*\n+** convert_vcvts_s64_f32:\n+**...\n+**\tfcvtzs\tx[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, uint64_t, vcvts_u64_f32)\n+/*\n+** convert_vcvts_u64_f32:\n+**...\n+**\tfcvtzu\tx[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, int64_t, vcvtns_s64_f32)\n+/*\n+** convert_vcvtns_s64_f32:\n+**...\n+**\tfcvtns\tx[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, uint64_t, vcvtns_u64_f32)\n+/*\n+** convert_vcvtns_u64_f32:\n+**...\n+**\tfcvtnu\tx[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, int64_t, vcvtms_s64_f32)\n+/*\n+** convert_vcvtms_s64_f32:\n+**...\n+**\tfcvtms\tx[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, uint64_t, vcvtms_u64_f32)\n+/*\n+** convert_vcvtms_u64_f32:\n+**...\n+**\tfcvtmu\tx[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, int64_t, vcvtps_s64_f32)\n+/*\n+** convert_vcvtps_s64_f32:\n+**...\n+**\tfcvtps\tx[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, uint64_t, vcvtps_u64_f32)\n+/*\n+** convert_vcvtps_u64_f32:\n+**...\n+**\tfcvtpu\tx[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, int64_t, vcvtas_s64_f32)\n+/*\n+** convert_vcvtas_s64_f32:\n+**...\n+**\tfcvtas\tx[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, uint64_t, vcvtas_u64_f32)\n+/*\n+** convert_vcvtas_u64_f32:\n+**...\n+**\tfcvtau\tx[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, int32_t, vcvtd_s32_f64)\n+/*\n+** convert_vcvtd_s32_f64:\n+**...\n+**\tfcvtzs\tw[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, uint32_t, vcvtd_u32_f64)\n+/*\n+** convert_vcvtd_u32_f64:\n+**...\n+**\tfcvtzu\tw[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, int32_t, vcvtnd_s32_f64)\n+/*\n+** convert_vcvtnd_s32_f64:\n+**...\n+**\tfcvtns\tw[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, uint32_t, vcvtnd_u32_f64)\n+/*\n+** convert_vcvtnd_u32_f64:\n+**...\n+**\tfcvtnu\tw[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, int32_t, vcvtmd_s32_f64)\n+/*\n+** convert_vcvtmd_s32_f64:\n+**...\n+**\tfcvtms\tw[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, uint32_t, vcvtmd_u32_f64)\n+/*\n+** convert_vcvtmd_u32_f64:\n+**...\n+**\tfcvtmu\tw[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, int32_t, vcvtpd_s32_f64)\n+/*\n+** convert_vcvtpd_s32_f64:\n+**...\n+**\tfcvtps\tw[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, uint32_t, vcvtpd_u32_f64)\n+/*\n+** convert_vcvtpd_u32_f64:\n+**...\n+**\tfcvtpu\tw[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, int32_t, vcvtad_s32_f64)\n+/*\n+** convert_vcvtad_s32_f64:\n+**...\n+**\tfcvtas\tw[0-9]+, d[0-9]+\n+**...\n+*/\n+\n", "prefixes": [ "1/2" ] }