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GET /api/patches/2231323/?format=api
{ "id": 2231323, "url": "http://patchwork.ozlabs.org/api/patches/2231323/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260430154159.3649425-3-alfie.richards@arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430154159.3649425-3-alfie.richards@arm.com>", "list_archive_url": null, "date": "2026-04-30T15:41:59", "name": "[2/2] aarch64: Add FEAT_FPRCVT support.", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "15bc56cdb4fc6d2761808b54725f7ec3a550cc5a", "submitter": { "id": 88864, "url": "http://patchwork.ozlabs.org/api/people/88864/?format=api", "name": "Alfie Richards", "email": "alfie.richards@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260430154159.3649425-3-alfie.richards@arm.com/mbox/", "series": [ { "id": 502331, "url": "http://patchwork.ozlabs.org/api/series/502331/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502331", "date": "2026-04-30T15:41:57", "name": "AArch64 new fp->int conversions and fprcvt", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502331/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231323/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231323/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ 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<alfie.richards@arm.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "<alex.coplan@arm.com>, <alice.carlotti@arm.com>,\n <andrew.pinski@oss.qualcomm.com>, <ktkachov@nvidia.com>,\n <richard.earnshaw@arm.com>, <tamar.christina@arm.com>,\n <wilco.dijkstra@arm.com>, Alfie Richards <alfie.richards@arm.com>", "Subject": "[PATCH 2/2] aarch64: Add FEAT_FPRCVT support.", "Date": "Thu, 30 Apr 2026 15:41:59 +0000", "Message-ID": "<20260430154159.3649425-3-alfie.richards@arm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260430154159.3649425-1-alfie.richards@arm.com>", "References": "<20260430154159.3649425-1-alfie.richards@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n DB5PEPF00014B8E:EE_|AM8PR08MB6452:EE_|AMS0EPF000001B3:EE_|AMDPR08MB11436:EE_", "X-MS-Office365-Filtering-Correlation-Id": "83b7798d-2bdb-4d0a-2aaa-08dea6cf372b", "x-checkrecipientrouted": "true", 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"Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "gcc/ChangeLog:\n\n\t* config/aarch64/aarch64.h (TARGET_FPRCVT): New macro definition.\n\t* config/aarch64/aarch64.md (arches): Add fprcvt.\n\t(arch_enabled): Add fprcvt.\n\t(l<fcvt_pattern><su_optab><GPF_F16:mode><GPI:mode>2): Add\n\tFEAT_FPRCVT variant.\n\t(<optab>_trunchf<GPI:mode>2): Likewise.\n\t(<optab>_trunc<fcvt_change_mode><GPI:mode>2): Likewise.\n\t(fix_to_zero_extend<mode>di2): Likewise.\n\t(<optab><fcvt_iesize><GPF:mode>2): Likewise.\n\t(define_insn \"aarch64_fp16_<optab><mode>hf2): Likewise.\n\t* config/aarch64/iterators.md (fpw): Add SF and DF variants.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/acle/fprcvt.c: New test.\n\t* gcc.target/aarch64/fprcvt.c: New test.\n\t* gcc.target/aarch64/fprcvt.x: New test.\n\t* gcc.target/aarch64/fprcvt_float32_int32.c: New test.\n\t* gcc.target/aarch64/fprcvt_float32_int64.c: New test.\n\t* gcc.target/aarch64/fprcvt_float32_uint32.c: New test.\n\t* gcc.target/aarch64/fprcvt_float32_uint64.c: New test.\n\t* gcc.target/aarch64/fprcvt_float64_int32.c: New test.\n\t* gcc.target/aarch64/fprcvt_float64_int64.c: New test.\n\t* gcc.target/aarch64/fprcvt_float64_uint32.c: New test.\n\t* gcc.target/aarch64/fprcvt_float64_uint64.c: New test.\n---\n gcc/config/aarch64/aarch64.h | 2 +\n gcc/config/aarch64/aarch64.md | 74 +-\n gcc/config/aarch64/iterators.md | 2 +-\n .../gcc.target/aarch64/acle/fprcvt.c | 651 ++++++++++++++++++\n gcc/testsuite/gcc.target/aarch64/fprcvt.c | 147 ++++\n gcc/testsuite/gcc.target/aarch64/fprcvt.x | 87 +++\n .../gcc.target/aarch64/fprcvt_float32_int32.c | 18 +\n .../gcc.target/aarch64/fprcvt_float32_int64.c | 16 +\n .../aarch64/fprcvt_float32_uint32.c | 18 +\n .../aarch64/fprcvt_float32_uint64.c | 18 +\n .../gcc.target/aarch64/fprcvt_float64_int32.c | 18 +\n .../gcc.target/aarch64/fprcvt_float64_int64.c | 16 +\n .../aarch64/fprcvt_float64_uint32.c | 18 +\n .../aarch64/fprcvt_float64_uint64.c | 18 +\n 14 files changed, 1073 insertions(+), 30 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/fprcvt.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/fprcvt.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/fprcvt.x\n create mode 100644 gcc/testsuite/gcc.target/aarch64/fprcvt_float32_int32.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/fprcvt_float32_int64.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/fprcvt_float32_uint32.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/fprcvt_float32_uint64.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/fprcvt_float64_int32.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/fprcvt_float64_int64.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/fprcvt_float64_uint32.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/fprcvt_float64_uint64.c", "diff": "diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h\nindex a0282ce285b..0a53b42b199 100644\n--- a/gcc/config/aarch64/aarch64.h\n+++ b/gcc/config/aarch64/aarch64.h\n@@ -591,6 +591,8 @@ through +ssve-fp8dot2. */\n \t\t\t && (AARCH64_HAVE_ISA (SSVE_FEXPA) \\\n \t\t\t || TARGET_NON_STREAMING))\n \n+#define TARGET_FPRCVT (AARCH64_HAVE_ISA (FPRCVT))\n+\n /* Standard register usage. */\n \n /* 31 64-bit general purpose registers R0-R30:\ndiff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\nindex 6541fa84f88..234850888e3 100644\n--- a/gcc/config/aarch64/aarch64.md\n+++ b/gcc/config/aarch64/aarch64.md\n@@ -503,7 +503,7 @@ (define_constants\n ;; Q registers and is equivalent to \"simd\".\n \n (define_enum \"arches\" [any rcpc8_4 fp fp_q base_simd nobase_simd\n-\t\t simd nosimd sve fp16 sme cssc sve2p2_or_sme2p2])\n+\t\t simd nosimd sve fp16 sme cssc fprcvt sve2p2_or_sme2p2])\n \n (define_enum_attr \"arch\" \"arches\" (const_string \"any\"))\n \n@@ -585,7 +585,10 @@ (define_attr \"arch_enabled\" \"no,yes\"\n \t (match_test \"TARGET_SME\"))\n \n \t(and (eq_attr \"arch\" \"sve2p2_or_sme2p2\")\n-\t (match_test \"TARGET_SVE2p2_OR_SME2p2\"))))\n+\t (match_test \"TARGET_SVE2p2_OR_SME2p2\"))\n+\n+\t(and (eq_attr \"arch\" \"fprcvt\")\n+\t (match_test \"TARGET_FPRCVT\"))))\n (const_string \"yes\")\n (const_string \"no\")))\n \n@@ -3156,8 +3159,8 @@ (define_insn \"*subs_<optab><ALLX:mode>_<GPI:mode>\"\n (define_insn \"*adds_<optab><ALLX:mode>_shift_<GPI:mode>\"\n [(set (reg:CC_NZ CC_REGNUM)\n \t(compare:CC_NZ\n-\t (plus:GPI (ashift:GPI \n-\t\t (ANY_EXTEND:GPI \n+\t (plus:GPI (ashift:GPI\n+\t\t (ANY_EXTEND:GPI\n \t\t (match_operand:ALLX 1 \"register_operand\" \"r\"))\n \t\t (match_operand 2 \"aarch64_imm3\" \"Ui3\"))\n \t\t (match_operand:GPI 3 \"register_operand\" \"rk\"))\n@@ -3175,7 +3178,7 @@ (define_insn \"*subs_<optab><ALLX:mode>_shift_<GPI:mode>\"\n [(set (reg:CC_NZ CC_REGNUM)\n \t(compare:CC_NZ\n \t (minus:GPI (match_operand:GPI 1 \"register_operand\" \"rk\")\n-\t\t (ashift:GPI \n+\t\t (ashift:GPI\n \t\t (ANY_EXTEND:GPI\n \t\t (match_operand:ALLX 2 \"register_operand\" \"r\"))\n \t\t (match_operand 3 \"aarch64_imm3\" \"Ui3\")))\n@@ -7097,13 +7100,15 @@ (define_insn \"<frint_pattern><mode>2\"\n ;; frcvt floating-point round to integer and convert standard patterns.\n ;; Expands to lbtrunc, lceil, lfloor, lround.\n (define_insn \"l<fcvt_pattern><su_optab><GPF_F16:mode><GPI:mode>2\"\n- [(set (match_operand:GPI 0 \"register_operand\" \"=r\")\n+ [(set (match_operand:GPI 0 \"register_operand\")\n \t(FIXUORS:GPI\n-\t (unspec:GPF_F16 [(match_operand:GPF_F16 1 \"register_operand\" \"w\")]\n+\t (unspec:GPF_F16 [(match_operand:GPF_F16 1 \"register_operand\")]\n \t FCVT)))]\n- \"TARGET_FLOAT\"\n- \"fcvt<frint_suffix><su>\\\\t%<GPI:w>0, %<GPF_F16:s>1\"\n- [(set_attr \"type\" \"f_cvtf2i\")]\n+ \"\"\n+ {@ [ cons: =0 , 1 ; attrs: type , arch ]\n+ [ r , w ; f_cvtf2i , fp ] fcvt<frint_suffix><su>\\t%<GPI:w>0, %<GPF_F16:s>1\n+ [ w , w ; f_cvtf2i , fprcvt ] fcvt<frint_suffix><su>\\t%<GPI:v>0, %<GPF_F16:s>1\n+ }\n )\n \n (define_insn \"*aarch64_fcvt<su_optab><GPF:mode><GPI:mode>2_mult\"\n@@ -7284,32 +7289,38 @@ (define_insn \"<optab>_trunc<fcvt_target><GPI:mode>2\"\n ;; Convert HF -> SI or DI\n \n (define_insn \"<optab>_trunchf<GPI:mode>2\"\n- [(set (match_operand:GPI 0 \"register_operand\" \"=r\")\n-\t(FIXUORS:GPI (match_operand:HF 1 \"register_operand\" \"w\")))]\n+ [(set (match_operand:GPI 0 \"register_operand\")\n+\t(FIXUORS:GPI (match_operand:HF 1 \"register_operand\")))]\n \"TARGET_FP_F16INST\"\n- \"fcvtz<su>\\t%<w>0, %h1\"\n- [(set_attr \"type\" \"f_cvtf2i\")]\n+ {@ [ cons: =0 , 1 ; attrs: type , arch ]\n+ [ r , w ; f_cvtf2i , fp ] fcvtz<su>\\t%<w>0, %h1\n+ [ w , w ; f_cvtf2i , fprcvt ] fcvtz<su>\\t%<s>0, %h1\n+ }\n )\n \n ;; Convert DF -> SI or SF -> DI which can only be accomplished with\n ;; input in a fp register and output in a integer register\n \n (define_insn \"<optab>_trunc<fcvt_change_mode><GPI:mode>2\"\n- [(set (match_operand:GPI 0 \"register_operand\" \"=r\")\n-\t(FIXUORS:GPI (match_operand:<FCVT_CHANGE_MODE> 1 \"register_operand\" \"w\")))]\n+ [(set (match_operand:GPI 0 \"register_operand\")\n+\t(FIXUORS:GPI (match_operand:<FCVT_CHANGE_MODE> 1 \"register_operand\")))]\n \"TARGET_FLOAT\"\n- \"fcvtz<su>\\t%<w>0, %<fpw>1\"\n- [(set_attr \"type\" \"f_cvtf2i\")]\n+ {@ [ cons: =0 , 1 ; attrs: type , arch ]\n+ [ r , w ; f_cvtf2i , fp ] fcvtz<su>\\t%<w>0, %<fpw>1\n+ [ w , w ; f_cvtf2i , fprcvt ] fcvtz<su>\\t%<s>0, %<fpw>1\n+ }\n )\n \n (define_insn \"*fix_to_zero_extend<mode>di2\"\n- [(set (match_operand:DI 0 \"register_operand\" \"=r\")\n+ [(set (match_operand:DI 0 \"register_operand\")\n \t(zero_extend:DI\n \t (unsigned_fix:SI\n-\t (match_operand:GPF 1 \"register_operand\" \"w\"))))]\n+\t (match_operand:GPF 1 \"register_operand\"))))]\n \"TARGET_FLOAT\"\n- \"fcvtzu\\t%w0, %<s>1\"\n- [(set_attr \"type\" \"f_cvtf2i\")]\n+ {@ [ cons: =0 , 1 ; attrs: type , arch ]\n+ [ r , w ; f_cvtf2i , fp ] fcvtzu\\t%w0, %<s>1\n+ [ w , w ; f_cvtf2i , fprcvt ] fcvtzu\\t%s0, %<s>1\n+ }\n )\n \n ;; Equal width integer to fp and multiply combine.\n@@ -7362,10 +7373,13 @@ (define_insn \"<optab><fcvt_target><GPF:mode>2\"\n \n ;; Unequal width integer to fp conversions.\n (define_insn \"<optab><fcvt_iesize><GPF:mode>2\"\n- [(set (match_operand:GPF 0 \"register_operand\" \"=w\")\n- (FLOATUORS:GPF (match_operand:<FCVT_IESIZE> 1 \"register_operand\" \"r\")))]\n+ [(set (match_operand:GPF 0 \"register_operand\")\n+\t(FLOATUORS:GPF (match_operand:<FCVT_IESIZE> 1 \"register_operand\")))]\n \"TARGET_FLOAT\"\n- \"<su_optab>cvtf\\t%<GPF:s>0, %<w2>1\"\n+ {@ [ cons: =0 , 1 ; attrs: type , arch ]\n+ [ w , r ; f_cvti2f , fp ] <su_optab>cvtf\\t%<GPF:s>0, %<w2>1\n+ [ w , w ; f_cvti2f , fprcvt ] <su_optab>cvtf\\t%<GPF:s>0, %<fpw>1\n+ }\n [(set_attr \"type\" \"f_cvti2f\")]\n )\n \n@@ -7377,11 +7391,13 @@ (define_insn \"<optab><fcvt_iesize><GPF:mode>2\"\n ;; of the mid-end logic.\n \n (define_insn \"aarch64_fp16_<optab><mode>hf2\"\n- [(set (match_operand:HF 0 \"register_operand\" \"=w\")\n-\t(FLOATUORS:HF (match_operand:GPI 1 \"register_operand\" \"r\")))]\n+ [(set (match_operand:HF 0 \"register_operand\")\n+\t(FLOATUORS:HF (match_operand:GPI 1 \"register_operand\")))]\n \"TARGET_FP_F16INST\"\n- \"<su_optab>cvtf\\t%h0, %<w>1\"\n- [(set_attr \"type\" \"f_cvti2f\")]\n+ {@ [ cons: =0 , 1 ; attrs: type , arch ]\n+ [ w , r ; f_cvti2f , fp ] <su_optab>cvtf\\t%h0, %<w>1\n+ [ w , w ; f_cvti2f , fprcvt ] <su_optab>cvtf\\t%h0, %<v>1\n+ }\n )\n \n (define_expand \"<optab>sihf2\"\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex 6b969258182..a469d082bbb 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -1440,7 +1440,7 @@ (define_mode_attr w1 [(HF \"w\") (SF \"w\") (DF \"x\")])\n (define_mode_attr w2 [(HF \"x\") (SF \"x\") (DF \"w\")])\n \n ;; For width of fp registers in fcvt instruction\n-(define_mode_attr fpw [(DI \"s\") (SI \"d\")])\n+(define_mode_attr fpw [(DI \"s\") (SI \"d\") (DF \"s\") (SF \"d\")])\n \n (define_mode_attr short_mask [(HI \"65535\") (QI \"255\")])\n \ndiff --git a/gcc/testsuite/gcc.target/aarch64/acle/fprcvt.c b/gcc/testsuite/gcc.target/aarch64/acle/fprcvt.c\nnew file mode 100644\nindex 00000000000..603e72d8c5a\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/acle/fprcvt.c\n@@ -0,0 +1,651 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-save-temps -fno-inline -O1 -march=armv9-a+fprcvt\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" } } */\n+\n+#include <stdint.h>\n+#include <arm_fp16.h>\n+#include <arm_acle.h>\n+#include <arm_neon.h>\n+\n+#define FORCE_FP_REG(a) asm volatile(\"fmov %d0, %d1\" : \"=w\"(a) : \"w\"(a) :)\n+#define CONVERT_INTRINSIC(T_FROM, T_TO, INTRINSIC) \\\n+ void convert_##INTRINSIC (T_FROM *from, T_TO *to) \\\n+ { \\\n+ T_FROM from_val = *from; \\\n+ FORCE_FP_REG (from_val); \\\n+ T_TO to_val = INTRINSIC (from_val); \\\n+ FORCE_FP_REG (to_val); \\\n+ *to = to_val; \\\n+ }\n+\n+CONVERT_INTRINSIC (float32_t, int32_t, vcvts_s32_f32)\n+/*\n+** convert_vcvts_s32_f32:\n+**...\n+**\tfcvtzs\ts[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, int64_t, vcvts_s64_f32)\n+/*\n+** convert_vcvts_s64_f32:\n+**...\n+**\tfcvtzs\td[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, uint32_t, vcvts_u32_f32)\n+/*\n+** convert_vcvts_u32_f32:\n+**...\n+**\tfcvtzu\ts[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, uint64_t, vcvts_u64_f32)\n+/*\n+** convert_vcvts_u64_f32:\n+**...\n+**\tfcvtzu\td[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, int32_t, vcvtns_s32_f32)\n+/*\n+** convert_vcvtns_s32_f32:\n+**...\n+**\tfcvtns\ts[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, int64_t, vcvtns_s64_f32)\n+/*\n+** convert_vcvtns_s64_f32:\n+**...\n+**\tfcvtns\td[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, uint32_t, vcvtns_u32_f32)\n+/*\n+** convert_vcvtns_u32_f32:\n+**...\n+**\tfcvtnu\ts[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, uint64_t, vcvtns_u64_f32)\n+/*\n+** convert_vcvtns_u64_f32:\n+**...\n+**\tfcvtnu\td[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, int32_t, vcvtms_s32_f32)\n+/*\n+** convert_vcvtms_s32_f32:\n+**...\n+**\tfcvtms\ts[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, int64_t, vcvtms_s64_f32)\n+/*\n+** convert_vcvtms_s64_f32:\n+**...\n+**\tfcvtms\td[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, uint32_t, vcvtms_u32_f32)\n+/*\n+** convert_vcvtms_u32_f32:\n+**...\n+**\tfcvtmu\ts[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, uint64_t, vcvtms_u64_f32)\n+/*\n+** convert_vcvtms_u64_f32:\n+**...\n+**\tfcvtmu\td[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, int32_t, vcvtps_s32_f32)\n+/*\n+** convert_vcvtps_s32_f32:\n+**...\n+**\tfcvtps\ts[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, int64_t, vcvtps_s64_f32)\n+/*\n+** convert_vcvtps_s64_f32:\n+**...\n+**\tfcvtps\td[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, uint32_t, vcvtps_u32_f32)\n+/*\n+** convert_vcvtps_u32_f32:\n+**...\n+**\tfcvtpu\ts[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, uint64_t, vcvtps_u64_f32)\n+/*\n+** convert_vcvtps_u64_f32:\n+**...\n+**\tfcvtpu\td[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, int32_t, vcvtas_s32_f32)\n+/*\n+** convert_vcvtas_s32_f32:\n+**...\n+**\tfcvtas\ts[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, int64_t, vcvtas_s64_f32)\n+/*\n+** convert_vcvtas_s64_f32:\n+**...\n+**\tfcvtas\td[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, uint32_t, vcvtas_u32_f32)\n+/*\n+** convert_vcvtas_u32_f32:\n+**...\n+**\tfcvtau\ts[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float32_t, uint64_t, vcvtas_u64_f32)\n+/*\n+** convert_vcvtas_u64_f32:\n+**...\n+**\tfcvtau\td[0-9]+, s[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, int32_t, vcvtd_s32_f64)\n+/*\n+** convert_vcvtd_s32_f64:\n+**...\n+**\tfcvtzs\ts[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, int64_t, vcvtd_s64_f64)\n+/*\n+** convert_vcvtd_s64_f64:\n+**...\n+**\tfcvtzs\td[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, uint32_t, vcvtd_u32_f64)\n+/*\n+** convert_vcvtd_u32_f64:\n+**...\n+**\tfcvtzu\ts[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, uint64_t, vcvtd_u64_f64)\n+/*\n+** convert_vcvtd_u64_f64:\n+**...\n+**\tfcvtzu\td[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, int32_t, vcvtnd_s32_f64)\n+/*\n+** convert_vcvtnd_s32_f64:\n+**...\n+**\tfcvtns\ts[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, int64_t, vcvtnd_s64_f64)\n+/*\n+** convert_vcvtnd_s64_f64:\n+**...\n+**\tfcvtns\td[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, uint32_t, vcvtnd_u32_f64)\n+/*\n+** convert_vcvtnd_u32_f64:\n+**...\n+**\tfcvtnu\ts[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, uint64_t, vcvtnd_u64_f64)\n+/*\n+** convert_vcvtnd_u64_f64:\n+**...\n+**\tfcvtnu\td[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, int32_t, vcvtmd_s32_f64)\n+/*\n+** convert_vcvtmd_s32_f64:\n+**...\n+**\tfcvtms\ts[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, int64_t, vcvtmd_s64_f64)\n+/*\n+** convert_vcvtmd_s64_f64:\n+**...\n+**\tfcvtms\td[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, uint32_t, vcvtmd_u32_f64)\n+/*\n+** convert_vcvtmd_u32_f64:\n+**...\n+**\tfcvtmu\ts[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, uint64_t, vcvtmd_u64_f64)\n+/*\n+** convert_vcvtmd_u64_f64:\n+**...\n+**\tfcvtmu\td[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, int32_t, vcvtpd_s32_f64)\n+/*\n+** convert_vcvtpd_s32_f64:\n+**...\n+**\tfcvtps\ts[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, int64_t, vcvtpd_s64_f64)\n+/*\n+** convert_vcvtpd_s64_f64:\n+**...\n+**\tfcvtps\td[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, uint32_t, vcvtpd_u32_f64)\n+/*\n+** convert_vcvtpd_u32_f64:\n+**...\n+**\tfcvtpu\ts[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, uint64_t, vcvtpd_u64_f64)\n+/*\n+** convert_vcvtpd_u64_f64:\n+**...\n+**\tfcvtpu\td[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, int32_t, vcvtad_s32_f64)\n+/*\n+** convert_vcvtad_s32_f64:\n+**...\n+**\tfcvtas\ts[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, int64_t, vcvtad_s64_f64)\n+/*\n+** convert_vcvtad_s64_f64:\n+**...\n+**\tfcvtas\td[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, uint32_t, vcvtad_u32_f64)\n+/*\n+** convert_vcvtad_u32_f64:\n+**...\n+**\tfcvtau\ts[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float64_t, uint64_t, vcvtad_u64_f64)\n+/*\n+** convert_vcvtad_u64_f64:\n+**...\n+**\tfcvtau\td[0-9]+, d[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, int16_t, vcvth_s16_f16)\n+/*\n+** convert_vcvth_s16_f16:\n+**...\n+**\tfcvtzs\th[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, int32_t, vcvth_s32_f16)\n+/*\n+** convert_vcvth_s32_f16:\n+**...\n+**\tfcvtzs\ts[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, int64_t, vcvth_s64_f16)\n+/*\n+** convert_vcvth_s64_f16:\n+**...\n+**\tfcvtzs\td[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, uint16_t, vcvth_u16_f16)\n+/*\n+** convert_vcvth_u16_f16:\n+**...\n+**\tfcvtzu\th[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, uint32_t, vcvth_u32_f16)\n+/*\n+** convert_vcvth_u32_f16:\n+**...\n+**\tfcvtzu\ts[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, uint64_t, vcvth_u64_f16)\n+/*\n+** convert_vcvth_u64_f16:\n+**...\n+**\tfcvtzu\td[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, int16_t, vcvtah_s16_f16)\n+/*\n+** convert_vcvtah_s16_f16:\n+**...\n+**\tfcvtas\th[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, int32_t, vcvtah_s32_f16)\n+/*\n+** convert_vcvtah_s32_f16:\n+**...\n+**\tfcvtas\ts[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, int64_t, vcvtah_s64_f16)\n+/*\n+** convert_vcvtah_s64_f16:\n+**...\n+**\tfcvtas\td[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, uint16_t, vcvtah_u16_f16)\n+/*\n+** convert_vcvtah_u16_f16:\n+**...\n+**\tfcvtau\th[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, uint32_t, vcvtah_u32_f16)\n+/*\n+** convert_vcvtah_u32_f16:\n+**...\n+**\tfcvtau\ts[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, uint64_t, vcvtah_u64_f16)\n+/*\n+** convert_vcvtah_u64_f16:\n+**...\n+**\tfcvtau\td[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, int16_t, vcvtmh_s16_f16)\n+/*\n+** convert_vcvtmh_s16_f16:\n+**...\n+**\tfcvtms\th[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, int32_t, vcvtmh_s32_f16)\n+/*\n+** convert_vcvtmh_s32_f16:\n+**...\n+**\tfcvtms\ts[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, int64_t, vcvtmh_s64_f16)\n+/*\n+** convert_vcvtmh_s64_f16:\n+**...\n+**\tfcvtms\td[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, uint16_t, vcvtmh_u16_f16)\n+/*\n+** convert_vcvtmh_u16_f16:\n+**...\n+**\tfcvtmu\th[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, uint32_t, vcvtmh_u32_f16)\n+/*\n+** convert_vcvtmh_u32_f16:\n+**...\n+**\tfcvtmu\ts[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, uint64_t, vcvtmh_u64_f16)\n+/*\n+** convert_vcvtmh_u64_f16:\n+**...\n+**\tfcvtmu\td[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, int16_t, vcvtnh_s16_f16)\n+/*\n+** convert_vcvtnh_s16_f16:\n+**...\n+**\tfcvtns\th[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, int32_t, vcvtnh_s32_f16)\n+/*\n+** convert_vcvtnh_s32_f16:\n+**...\n+**\tfcvtns\ts[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, int64_t, vcvtnh_s64_f16)\n+/*\n+** convert_vcvtnh_s64_f16:\n+**...\n+**\tfcvtns\td[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, uint16_t, vcvtnh_u16_f16)\n+/*\n+** convert_vcvtnh_u16_f16:\n+**...\n+**\tfcvtnu\th[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, uint32_t, vcvtnh_u32_f16)\n+/*\n+** convert_vcvtnh_u32_f16:\n+**...\n+**\tfcvtnu\ts[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, uint64_t, vcvtnh_u64_f16)\n+/*\n+** convert_vcvtnh_u64_f16:\n+**...\n+**\tfcvtnu\td[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, int16_t, vcvtph_s16_f16)\n+/*\n+** convert_vcvtph_s16_f16:\n+**...\n+**\tfcvtps\th[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, int32_t, vcvtph_s32_f16)\n+/*\n+** convert_vcvtph_s32_f16:\n+**...\n+**\tfcvtps\ts[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, int64_t, vcvtph_s64_f16)\n+/*\n+** convert_vcvtph_s64_f16:\n+**...\n+**\tfcvtps\td[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, uint16_t, vcvtph_u16_f16)\n+/*\n+** convert_vcvtph_u16_f16:\n+**...\n+**\tfcvtpu\th[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, uint32_t, vcvtph_u32_f16)\n+/*\n+** convert_vcvtph_u32_f16:\n+**...\n+**\tfcvtpu\ts[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+CONVERT_INTRINSIC (float16_t, uint64_t, vcvtph_u64_f16)\n+/*\n+** convert_vcvtph_u64_f16:\n+**...\n+**\tfcvtpu\td[0-9]+, h[0-9]+\n+**...\n+*/\n+\n+\n+CONVERT_INTRINSIC (int32_t, float32_t, vcvts_f32_s32)\n+/*\n+** convert_vcvts_f32_s32:\n+**...\n+**\tscvtf\ts[0-9]+, s[0-9]+\n+**...\n+*/\n+CONVERT_INTRINSIC (uint32_t, float32_t, vcvts_f32_u32)\n+/*\n+** convert_vcvts_f32_u32:\n+**...\n+**\tucvtf\ts[0-9]+, s[0-9]+\n+**...\n+*/\n+CONVERT_INTRINSIC (int64_t, float64_t, vcvtd_f64_s64)\n+/*\n+** convert_vcvtd_f64_s64:\n+**...\n+**\tscvtf\td[0-9]+, d[0-9]+\n+**...\n+*/\n+CONVERT_INTRINSIC (uint64_t, float64_t, vcvtd_f64_u64)\n+/*\n+** convert_vcvtd_f64_u64:\n+**...\n+**\tucvtf\td[0-9]+, d[0-9]+\n+**...\n+*/\n+CONVERT_INTRINSIC (int16_t, float16_t, vcvth_f16_s16)\n+/*\n+** convert_vcvth_f16_s16:\n+**...\n+**\tscvtf\th[0-9]+, h[0-9]+\n+**...\n+*/\n+CONVERT_INTRINSIC (int32_t, float16_t, vcvth_f16_s32)\n+/*\n+** convert_vcvth_f16_s32:\n+**...\n+**\tscvtf\th[0-9]+, s[0-9]+\n+**...\n+*/\n+CONVERT_INTRINSIC (int64_t, float16_t, vcvth_f16_s64)\n+/*\n+** convert_vcvth_f16_s64:\n+**...\n+**\tscvtf\th[0-9]+, d[0-9]+\n+**...\n+*/\n+CONVERT_INTRINSIC (uint16_t, float16_t, vcvth_f16_u16)\n+/*\n+** convert_vcvth_f16_u16:\n+**...\n+**\tucvtf\th[0-9]+, h[0-9]+\n+**...\n+*/\n+CONVERT_INTRINSIC (uint32_t, float16_t, vcvth_f16_u32)\n+/*\n+** convert_vcvth_f16_u32:\n+**...\n+**\tucvtf\th[0-9]+, s[0-9]+\n+**...\n+*/\n+CONVERT_INTRINSIC (uint64_t, float16_t, vcvth_f16_u64)\n+/*\n+** convert_vcvth_f16_u64:\n+**...\n+**\tucvtf\th[0-9]+, d[0-9]+\n+**...\n+*/\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fprcvt.c b/gcc/testsuite/gcc.target/aarch64/fprcvt.c\nnew file mode 100644\nindex 00000000000..1bca48b9a15\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fprcvt.c\n@@ -0,0 +1,147 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-save-temps -fno-inline -O2 -march=armv9-a+fprcvt\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" } } */\n+\n+#include <stdint.h>\n+#include <arm_fp16.h>\n+#include <arm_acle.h>\n+#include <arm_neon.h>\n+\n+#define FORCE_FP_REG(a) asm volatile(\"fmov %d0, %d1\" : \"=w\"(a) : \"w\"(a) :)\n+#define CONVERT(T_FROM, T_TO) \\\n+ void convert_##T_FROM##_to_##T_TO (T_FROM *from, T_TO *to) \\\n+ { \\\n+ T_FROM from_val = *from; \\\n+ FORCE_FP_REG (from_val); \\\n+ T_TO to_val = (T_TO) from_val; \\\n+ FORCE_FP_REG (to_val); \\\n+ *to = to_val; \\\n+ }\n+\n+/*\n+** convert_float16_t_to_int32_t:\n+**...\n+**\tfcvtzs\ts[0-9]+, h[0-9]+\n+**...\n+*/\n+CONVERT (float16_t, int32_t)\n+\n+/*\n+** convert_float64_t_to_int32_t:\n+**...\n+**\tfcvtzs\ts[0-9]+, d[0-9]+\n+**...\n+*/\n+CONVERT (float64_t, int32_t)\n+\n+/*\n+** convert_float16_t_to_int64_t:\n+**...\n+**\tfcvtzs\td[0-9]+, h[0-9]+\n+**...\n+*/\n+CONVERT (float16_t, int64_t)\n+\n+/*\n+** convert_float32_t_to_int64_t:\n+**...\n+**\tfcvtzs\td[0-9]+, s[0-9]+\n+**...\n+*/\n+CONVERT (float32_t, int64_t)\n+\n+/*\n+** convert_float16_t_to_uint32_t:\n+**...\n+**\tfcvtzu\ts[0-9]+, h[0-9]+\n+**...\n+*/\n+CONVERT (float16_t, uint32_t)\n+\n+/*\n+** convert_float64_t_to_uint32_t:\n+**...\n+**\tfcvtzu\ts[0-9]+, d[0-9]+\n+**...\n+*/\n+CONVERT (float64_t, uint32_t)\n+\n+/*\n+** convert_float16_t_to_uint64_t:\n+**...\n+**\tfcvtzu\td[0-9]+, h[0-9]+\n+**...\n+*/\n+CONVERT (float16_t, uint64_t)\n+\n+/*\n+** convert_float32_t_to_uint64_t:\n+**...\n+**\tfcvtzu\td[0-9]+, s[0-9]+\n+**...\n+*/\n+CONVERT (float32_t, uint64_t)\n+\n+/*\n+** convert_int32_t_to_float16_t:\n+**...\n+**\tscvtf\th[0-9]+, s[0-9]+\n+**...\n+*/\n+CONVERT (int32_t, float16_t)\n+\n+/*\n+** convert_int32_t_to_float64_t:\n+**...\n+**\tscvtf\td[0-9]+, s[0-9]+\n+**...\n+*/\n+CONVERT (int32_t, float64_t)\n+\n+/*\n+** convert_int64_t_to_float16_t:\n+**...\n+**\tscvtf\th[0-9]+, d[0-9]+\n+**...\n+*/\n+CONVERT (int64_t, float16_t)\n+\n+/*\n+** convert_int64_t_to_float32_t:\n+**...\n+**\tscvtf\ts[0-9]+, d[0-9]+\n+**...\n+*/\n+CONVERT (int64_t, float32_t)\n+\n+/*\n+** convert_uint32_t_to_float16_t:\n+**...\n+**\tucvtf\th[0-9]+, s[0-9]+\n+**...\n+*/\n+CONVERT (uint32_t, float16_t)\n+\n+/*\n+** convert_uint32_t_to_float64_t:\n+**...\n+**\tucvtf\td[0-9]+, s[0-9]+\n+**...\n+*/\n+CONVERT (uint32_t, float64_t)\n+\n+/*\n+** convert_uint64_t_to_float16_t:\n+**...\n+**\tucvtf\th[0-9]+, d[0-9]+\n+**...\n+*/\n+CONVERT (uint64_t, float16_t)\n+\n+/*\n+** convert_uint64_t_to_float32_t:\n+**...\n+**\tucvtf\ts[0-9]+, d[0-9]+\n+**...\n+*/\n+CONVERT (uint64_t, float32_t)\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fprcvt.x b/gcc/testsuite/gcc.target/aarch64/fprcvt.x\nnew file mode 100644\nindex 00000000000..a4e8fc39505\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fprcvt.x\n@@ -0,0 +1,87 @@\n+extern GPF SUFFIX(trunc) (GPF);\n+extern GPF SUFFIX(ceil) (GPF);\n+extern GPF SUFFIX(floor) (GPF);\n+extern GPF SUFFIX(round) (GPF);\n+\n+#define FORCE_FP_REG(a) asm volatile(\"fmov %d0, %d1\" : \"=w\"(a) : \"w\"(a) :)\n+\n+GPI test1a (GPF x) {\n+ FORCE_FP_REG(x);\n+ GPI res = SUFFIX(__builtin_trunc)(x);\n+ FORCE_FP_REG(res);\n+ return res;\n+}\n+\n+GPI test1b (GPF x)\n+{\n+ FORCE_FP_REG(x);\n+ GPI res = SUFFIX(trunc)(x);\n+ FORCE_FP_REG(res);\n+ return res;\n+}\n+\n+GPI test2a (GPF x)\n+{\n+ FORCE_FP_REG(x);\n+ GPI res = SUFFIX(__builtin_lceil)(x);\n+ FORCE_FP_REG(res);\n+ return res;\n+}\n+\n+GPI test2b (GPF x)\n+{\n+ FORCE_FP_REG(x);\n+ GPI res = SUFFIX(ceil)(x);\n+ FORCE_FP_REG(res);\n+ return res;\n+}\n+\n+GPI test2c (GPF x)\n+{\n+ FORCE_FP_REG(x);\n+ GPI res = SUFFIX(__builtin_ceil)(x);\n+ FORCE_FP_REG(res);\n+ return res;\n+}\n+\n+GPI test3a (GPF x)\n+{\n+ FORCE_FP_REG(x);\n+ GPI res = SUFFIX(__builtin_lfloor)(x);\n+ FORCE_FP_REG(res);\n+ return res;\n+}\n+\n+GPI test3b (GPF x)\n+{\n+ FORCE_FP_REG(x);\n+ GPI res = SUFFIX(floor)(x);\n+ FORCE_FP_REG(res);\n+ return res;\n+}\n+\n+GPI test3c (GPF x)\n+{\n+ FORCE_FP_REG(x);\n+ GPI res = SUFFIX(__builtin_floor)(x);\n+ FORCE_FP_REG(res);\n+ return res;\n+}\n+\n+GPI test4a (GPF x)\n+{\n+ FORCE_FP_REG(x);\n+ GPI res = SUFFIX(__builtin_round)(x);\n+ FORCE_FP_REG(res);\n+ return res;\n+}\n+\n+GPI test4b (GPF x)\n+{\n+ FORCE_FP_REG(x);\n+ GPI res = SUFFIX(round)(x);\n+ FORCE_FP_REG(res);\n+ return res;\n+}\n+\n+\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fprcvt_float32_int32.c b/gcc/testsuite/gcc.target/aarch64/fprcvt_float32_int32.c\nnew file mode 100644\nindex 00000000000..6a086339e1b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fprcvt_float32_int32.c\n@@ -0,0 +1,18 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv9-a+fprcvt\" } */\n+\n+#include <stdint.h>\n+#include <arm_neon.h>\n+\n+#define GPF float32_t\n+#define SUFFIX(x) x##f\n+#define GPI int32_t\n+\n+#include \"fprcvt.x\"\n+\n+/* { dg-final { scan-assembler-times \"fcvtzs\\ts\\[0-9\\]+, *s\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtps\\td\\[0-9\\]+, *s\\[0-9\\]\" 1 } } */\n+/* { dg-final { scan-assembler-times \"fcvtps\\ts\\[0-9\\]+, *s\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtms\\td\\[0-9\\]+, *s\\[0-9\\]\" 1 } } */\n+/* { dg-final { scan-assembler-times \"fcvtms\\ts\\[0-9\\]+, *s\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtas\\ts\\[0-9\\]+, *s\\[0-9\\]\" 2 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fprcvt_float32_int64.c b/gcc/testsuite/gcc.target/aarch64/fprcvt_float32_int64.c\nnew file mode 100644\nindex 00000000000..22464157d2f\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fprcvt_float32_int64.c\n@@ -0,0 +1,16 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv9-a+fprcvt\" } */\n+\n+#include <stdint.h>\n+#include <arm_neon.h>\n+\n+#define GPF float32_t\n+#define SUFFIX(x) x##f\n+#define GPI int64_t\n+\n+#include \"fprcvt.x\"\n+\n+/* { dg-final { scan-assembler-times \"fcvtzs\\td\\[0-9\\]+, *s\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtps\\td\\[0-9\\]+, *s\\[0-9\\]\" 3 } } */\n+/* { dg-final { scan-assembler-times \"fcvtms\\td\\[0-9\\]+, *s\\[0-9\\]\" 3 } } */\n+/* { dg-final { scan-assembler-times \"fcvtas\\td\\[0-9\\]+, *s\\[0-9\\]\" 2 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fprcvt_float32_uint32.c b/gcc/testsuite/gcc.target/aarch64/fprcvt_float32_uint32.c\nnew file mode 100644\nindex 00000000000..87e4686edd3\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fprcvt_float32_uint32.c\n@@ -0,0 +1,18 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv9-a+fprcvt\" } */\n+\n+#include <stdint.h>\n+#include <arm_neon.h>\n+\n+#define GPF float32_t\n+#define SUFFIX(x) x##f\n+#define GPI uint32_t\n+\n+#include \"fprcvt.x\"\n+\n+/* { dg-final { scan-assembler-times \"fcvtzu\\ts\\[0-9\\]+, *s\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtps\\td\\[0-9\\]+, *s\\[0-9\\]\" 1 } } */\n+/* { dg-final { scan-assembler-times \"fcvtpu\\ts\\[0-9\\]+, *s\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtms\\td\\[0-9\\]+, *s\\[0-9\\]\" 1 } } */\n+/* { dg-final { scan-assembler-times \"fcvtmu\\ts\\[0-9\\]+, *s\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtau\\ts\\[0-9\\]+, *s\\[0-9\\]\" 2 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fprcvt_float32_uint64.c b/gcc/testsuite/gcc.target/aarch64/fprcvt_float32_uint64.c\nnew file mode 100644\nindex 00000000000..76922b33edf\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fprcvt_float32_uint64.c\n@@ -0,0 +1,18 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv9-a+fprcvt\" } */\n+\n+#include <stdint.h>\n+#include <arm_neon.h>\n+\n+#define GPF float32_t\n+#define SUFFIX(x) x##f\n+#define GPI uint64_t\n+\n+#include \"fprcvt.x\"\n+\n+/* { dg-final { scan-assembler-times \"fcvtzu\\td\\[0-9\\]+, *s\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtps\\td\\[0-9\\]+, *s\\[0-9\\]\" 1 } } *\n+/* { dg-final { scan-assembler-times \"fcvtpu\\td\\[0-9\\]+, *s\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtms\\td\\[0-9\\]+, *s\\[0-9\\]\" 1 } } */\n+/* { dg-final { scan-assembler-times \"fcvtmu\\td\\[0-9\\]+, *s\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtau\\td\\[0-9\\]+, *s\\[0-9\\]\" 2 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fprcvt_float64_int32.c b/gcc/testsuite/gcc.target/aarch64/fprcvt_float64_int32.c\nnew file mode 100644\nindex 00000000000..dd772600e0d\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fprcvt_float64_int32.c\n@@ -0,0 +1,18 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv9-a+fprcvt\" } */\n+\n+#include <stdint.h>\n+#include <arm_neon.h>\n+\n+#define GPF float64_t\n+#define SUFFIX(x) x\n+#define GPI int32_t\n+\n+#include \"fprcvt.x\"\n+\n+/* { dg-final { scan-assembler-times \"fcvtzs\\ts\\[0-9\\]+, *d\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtps\\td\\[0-9\\]+, *d\\[0-9\\]\" 1 } } */\n+/* { dg-final { scan-assembler-times \"fcvtps\\ts\\[0-9\\]+, *d\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtms\\td\\[0-9\\]+, *d\\[0-9\\]\" 1 } } */\n+/* { dg-final { scan-assembler-times \"fcvtms\\ts\\[0-9\\]+, *d\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtas\\ts\\[0-9\\]+, *d\\[0-9\\]\" 2 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fprcvt_float64_int64.c b/gcc/testsuite/gcc.target/aarch64/fprcvt_float64_int64.c\nnew file mode 100644\nindex 00000000000..c28960a4601\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fprcvt_float64_int64.c\n@@ -0,0 +1,16 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv9-a+fprcvt\" } */\n+\n+#include <stdint.h>\n+#include <arm_neon.h>\n+\n+#define GPF float64_t\n+#define SUFFIX(x) x\n+#define GPI int64_t\n+\n+#include \"fprcvt.x\"\n+\n+/* { dg-final { scan-assembler-times \"fcvtzs\\td\\[0-9\\]+, *d\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtps\\td\\[0-9\\]+, *d\\[0-9\\]\" 3 } } */\n+/* { dg-final { scan-assembler-times \"fcvtms\\td\\[0-9\\]+, *d\\[0-9\\]\" 3 } } */\n+/* { dg-final { scan-assembler-times \"fcvtas\\td\\[0-9\\]+, *d\\[0-9\\]\" 2 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fprcvt_float64_uint32.c b/gcc/testsuite/gcc.target/aarch64/fprcvt_float64_uint32.c\nnew file mode 100644\nindex 00000000000..7dcd0cc41f6\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fprcvt_float64_uint32.c\n@@ -0,0 +1,18 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv9-a+fprcvt\" } */\n+\n+#include <stdint.h>\n+#include <arm_neon.h>\n+\n+#define GPF float64_t\n+#define SUFFIX(x) x\n+#define GPI uint32_t\n+\n+#include \"fprcvt.x\"\n+\n+/* { dg-final { scan-assembler-times \"fcvtzu\\ts\\[0-9\\]+, *d\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtps\\td\\[0-9\\]+, *d\\[0-9\\]\" 1 } } *\n+/* { dg-final { scan-assembler-times \"fcvtpu\\ts\\[0-9\\]+, *d\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtms\\td\\[0-9\\]+, *d\\[0-9\\]\" 1 } } */\n+/* { dg-final { scan-assembler-times \"fcvtmu\\ts\\[0-9\\]+, *d\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtau\\ts\\[0-9\\]+, *d\\[0-9\\]\" 2 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fprcvt_float64_uint64.c b/gcc/testsuite/gcc.target/aarch64/fprcvt_float64_uint64.c\nnew file mode 100644\nindex 00000000000..f0d385d44c1\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fprcvt_float64_uint64.c\n@@ -0,0 +1,18 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=armv9-a+fprcvt\" } */\n+\n+#include <stdint.h>\n+#include <arm_neon.h>\n+\n+#define GPF float64_t\n+#define SUFFIX(x) x\n+#define GPI uint64_t\n+\n+#include \"fprcvt.x\"\n+\n+/* { dg-final { scan-assembler-times \"fcvtzu\\td\\[0-9\\]+, *d\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtpu\\td\\[0-9\\]+, *d\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtps\\td\\[0-9\\]+, *d\\[0-9\\]\" 1 } } */\n+/* { dg-final { scan-assembler-times \"fcvtmu\\td\\[0-9\\]+, *d\\[0-9\\]\" 2 } } */\n+/* { dg-final { scan-assembler-times \"fcvtms\\td\\[0-9\\]+, *d\\[0-9\\]\" 1 } } */\n+/* { dg-final { scan-assembler-times \"fcvtau\\td\\[0-9\\]+, *d\\[0-9\\]\" 2 } } */\n", "prefixes": [ "2/2" ] }