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GET /api/patches/2231301/?format=api
{ "id": 2231301, "url": "http://patchwork.ozlabs.org/api/patches/2231301/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260430143920.22708-2-xry111@xry111.site/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430143920.22708-2-xry111@xry111.site>", "list_archive_url": null, "date": "2026-04-30T14:35:47", "name": "LoongArch: harden SSP canary set and test routines [PR 125049]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "62d32d6b786d68023443ca540a50b182d0060e11", "submitter": { "id": 84026, "url": "http://patchwork.ozlabs.org/api/people/84026/?format=api", "name": "Xi Ruoyao", "email": "xry111@xry111.site" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260430143920.22708-2-xry111@xry111.site/mbox/", "series": [ { "id": 502317, "url": "http://patchwork.ozlabs.org/api/series/502317/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502317", "date": "2026-04-30T14:35:47", "name": "LoongArch: harden SSP canary set and test routines [PR 125049]", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502317/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231301/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231301/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=xry111.site header.i=@xry111.site header.a=rsa-sha256\n header.s=default header.b=UFZ1Zsnj;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n\tdkim=pass (1024-bit key,\n unprotected) header.d=xry111.site header.i=@xry111.site header.a=rsa-sha256\n header.s=default header.b=UFZ1Zsnj", "sourceware.org;\n dmarc=pass (p=reject dis=none) header.from=xry111.site", "sourceware.org; spf=pass smtp.mailfrom=xry111.site", "server2.sourceware.org;\n arc=none smtp.remote-ip=89.208.246.23" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5xgJ5bKPz1yHZ\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 01 May 2026 00:40:59 +1000 (AEST)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id A93D943B5514\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 14:40:57 +0000 (GMT)", "from xry111.site (xry111.site [89.208.246.23])\n by sourceware.org (Postfix) with ESMTPS id 4A3BA4BAD168\n for <gcc-patches@gcc.gnu.org>; Thu, 30 Apr 2026 14:40:28 +0000 (GMT)", "from stargazer (unknown\n [IPv6:240e:45d:230:59b8:30ac:66a4:df02:3faf])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n (Client did not present a certificate)\n (Authenticated sender: xry111@xry111.site)\n by xry111.site (Postfix) with ESMTPSA id 03E6365992;\n Thu, 30 Apr 2026 10:40:22 -0400 (EDT)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org A93D943B5514", "OpenDKIM Filter v2.11.0 sourceware.org 4A3BA4BAD168" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org 4A3BA4BAD168", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 4A3BA4BAD168", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1777560028; cv=none;\n b=cKIqFz50mmFYlcO3EljmjJM9xBozZPQVU9W5JEqebHsWoCIka8WMLaz+LUxLyDG5tvQm4W3Rflblj+OGv8jP5+YBVVSQb0JtB+D5HBO+Q4D2WOqsZ4PR4SFV+KB3dxTJNx5oHN1Z7NRDXGVAKtVfAbRIFGK0mSxBAydynCYn2+I=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1777560028; c=relaxed/simple;\n bh=c4w/vNxKMlT3t3FXDxA87oVUskL92xbj3onrR2noshA=;\n h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version;\n b=kPl/T4hwkXu1zhTJP5SgN46tWWlBcj29sW8OWKggzaeUoAUtSIa9x3Coy1rSS57GqOBBstY8/B5nHpiHPQrMNrT9ABZvC1yZFDVArfb76MsXNMwcw9chFkrpTeHbm0XgLDyDGVu2rMlrSBpdTKyKEzjyJSaubLErd58VXtMCfeQ=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=xry111.site;\n s=default; t=1777560025;\n bh=q9yicrV8EWMPzDxPt1sWX3KmVqXlnU/CzN5X1d7NZn8=;\n h=From:To:Cc:Subject:Date:From;\n b=UFZ1Zsnj3MhU3ghhlvr+rgHwy0O4fKRSZymLzmop/DUHhINAsUnlkpo1XiURP4owq\n IIfQVPI66ZGVywu2gAkoJ2cWMEvPp8+oN3I/+wxK2np0XJPWuPUt/i64GNPDsWQ/0t\n Pl8/VcAdBXjimQc6bNnG0Dz4AWir5NCzi5fzv8TI=", "From": "Xi Ruoyao <xry111@xry111.site>", "To": "gcc-patches@gcc.gnu.org", "Cc": "Lulu Cheng <chenglulu@loongson.cn>, WANG Xuerui <i@xen0n.name>,\n Mingcong Bai <jeffbai@aosc.io>, Zixing Liu <liushuyu@aosc.io>,\n Jingyao Zhong <220245569@seu.edu.cn>, Xi Ruoyao <xry111@xry111.site>", "Subject": "[PATCH] LoongArch: harden SSP canary set and test routines [PR\n 125049]", "Date": "Thu, 30 Apr 2026 22:35:47 +0800", "Message-ID": "<20260430143920.22708-2-xry111@xry111.site>", "X-Mailer": "git-send-email 2.54.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Add the stack_protect_combined_{set,test} expanders to expand the\nroutines as unsplitable insns which does not leave any sensitive data\n(the canary value, the canary address, and all the intermediate values\nused materializing the address) in a register. This prevents the\nattacker from defeating SSP by probing the canary value from the\nregister context or overwriting the address spilled onto the stack.\n\n\tPR target/125049\n\ngcc/\n\n\t* config/loongarch/predicates.md (ssp_operand): New\n\tdefine_predicate.\n\t(ssp_normal_operand): New define_predicate.\n\t* config/loongarch/constraints.md (ZE): New define_constraint.\n\t(ZF): New define_constraint.\n\t* config/loongarch/loongarch.md (UNSPEC_SSP): New unspec.\n\t(cbranch4): Add \"@\" to create gen_cbranch4(machine_mode, ...).\n\t(@stack_protect_combined_set_normal_<mode>): New define_insn.\n\t(@stack_protect_combined_set_extreme_<mode>): New define_insn.\n\t(@stack_protect_combined_test_internal_<mode>): New define_insn.\n\t(stack_protect_combined_set): New define_expand.\n\t(stack_protect_combined_test): New define_expand.\n\t* config/loongarch/loongarch-protos.h\n\t(loongarch_output_asm_load_canary): Declare.\n\t* config/loongarch/loongarch.cc (loongarch_print_operand): Allow\n\t'v' to print d/w for DImode/SImode.\n\t(loongarch_output_asm_load_canary): Implement.\n\ngcc/testsuite/\n\n\t* gcc.target/loongarch/pr125049.c: New test.\n---\n\nBootstrapped and regtested on loongarch64-linux-gnu (with\n--enable-default-ssp). Ok for trunk? And should we backport this?\n\n gcc/config/loongarch/constraints.md | 9 ++\n gcc/config/loongarch/loongarch-protos.h | 1 +\n gcc/config/loongarch/loongarch.cc | 51 +++++++++++\n gcc/config/loongarch/loongarch.md | 88 ++++++++++++++++++-\n gcc/config/loongarch/predicates.md | 8 ++\n gcc/testsuite/gcc.target/loongarch/pr125049.c | 50 +++++++++++\n 6 files changed, 206 insertions(+), 1 deletion(-)\n create mode 100644 gcc/testsuite/gcc.target/loongarch/pr125049.c", "diff": "diff --git a/gcc/config/loongarch/constraints.md b/gcc/config/loongarch/constraints.md\nindex 2b10d685137..b681cf95205 100644\n--- a/gcc/config/loongarch/constraints.md\n+++ b/gcc/config/loongarch/constraints.md\n@@ -370,3 +370,12 @@ (define_address_constraint \"ZD\"\n and offset that is suitable for use in instructions with the same\n addressing mode as @code{preld}.\"\n (match_test \"loongarch_12bit_offset_address_p (op, mode)\"))\n+\n+(define_constraint \"ZE\"\n+ \"A symbolic suitable as stack canary in the normal/medium code model.\"\n+ (match_operand 0 \"ssp_normal_operand\"))\n+\n+(define_constraint \"ZF\"\n+ \"A symbolic suitable as stack canary, but in the extreme code model.\"\n+ (and (match_operand 0 \"ssp_operand\")\n+ (not (match_operand 0 \"ssp_normal_operand\"))))\ndiff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h\nindex 11575a15454..e67addf36e3 100644\n--- a/gcc/config/loongarch/loongarch-protos.h\n+++ b/gcc/config/loongarch/loongarch-protos.h\n@@ -235,4 +235,5 @@ extern bool loongarch_parse_fmv_features (location_t, string_slice,\n extern void get_feature_mask_for_version (tree, loongarch_fmv_feature_mask *,\n \t\t\t\t\t auto_vec<unsigned int> *);\n extern int loongarch_compare_version_priority (tree, tree);\n+extern void loongarch_output_asm_load_canary (rtx reg, rtx canary, rtx tmp);\n #endif /* ! GCC_LOONGARCH_PROTOS_H */\ndiff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc\nindex 134ed47afdf..bdafcd5c539 100644\n--- a/gcc/config/loongarch/loongarch.cc\n+++ b/gcc/config/loongarch/loongarch.cc\n@@ -6935,12 +6935,14 @@ loongarch_print_operand (FILE *file, rtx op, int letter)\n \tcase E_V4SFmode:\n \tcase E_V8SImode:\n \tcase E_V8SFmode:\n+\tcase E_SImode:\n \t fprintf (file, \"w\");\n \t break;\n \tcase E_V2DImode:\n \tcase E_V2DFmode:\n \tcase E_V4DImode:\n \tcase E_V4DFmode:\n+\tcase E_DImode:\n \t fprintf (file, \"d\");\n \t break;\n \tdefault:\n@@ -12110,6 +12112,55 @@ loongarch_option_same_function_versions (string_slice str1, const_tree,\n return feature_mask1 == feature_mask2;\n }\n \n+/* Output assembly to materialize the address of the stack canary value\n+ into reg. The third argument, tmp, should be and should only be\n+ non-NULL if the extreme code model is effective for the canary. If\n+ the fourth arugment, load, is true, the canary value is loaded into\n+ the register.\n+\n+ The assembly cannot be splitted due to security reason. */\n+void\n+loongarch_output_asm_load_canary (rtx reg, rtx canary, rtx tmp)\n+{\n+ gcc_checking_assert (ssp_operand (canary, VOIDmode));\n+ gcc_checking_assert ((!tmp) == ssp_normal_operand (canary, VOIDmode));\n+ gcc_checking_assert (register_operand (reg, Pmode));\n+\n+ rtx op[] = {reg, canary, tmp};\n+ bool got = (loongarch_classify_symbol (canary) == SYMBOL_GOT_DISP);\n+ bool need_ld = false;\n+\n+ if (la_opt_explicit_relocs != EXPLICIT_RELOCS_ALWAYS)\n+ {\n+ if (got)\n+\toutput_asm_insn (tmp ? \"la.global\\t%0,%2,%1\" : \"la.global\\t%0,%1\",\n+\t\t\t op);\n+ else\n+\toutput_asm_insn (tmp ? \"la.local\\t%0,%2,%1\" : \"la.local\\t%0,%1\",\n+\t\t\t op);\n+\n+ need_ld = true;\n+ }\n+ else\n+ {\n+ output_asm_insn (\"pcalau12i\\t%0,%r1\", op);\n+ if (!tmp)\n+\toutput_asm_insn (\"ld.%v0\\t%0,%0,%L1\", op);\n+ else\n+\t{\n+\t output_asm_insn (\"addi.d\\t%2,$r0,%L1\", op);\n+\t output_asm_insn (\"lu32i.d\\t%2,%R1\", op);\n+\t output_asm_insn (\"lu52i.d\\t%2,%2,%H1\", op);\n+\t output_asm_insn (\"ldx.d\\t%0,%0,%2\", op);\n+\t}\n+\n+ need_ld = got;\n+ }\n+\n+ if (need_ld)\n+ output_asm_insn (\"ld.%v0\\t%0,%0,0\", op);\n+}\n+\n /* Initialize the GCC target structure. */\n #undef TARGET_ASM_ALIGNED_HI_OP\n #define TARGET_ASM_ALIGNED_HI_OP \"\\t.half\\t\"\ndiff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md\nindex 1732e7c7d32..1fea712f668 100644\n--- a/gcc/config/loongarch/loongarch.md\n+++ b/gcc/config/loongarch/loongarch.md\n@@ -83,6 +83,8 @@ (define_c_enum \"unspec\" [\n UNSPEC_LOAD_SYMBOL_OFFSET64\n UNSPEC_LA_PCREL_64_PART1\n UNSPEC_LA_PCREL_64_PART2\n+\n+ UNSPEC_SSP\n ])\n \n (define_c_enum \"unspecv\" [\n@@ -3686,7 +3688,7 @@ (define_insn \"*branch_equality<mode>_inverted\"\n ;; QImode values so we can force zero-extension.\n (define_mode_iterator BR [(QI \"TARGET_64BIT\") SI (DI \"TARGET_64BIT\")])\n \n-(define_expand \"cbranch<mode>4\"\n+(define_expand \"@cbranch<mode>4\"\n [(set (pc)\n \t(if_then_else (match_operator 0 \"comparison_operator\"\n \t\t\t[(match_operand:BR 1 \"register_operand\")\n@@ -5036,6 +5038,90 @@ (define_insn_and_rewrite \"simple_store<mode>\"\n operands[0] = loongarch_rewrite_mem_for_simple_ldst (operands[0]);\n })\n \n+;; Set and check against stack canary without leaving it in a register.\n+;; DO NOT ATTEMPT TO SPLIT THESE INSNS! It's important for security reason\n+;; that the canary value does not live beyond the life of this sequence.\n+\n+(define_insn \"@stack_protect_combined_set_normal_<mode>\"\n+ [(set (match_operand:P 0 \"memory_operand\" \"=m,ZC\")\n+ (unspec:P [(mem:P (match_operand:P 1 \"ssp_normal_operand\"))]\n+\t\t UNSPEC_SSP))\n+ (set (match_scratch:P 2 \"=&r,&r\") (const_int 0))]\n+ \"\"\n+{\n+ loongarch_output_asm_load_canary (operands[2], operands[1], NULL_RTX);\n+ output_asm_insn (which_alternative ? \"stptr.d\\t%2,%0\" : \"st.d\\t%2,%0\",\n+\t\t operands);\n+ return \"ori\\t%2,$r0,0\";\n+}\n+ [(set_attr \"type\" \"store\")\n+ (set_attr \"length\" \"20\")])\n+\n+(define_insn \"@stack_protect_combined_set_extreme_<mode>\"\n+ [(set (match_operand:P 0 \"memory_operand\" \"=m,ZC\")\n+ (unspec:P [(mem:P (match_operand:P 1 \"ssp_operand\"))] UNSPEC_SSP))\n+ (set (match_scratch:P 2 \"=&r,&r\") (const_int 0))\n+ (set (match_scratch:P 3 \"=&r,&r\") (const_int 0))]\n+ \"\"\n+{\n+ loongarch_output_asm_load_canary (operands[2], operands[1], operands[3]);\n+ output_asm_insn (which_alternative ? \"stptr.d\\t%2,%0\" : \"st.d\\t%2,%0\",\n+\t\t operands);\n+ return \"ori\\t%2,$r0,0\\n\\tori\\t%3,$r0,0\";\n+}\n+ [(set_attr \"type\" \"store\")\n+ (set_attr \"length\" \"36\")])\n+\n+(define_insn \"@stack_protect_combined_test_internal_<mode>\"\n+ [(set (match_operand:P 0 \"register_operand\" \"=r,r,&r,&r\")\n+\t(xor:P\n+\t (match_operand:P 1 \"memory_operand\" \"=m,ZC,m,ZC\")\n+\t (unspec:P\n+\t [(mem:P (match_operand:P 2 \"ssp_operand\" \"ZE,ZE,ZF,ZF\"))]\n+\t UNSPEC_SSP)))\n+ (set (match_scratch:P 3 \"=&r,&r,&r,&r\") (const_int 0))]\n+ \"\"\n+{\n+ rtx t = (which_alternative >= 2 ? operands[0] : NULL_RTX);\n+ loongarch_output_asm_load_canary (operands[3], operands[2], t);\n+ output_asm_insn ((which_alternative & 1) ? \"ldptr.d\\t%0,%1\"\n+\t\t\t\t\t : \"ld.d\\t%0,%1\",\n+\t\t operands);\n+ return \"xor\\t%0,%0,%3\\n\\tori\\t%3,$r0,0\";\n+}\n+ [(set_attr \"type\" \"load,load,load,load\")\n+ (set_attr \"length\" \"24,24,36,36\")])\n+\n+(define_expand \"stack_protect_combined_set\"\n+ [(match_operand 0 \"memory_operand\")\n+ (match_operand 1 \"memory_operand\")]\n+ \"\"\n+{\n+ rtx canary = XEXP (operands[1], 0);\n+ auto fn = (ssp_normal_operand (canary, VOIDmode)\n+\t ? gen_stack_protect_combined_set_normal\n+\t : gen_stack_protect_combined_set_extreme);\n+\n+ emit_insn (fn (Pmode, operands[0], canary));\n+ DONE;\n+})\n+\n+(define_expand \"stack_protect_combined_test\"\n+ [(match_operand 0 \"memory_operand\")\n+ (match_operand 1 \"memory_operand\")\n+ (match_operand 2 \"\")]\n+ \"\"\n+{\n+ rtx t = gen_reg_rtx (Pmode);\n+ rtx canary = XEXP (operands[1], 0);\n+ emit_insn (gen_stack_protect_combined_test_internal (Pmode, t,\n+\t\t\t\t\t\t operands[0],\n+\t\t\t\t\t\t canary));\n+ rtx cond = gen_rtx_EQ (VOIDmode, t, const0_rtx);\n+ emit_jump_insn (gen_cbranch4 (Pmode, cond, t, const0_rtx, operands[2]));\n+ DONE;\n+})\n+\n ;; Synchronization instructions.\n \n (include \"sync.md\")\ndiff --git a/gcc/config/loongarch/predicates.md b/gcc/config/loongarch/predicates.md\nindex da46de8ec04..af3b770c4e9 100644\n--- a/gcc/config/loongarch/predicates.md\n+++ b/gcc/config/loongarch/predicates.md\n@@ -610,6 +610,14 @@ (define_predicate \"symbolic_off64_or_reg_operand\"\n (ior (match_operand 0 \"register_operand\")\n (match_operand 0 \"symbolic_off64_operand\")))\n \n+;; Currently stack canary must be the global symbol __stack_chk_guard.\n+(define_predicate \"ssp_operand\" (match_code \"symbol_ref\"))\n+\n+;; If the stack canary is within the normal/medium code model.\n+(define_predicate \"ssp_normal_operand\"\n+ (and (match_operand 0 \"ssp_operand\")\n+ (not (match_operand 0 \"symbolic_off64_operand\"))))\n+\n (define_predicate \"equality_operator\"\n (match_code \"eq,ne\"))\n \ndiff --git a/gcc/testsuite/gcc.target/loongarch/pr125049.c b/gcc/testsuite/gcc.target/loongarch/pr125049.c\nnew file mode 100644\nindex 00000000000..cfe036e2061\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/loongarch/pr125049.c\n@@ -0,0 +1,50 @@\n+/* PR 125049: ensure stack canary and its address are not leaked. */\n+/* { dg-options \"-O2 -fstack-protector-strong -ffixed-r30 -ffixed-r31\" } */\n+/* { dg-do run } */\n+/* { dg-require-effective-target fstack_protector } */\n+\n+extern long __stack_chk_guard;\n+register long s7 asm (\"s7\"), *s8 asm (\"s8\");\n+\n+[[gnu::zero_call_used_regs (\"all\"), gnu::noipa]] void\n+init_test (void)\n+{\n+ s7 = __stack_chk_guard;\n+ s8 = &__stack_chk_guard;\n+}\n+\n+[[gnu::always_inline]] static inline void\n+check_reg (void)\n+{\n+#pragma GCC unroll 30\n+ for (int i = 4; i < 30; i++)\n+ asm goto (\n+ \"beq $r%0,$s7,%l[error]\\n\\t\"\n+ \"beq $r%0,$s8,%l[error]\\n\\t\"\n+ :\n+ : \"i\" (i)\n+ :\n+ : error\n+ );\n+ return;\n+error:\n+ __builtin_trap ();\n+}\n+\n+[[gnu::noipa]] void\n+test (void)\n+{\n+ char buf[256];\n+ asm (\"\":\"+m\"(buf));\n+\n+ check_reg ();\n+}\n+\n+int\n+main (void)\n+{\n+ init_test ();\n+ test ();\n+\n+ check_reg ();\n+}\n", "prefixes": [] }