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GET /api/patches/2231291/?format=api
{ "id": 2231291, "url": "http://patchwork.ozlabs.org/api/patches/2231291/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/CAMe9rOqfXXeWOO0p9ZkfWPJeoZPwwav17gXtUg+_axqNN9rjRA@mail.gmail.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<CAMe9rOqfXXeWOO0p9ZkfWPJeoZPwwav17gXtUg+_axqNN9rjRA@mail.gmail.com>", "list_archive_url": null, "date": "2026-04-30T14:07:19", "name": "x86_cse: Add X86_CSE_CONST_VECTOR", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b6e4f30c9326a7252e3d9c7f479128ff413fbbbd", "submitter": { "id": 4387, "url": "http://patchwork.ozlabs.org/api/people/4387/?format=api", "name": "H.J. Lu", "email": "hjl.tools@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/CAMe9rOqfXXeWOO0p9ZkfWPJeoZPwwav17gXtUg+_axqNN9rjRA@mail.gmail.com/mbox/", "series": [ { "id": 502310, "url": "http://patchwork.ozlabs.org/api/series/502310/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502310", "date": "2026-04-30T14:07:19", "name": "x86_cse: Add X86_CSE_CONST_VECTOR", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502310/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231291/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231291/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=fq2i+D0I;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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Thu, 30 Apr 2026\n 07:07:57 -0700 (PDT)", "MIME-Version": "1.0", "From": "\"H.J. Lu\" <hjl.tools@gmail.com>", "Date": "Thu, 30 Apr 2026 22:07:19 +0800", "X-Gm-Features": "AVHnY4LJA3C3NOQm4uZZ_TlQ4CwrRHYV0T8yqX6BzG3a3eOlQphXNUdgdThDSTo", "Message-ID": "\n <CAMe9rOqfXXeWOO0p9ZkfWPJeoZPwwav17gXtUg+_axqNN9rjRA@mail.gmail.com>", "Subject": "[PATCH] x86_cse: Add X86_CSE_CONST_VECTOR", "To": "GCC Patches <gcc-patches@gcc.gnu.org>, Uros Bizjak <ubizjak@gmail.com>,\n Hongtao Liu <hongtao.liu@intel.com>", "Content-Type": "multipart/mixed; boundary=\"000000000000c128fe0650adfd20\"", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Add X86_CSE_CONST_VECTOR for native CONST_VECTOR:\n\n(insn 25 23 234 4 (set (reg:V16QI 135)\n (const_vector:V16QI [\n (const_int -1 [0xffffffffffffffff]) repeated x16\n ])) \"bar-2.c\":10:16 discrim 67584 2453 {movv16qi_internal}\n (nil))\n\nand constant integer load:\n\n(insn 280 8 279 2 (set (subreg:HI (reg:V2QI 172) 0)\n (const_int -1 [0xffffffffffffffff])) -1\n (nil))\n...\n(insn 110 39 194 9 (set (reg:V2QI 147)\n (reg:V2QI 172)) 2089 {*movv2qi_internal}\n (expr_list:REG_EQUAL (const_vector:V2QI [\n (const_int -1 [0xffffffffffffffff]) repeated x2\n ])\n (nil)))\n\nconverted from\n\n(insn 111 87 121 18 (set (reg:V2QI 147)\n (mem/u/c:V2QI (symbol_ref/u:DI (\"*.LC0\") [flags 0x2]) [0 S2\nA16])) 2089 {*movv2qi_internal}\n (expr_list:REG_EQUAL (const_vector:V2QI [\n (const_int -1 [0xffffffffffffffff]) repeated x2])\n (nil)))\n\nKeep redundant constant integer load when crossing a function call since\nit is faster than save and restore an integer register.\n\nConvert CONST_VECTOR load no larger than integer register to constant\ninteger load even if there is no redundant CONST_VECTOR load.\n\nTested on Linux/x86-64 and Linux/i686.\n\ngcc/\n\nPR target/125100\n* config/i386/i386-features.cc (x86_cse_kind): Add\nX86_CSE_CONST_VECTOR.\n(redundant_pattern): Add dest_mode.\n(ix86_place_single_vector_set): Handle X86_CSE_CONST_VECTOR.\nGenerate SUBREG for constant integer source.\n(ix86_broadcast_inner): Add an INSN argument. Check REG_EQUAL\nnotes for CONST_VECTOR. Set load kind to X86_CSE_CONST_VECTOR\nfor native and converted CONST_VECTORs. Return CONST_VECTOR\nif it can be converted to constant integer load.\n(pass_x86_cse::candidate_vector_p): Add an INSN argument and\npass the insn to ix86_broadcast_inner.\n(pass_x86_cse::x86_cse): Add a basic block bitmap for calls.\nPass the insn to candidate_vector_p. Handle X86_CSE_CONST_VECTOR.\nSet dest_mode. Keep redundant constant integer load when\ncrossing a function call. Convert CONST_VECTOR load no larger\nthan integer register to constant integer load even if there is\nno redundant CONST_VECTOR load.\n\ngcc/testsuite/\n\nPR target/125100\n* gcc.target/i386/pr125100-1.c: New test.\n* gcc.target/i386/pr125100-2.c: Likewise.\n* gcc.target/i386/pr125100-3.c: Likewise.", "diff": "From 5ddfc773191aee18d1eca7bca6d352e291034ee7 Mon Sep 17 00:00:00 2001\nFrom: \"H.J. Lu\" <hjl.tools@gmail.com>\nDate: Thu, 30 Apr 2026 09:21:27 +0800\nSubject: [PATCH] x86_cse: Add X86_CSE_CONST_VECTOR\n\nAdd X86_CSE_CONST_VECTOR for native CONST_VECTOR:\n\n(insn 25 23 234 4 (set (reg:V16QI 135)\n (const_vector:V16QI [\n (const_int -1 [0xffffffffffffffff]) repeated x16\n ])) \"bar-2.c\":10:16 discrim 67584 2453 {movv16qi_internal}\n (nil))\n\nand constant integer load:\n\n(insn 280 8 279 2 (set (subreg:HI (reg:V2QI 172) 0)\n (const_int -1 [0xffffffffffffffff])) -1\n (nil))\n...\n(insn 110 39 194 9 (set (reg:V2QI 147)\n (reg:V2QI 172)) 2089 {*movv2qi_internal}\n (expr_list:REG_EQUAL (const_vector:V2QI [\n (const_int -1 [0xffffffffffffffff]) repeated x2\n ])\n (nil)))\n\nconverted from\n\n(insn 111 87 121 18 (set (reg:V2QI 147)\n (mem/u/c:V2QI (symbol_ref/u:DI (\"*.LC0\") [flags 0x2]) [0 S2 A16])) 2089 {*movv2qi_internal}\n (expr_list:REG_EQUAL (const_vector:V2QI [\n (const_int -1 [0xffffffffffffffff]) repeated x2])\n (nil)))\n\nKeep redundant constant integer load when crossing a function call since\nit is faster than save and restore an integer register.\n\nConvert CONST_VECTOR load no larger than integer register to constant\ninteger load even if there is no redundant CONST_VECTOR load.\n\nTested on Linux/x86-64 and Linux/i686.\n\ngcc/\n\n\tPR target/125100\n\t* config/i386/i386-features.cc (x86_cse_kind): Add\n\tX86_CSE_CONST_VECTOR.\n\t(redundant_pattern): Add dest_mode.\n\t(ix86_place_single_vector_set): Handle X86_CSE_CONST_VECTOR.\n\tGenerate SUBREG for constant integer source.\n\t(ix86_broadcast_inner): Add an INSN argument. Check REG_EQUAL\n\tnotes for CONST_VECTOR. Set load kind to X86_CSE_CONST_VECTOR\n\tfor native and converted CONST_VECTORs. Return CONST_VECTOR\n\tif it can be converted to constant integer load.\n\t(pass_x86_cse::candidate_vector_p): Add an INSN argument and\n\tpass the insn to ix86_broadcast_inner.\n\t(pass_x86_cse::x86_cse): Add a basic block bitmap for calls.\n\tPass the insn to candidate_vector_p. Handle X86_CSE_CONST_VECTOR.\n\tSet dest_mode. Keep redundant constant integer load when\n\tcrossing a function call. Convert CONST_VECTOR load no larger\n\tthan integer register to constant integer load even if there is\n\tno redundant CONST_VECTOR load.\n\ngcc/testsuite/\n\n\tPR target/125100\n\t* gcc.target/i386/pr125100-1.c: New test.\n\t* gcc.target/i386/pr125100-2.c: Likewise.\n\t* gcc.target/i386/pr125100-3.c: Likewise.\n\nSigned-off-by: H.J. Lu <hjl.tools@gmail.com>\n---\n gcc/config/i386/i386-features.cc | 167 ++++++++++++++++-----\n gcc/testsuite/gcc.target/i386/pr125100-1.c | 20 +++\n gcc/testsuite/gcc.target/i386/pr125100-2.c | 18 +++\n gcc/testsuite/gcc.target/i386/pr125100-3.c | 18 +++\n 4 files changed, 189 insertions(+), 34 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/i386/pr125100-1.c\n create mode 100644 gcc/testsuite/gcc.target/i386/pr125100-2.c\n create mode 100644 gcc/testsuite/gcc.target/i386/pr125100-3.c\n\ndiff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc\nindex 123c86a0fac..3cc3baa5df0 100644\n--- a/gcc/config/i386/i386-features.cc\n+++ b/gcc/config/i386/i386-features.cc\n@@ -3223,6 +3223,7 @@ enum x86_cse_kind\n {\n X86_CSE_CONST0_VECTOR,\n X86_CSE_CONSTM1_VECTOR,\n+ X86_CSE_CONST_VECTOR,\n X86_CSE_VEC_DUP,\n X86_CSE_TLS_GD,\n X86_CSE_TLS_LD_BASE,\n@@ -3241,6 +3242,9 @@ struct redundant_pattern\n rtx tlsdesc_val;\n /* The inner scalar mode. */\n machine_mode mode;\n+ /* The destination mode which can be changed to the integer mode of\n+ the same time. */\n+ machine_mode dest_mode;\n /* The instruction which sets the inner scalar. Nullptr if the inner\n scalar is applied to the whole function, instead of within the same\n block. */\n@@ -3272,9 +3276,11 @@ ix86_place_single_vector_set (rtx dest, rtx src, bitmap bbs,\n \t\t\t redundant_pattern *load = nullptr)\n {\n basic_block bb = nearest_common_dominator_for_set (CDI_DOMINATORS, bbs);\n- /* For X86_CSE_VEC_DUP, don't place the vector set outside of the loop\n- to avoid extra spills. */\n- if (!load || load->kind != X86_CSE_VEC_DUP)\n+ /* For X86_CSE_VEC_DUP and X86_CSE_CONST_VECTOR, don't place the vector\n+ set outside of the loop to avoid extra spills. */\n+ if (!load\n+ || (load->kind != X86_CSE_VEC_DUP\n+\t && load->kind != X86_CSE_CONST_VECTOR))\n {\n while (bb->loop_father->latch\n \t != EXIT_BLOCK_PTR_FOR_FN (cfun))\n@@ -3282,6 +3288,8 @@ ix86_place_single_vector_set (rtx dest, rtx src, bitmap bbs,\n \t\t\t\t bb->loop_father->header);\n }\n \n+ if (CONST_INT_P (src))\n+ dest = gen_rtx_SUBREG (load->dest_mode, dest, 0);\n rtx set = gen_rtx_SET (dest, src);\n \n rtx_insn *insn = BB_HEAD (bb);\n@@ -3322,10 +3330,7 @@ ix86_place_single_vector_set (rtx dest, rtx src, bitmap bbs,\n \t}\n }\n \n- /* NB: CONST_VECTOR load is generated and handled in x86_cse. */\n- if (load\n- && !CONST_VECTOR_P (src)\n- && load->kind == X86_CSE_VEC_DUP)\n+ if (load && load->kind == X86_CSE_VEC_DUP)\n {\n /* Get the source from LOAD as (reg:SI 99) in\n \n@@ -3759,25 +3764,68 @@ ix86_broadcast_inner (rtx op, machine_mode mode,\n \t return nullptr;\n \t}\n }\n- else if (CONST_VECTOR_P (op))\n+ else\n {\n- rtx first = XVECEXP (op, 0, 0);\n- for (int i = 1; i < nunits; ++i)\n+ rtx equal;\n+ bool int_load_p = false;\n+ if (CONST_VECTOR_P (op))\n \t{\n-\t rtx tmp = XVECEXP (op, 0, i);\n-\t /* Vector duplicate value. */\n-\t if (!rtx_equal_p (tmp, first))\n-\t return nullptr;\n+\t /* CONST_VECTOR is supported natively. */\n+\t *kind_p = X86_CSE_CONST_VECTOR;\n+\t int_load_p = GET_MODE_SIZE (mode) <= UNITS_PER_WORD;\n+\t equal = op;\n \t}\n- /* Use the inner mode to handle\n-\t (const_vector:V2QI [(const_int 0 [0]) repeated x2])\n- */\n- *scalar_mode_p = GET_MODE_INNER (mode);\n- *insn_p = nullptr;\n- return first;\n+ else\n+\t{\n+\t /* Check CONST_VECTOR load which can be converted to constant\n+\t integer load. */\n+\t equal = find_reg_equal_equiv_note (*insn_p);\n+\t if (equal)\n+\t {\n+\t equal = XEXP (equal, 0);\n+\t if (CONST_VECTOR_P (equal)\n+\t\t && GET_MODE_SIZE (mode) <= UNITS_PER_WORD)\n+\t\t{\n+\t\t /* X86_CSE_CONST_VECTOR is supported by converting it\n+\t\t to constant integer load. */\n+\t\t *kind_p = X86_CSE_CONST_VECTOR;\n+\t\t int_load_p = true;\n+\t\t op = equal;\n+\t\t}\n+\t else\n+\t\tequal = nullptr;\n+\t }\n+\t}\n+\n+ if (equal)\n+\t{\n+\t if (int_load_p)\n+\t {\n+\t /* This CONST_VECTOR load can be converted to constant\n+\t\t integer load. */\n+\t *scalar_mode_p = mode;\n+\t *insn_p = nullptr;\n+\t return op;\n+\t }\n+\n+\t rtx first = XVECEXP (op, 0, 0);\n+\t for (int i = 1; i < nunits; ++i)\n+\t {\n+\t rtx tmp = XVECEXP (op, 0, i);\n+\t /* Vector duplicate value. */\n+\t if (!rtx_equal_p (tmp, first))\n+\t\treturn nullptr;\n+\t }\n+\t /* Use the inner mode to handle\n+\t (const_vector:V2QI [(const_int 0 [0]) repeated x2])\n+\t */\n+\t *scalar_mode_p = GET_MODE_INNER (mode);\n+\t *insn_p = nullptr;\n+\t return first;\n+\t}\n+ else\n+\treturn nullptr;\n }\n- else\n- return nullptr;\n \n mode = GET_MODE (op);\n \n@@ -4357,7 +4405,7 @@ private:\n unsigned int x86_cse (void);\n bool candidate_gnu_tls_p (rtx_insn *, attr_tls64);\n bool candidate_gnu2_tls_p (rtx, attr_tls64);\n- bool candidate_vector_p (rtx);\n+ bool candidate_vector_p (rtx, rtx_insn *);\n rtx_insn *tls_set_insn_from_symbol (const_rtx, const_rtx);\n }; // class pass_x86_cse\n \n@@ -4539,7 +4587,7 @@ pass_x86_cse::candidate_gnu2_tls_p (rtx set, attr_tls64 tls64)\n INSN is a vector broadcast instruction. */\n \n bool\n-pass_x86_cse::candidate_vector_p (rtx set)\n+pass_x86_cse::candidate_vector_p (rtx set, rtx_insn *insn)\n {\n rtx src = SET_SRC (set);\n rtx dest = SET_DEST (set);\n@@ -4552,6 +4600,7 @@ pass_x86_cse::candidate_vector_p (rtx set)\n if (!REG_P (dest) && !SUBREG_P (dest))\n return false;\n \n+ def_insn = insn;\n val = ix86_broadcast_inner (src, mode, &scalar_mode, &kind,\n \t\t\t &def_insn);\n return val ? true : false;\n@@ -4585,6 +4634,7 @@ pass_x86_cse::x86_cse (void)\n unsigned int i;\n auto_bitmap updated_gnu_tls_insns;\n auto_bitmap updated_gnu2_tls_insns;\n+ auto_bitmap call_bbs;\n \n df_set_flags (DF_DEFER_INSN_RESCAN);\n \n@@ -4603,8 +4653,13 @@ pass_x86_cse::x86_cse (void)\n \t unsigned int threshold = 2;\n \n \t rtx set = single_set (insn);\n-\t if (!set && !CALL_P (insn))\n-\t continue;\n+\t if (!set)\n+\t {\n+\t if (CALL_P (insn))\n+\t\tbitmap_set_bit (call_bbs, BLOCK_FOR_INSN (insn)->index);\n+\t else\n+\t\tcontinue;\n+\t }\n \n \t tlsdesc_val = nullptr;\n \n@@ -4634,7 +4689,7 @@ pass_x86_cse::x86_cse (void)\n \t\tcontinue;\n \n \t /* Check for vector broadcast. */\n-\t if (candidate_vector_p (set))\n+\t if (candidate_vector_p (set, insn))\n \t\tbreak;\n \t continue;\n \t }\n@@ -4645,7 +4700,8 @@ pass_x86_cse::x86_cse (void)\n \t\t&& load->kind == kind\n \t\t&& load->mode == scalar_mode\n \t\t&& (load->bb == bb\n-\t\t || kind != X86_CSE_VEC_DUP\n+\t\t || (kind != X86_CSE_VEC_DUP\n+\t\t\t&& kind != X86_CSE_CONST_VECTOR)\n \t\t /* Non all 0s/1s vector load must be in the same\n \t\t basic block if it is in a recursive call. */\n \t\t || !recursive_call_p)\n@@ -4678,12 +4734,19 @@ pass_x86_cse::x86_cse (void)\n \t instruction basic block and the instruction kind. */\n \t load = new redundant_pattern;\n \n+\t /* Convert CONST_VECTOR load no larger than integer register\n+\t to constant integer load even if there is no redundant\n+\t CONST_VECTOR load. */\n+\t if (CONST_VECTOR_P (val))\n+\t threshold = 1;\n+\n \t load->val = copy_rtx (val);\n \t if (tlsdesc_val)\n \t load->tlsdesc_val = copy_rtx (tlsdesc_val);\n \t else\n \t load->tlsdesc_val = nullptr;\n \t load->mode = scalar_mode;\n+\t load->dest_mode = mode;\n \t load->size = GET_MODE_SIZE (mode);\n \t load->def_insn = def_insn;\n \t load->count = 1;\n@@ -4725,10 +4788,13 @@ pass_x86_cse::x86_cse (void)\n \t\t || load->size <= UNITS_PER_WORD))\n \t {\n \t\t/* Generate CONST_VECTOR load. */\n+\t case X86_CSE_CONST_VECTOR:\n \t\tmode = ix86_get_vector_cse_mode (load->size,\n \t\t\t\t\t\t load->mode);\n \n-\t\tif (load->val == CONST0_RTX (load->mode))\n+\t\tif (CONST_VECTOR_P (load->val))\n+\t\t broadcast_source = load->val;\n+\t\telse if (load->val == CONST0_RTX (load->mode))\n \t\t broadcast_source = CONST0_RTX (mode);\n \t\telse if (load->val == CONSTM1_RTX (load->mode))\n \t\t broadcast_source = CONSTM1_RTX (mode);\n@@ -4758,15 +4824,46 @@ pass_x86_cse::x86_cse (void)\n \t\t */\n \t\t machine_mode int_mode\n \t\t = int_mode_for_mode (mode).require ();\n+\t\t load->dest_mode = int_mode;\n \t\t broadcast_source = simplify_subreg (int_mode,\n \t\t\t\t\t\t\tbroadcast_source,\n \t\t\t\t\t\t\tmode, 0);\n \t\t gcc_assert (broadcast_source != nullptr);\n-\t\t replace_vector_const (mode, broadcast_source,\n-\t\t\t\t\t load->insns, int_mode);\n-\t\t /* Keep redundant constant integer load. */\n-\t\t load->broadcast_source = nullptr;\n-\t\t load->broadcast_reg = nullptr;\n+\n+\t\t bool keep_redundant_load = false;\n+\t\t if (!bitmap_empty_p (call_bbs))\n+\t\t {\n+\t\t\tbitmap_iterator bi;\n+\t\t\tunsigned int id;\n+\t\t\tEXECUTE_IF_SET_IN_BITMAP (load->bbs, 0, id, bi)\n+\t\t\t if (bitmap_bit_p (call_bbs, id))\n+\t\t\t {\n+\t\t\t /* NB: Redundant constant integer load is\n+\t\t\t\t faster than save and restore an integer\n+\t\t\t\t register when crossing a function call.\n+\t\t\t */\n+\t\t\t keep_redundant_load = true;\n+\t\t\t break;\n+\t\t\t }\n+\t\t }\n+\n+\t\t if (keep_redundant_load)\n+\t\t {\n+\t\t\t/* Keep redundant constant integer load. */\n+\t\t\treplace_vector_const (mode, broadcast_source,\n+\t\t\t\t\t load->insns, int_mode);\n+\t\t\tload->broadcast_source = nullptr;\n+\t\t\tload->broadcast_reg = nullptr;\n+\t\t }\n+\t\t else\n+\t\t {\n+\t\t\tbroadcast_reg = gen_reg_rtx (mode);\n+\t\t\treg = gen_reg_rtx (load->mode);\n+\t\t\treplace_vector_const (mode, broadcast_reg,\n+\t\t\t\t\t load->insns, load->mode);\n+\t\t\tload->broadcast_source = broadcast_source;\n+\t\t\tload->broadcast_reg = broadcast_reg;\n+\t\t }\n \t\t break;\n \t\t }\n \t }\n@@ -4797,6 +4894,7 @@ pass_x86_cse::x86_cse (void)\n \t\tcase X86_CSE_CONSTM1_VECTOR:\n \t\t broadcast_source = CONSTM1_RTX (mode);\n \t\t break;\n+\t\tcase X86_CSE_CONST_VECTOR:\n \t\tcase X86_CSE_VEC_DUP:\n \t\t if (!broadcast_source)\n \t\t {\n@@ -4888,6 +4986,7 @@ pass_x86_cse::x86_cse (void)\n \t\t\t\t\t updated_gnu_tls_insns,\n \t\t\t\t\t updated_gnu2_tls_insns);\n \t\t break;\n+\t\tcase X86_CSE_CONST_VECTOR:\n \t\tcase X86_CSE_VEC_DUP:\n \t\t /* Keep redundant constant integer load. */\n \t\t if (!load->broadcast_reg)\ndiff --git a/gcc/testsuite/gcc.target/i386/pr125100-1.c b/gcc/testsuite/gcc.target/i386/pr125100-1.c\nnew file mode 100644\nindex 00000000000..21765a5843e\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/pr125100-1.c\n@@ -0,0 +1,20 @@\n+/* { dg-do compile { target fpic } } */\n+/* { dg-options \"-mtune=generic -O2 -fPIC\" } */\n+/* { dg-additional-options \"-march=pentiumpro\" { target ia32 } } */\n+\n+struct desc {\n+ char c1;\n+ char c2;\n+};\n+void\n+foo (struct desc *list, int n, int l)\n+{\n+ int j;\n+ for (j = 0; j < l; j++)\n+ list[j].c1 = list[j].c2 = -1;\n+ for (;j < n; j++)\n+ list[j].c1 = list[j].c2 = -1;\n+}\n+\n+/* { dg-final { scan-assembler-times \"movl\\[ \\\\t\\]+\\\\\\$-1, %\\[a-z0-9\\]+\" 1 } } */\n+/* { dg-final { scan-assembler-not \"__x86.get_pc_thunk\" { target ia32 } } } */\ndiff --git a/gcc/testsuite/gcc.target/i386/pr125100-2.c b/gcc/testsuite/gcc.target/i386/pr125100-2.c\nnew file mode 100644\nindex 00000000000..d179c3f4050\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/pr125100-2.c\n@@ -0,0 +1,18 @@\n+/* { dg-do compile { target fpic } } */\n+/* { dg-options \"-mtune=generic -O2 -fPIC\" } */\n+/* { dg-additional-options \"-march=pentiumpro\" { target ia32 } } */\n+\n+struct desc {\n+ char c1;\n+ char c2;\n+};\n+void\n+foo (struct desc *list, int n, int l)\n+{\n+ int j;\n+ for (j = 0; j < l; j++)\n+ list[j].c1 = list[j].c2 = -1;\n+}\n+\n+/* { dg-final { scan-assembler-times \"movl\\[ \\\\t\\]+\\\\\\$-1, %\\[a-z0-9\\]+\" 1 } } */\n+/* { dg-final { scan-assembler-not \"__x86.get_pc_thunk\" { target ia32 } } } */\ndiff --git a/gcc/testsuite/gcc.target/i386/pr125100-3.c b/gcc/testsuite/gcc.target/i386/pr125100-3.c\nnew file mode 100644\nindex 00000000000..2015ee819b3\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/pr125100-3.c\n@@ -0,0 +1,18 @@\n+/* { dg-do compile { target fpic } } */\n+/* { dg-options \"-mtune=generic -O2 -fPIC\" } */\n+/* { dg-additional-options \"-march=pentiumpro\" { target ia32 } } */\n+\n+struct desc {\n+ char c1;\n+ char c2;\n+};\n+void\n+foo (struct desc *list, int n, int l)\n+{\n+ int j;\n+ for (j = 0; j < l; j++)\n+ list[j].c1 = list[j].c2 = 1;\n+}\n+\n+/* { dg-final { scan-assembler-times \"movl\\[ \\\\t\\]+\\\\\\$257, %\\[a-z0-9\\]+\" 1 } } */\n+/* { dg-final { scan-assembler-not \"__x86.get_pc_thunk\" { target ia32 } } } */\n-- \n2.54.0\n\n", "prefixes": [] }