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GET /api/patches/2230865/?format=api
{ "id": 2230865, "url": "http://patchwork.ozlabs.org/api/patches/2230865/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430-sm6350-lpi-tlmm-v2-2-81d068025b97@fairphone.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430-sm6350-lpi-tlmm-v2-2-81d068025b97@fairphone.com>", "list_archive_url": null, "date": "2026-04-30T07:10:42", "name": "[v2,2/5] pinctrl: qcom: lpass-lpi: Add ability to use SPARE_1 for slew control", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7855d0eef6a5d2fe5cdd6bb77e6c911265e080b3", "submitter": { "id": 83060, "url": "http://patchwork.ozlabs.org/api/people/83060/?format=api", "name": "Luca Weiss", "email": "luca.weiss@fairphone.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430-sm6350-lpi-tlmm-v2-2-81d068025b97@fairphone.com/mbox/", "series": [ { "id": 502221, "url": "http://patchwork.ozlabs.org/api/series/502221/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502221", "date": "2026-04-30T07:10:40", "name": "Add LPASS LPI pin controller support for SM6350", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502221/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230865/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230865/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-35828-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=fairphone.com header.i=@fairphone.com\n header.a=rsa-sha256 header.s=fair header.b=AwxS28zD;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260430-sm6350-lpi-tlmm-v2-2-81d068025b97@fairphone.com>", "References": "<20260430-sm6350-lpi-tlmm-v2-0-81d068025b97@fairphone.com>", "In-Reply-To": "<20260430-sm6350-lpi-tlmm-v2-0-81d068025b97@fairphone.com>", "To": "Bjorn Andersson <andersson@kernel.org>,\n Linus Walleij <linusw@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Konrad Dybcio <konradybcio@kernel.org>,\n Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>", "Cc": "~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Luca Weiss <luca.weiss@fairphone.com>,\n Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777533047; l=2676;\n i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id;\n bh=8AL+NQRRa6kPH6NzCfcOC2Llr5owhpqb7+IMEyXnI98=;\n b=+MrwYSNWoWi0pZLMiyT+PYWHDz4bMO5KSMD0GqsL/a7Q4KPUi3ktOJmileienxzbK2uLaAs5e\n WIBgh2XEgoJCWbC3JqImBCKNIg8DSDE0HZ/15ncEtwbvPRXvJCQv9LR", "X-Developer-Key": "i=luca.weiss@fairphone.com; a=ed25519;\n pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8=" }, "content": "On some platforms like SM6350 (Bitra), some pins have their slew\ncontrolled with the SPARE_1 register. Add support for that.\n\nReviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>\nSigned-off-by: Luca Weiss <luca.weiss@fairphone.com>\n---\n drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 ++\n drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 20 ++++++++++++++++++++\n 2 files changed, 22 insertions(+)", "diff": "diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c\nindex 76aed3296279..15ced5027579 100644\n--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c\n+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c\n@@ -220,6 +220,8 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl,\n \n \tif (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)\n \t\treg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG;\n+\telse if (g->slew_base_spare_1)\n+\t\treg = pctrl->slew_base + LPI_SPARE_1_REG;\n \telse\n \t\treg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG;\n \ndiff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h\nindex f48368492861..6ba0c4eba984 100644\n--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h\n+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h\n@@ -16,6 +16,7 @@ struct platform_device;\n struct pinctrl_pin_desc;\n \n #define LPI_SLEW_RATE_CTL_REG\t0xa000\n+#define LPI_SPARE_1_REG\t\t0xc000\n #define LPI_TLMM_REG_OFFSET\t\t0x1000\n #define LPI_SLEW_RATE_MAX\t\t0x03\n #define LPI_SLEW_BITS_SIZE\t\t0x02\n@@ -47,6 +48,7 @@ struct pinctrl_pin_desc;\n \t{\t\t\t\t\t\t\\\n \t\t.pin = id,\t\t\t\t\\\n \t\t.slew_offset = soff,\t\t\t\\\n+\t\t.slew_base_spare_1 = false,\t\t\\\n \t\t.funcs = (int[]){\t\t\t\\\n \t\t\tLPI_MUX_gpio,\t\t\t\\\n \t\t\tLPI_MUX_##f1,\t\t\t\\\n@@ -62,6 +64,7 @@ struct pinctrl_pin_desc;\n \t{\t\t\t\t\t\t\t\\\n \t\t.pin = id,\t\t\t\t\t\\\n \t\t.slew_offset = soff,\t\t\t\t\\\n+\t\t.slew_base_spare_1 = false,\t\t\t\\\n \t\t.funcs = (int[]){\t\t\t\t\\\n \t\t\tLPI_MUX_gpio,\t\t\t\t\\\n \t\t\tLPI_MUX_##f1,\t\t\t\t\\\n@@ -73,6 +76,22 @@ struct pinctrl_pin_desc;\n \t\t.pin_offset = poff,\t\t\t\t\\\n \t}\n \n+#define LPI_PINGROUP_SLEW_SPARE_1(id, soff, f1, f2, f3, f4)\t\\\n+\t{\t\t\t\t\t\t\t\\\n+\t\t.pin = id,\t\t\t\t\t\\\n+\t\t.slew_offset = soff,\t\t\t\t\\\n+\t\t.slew_base_spare_1 = true,\t\t\t\\\n+\t\t.funcs = (int[]){\t\t\t\t\\\n+\t\t\tLPI_MUX_gpio,\t\t\t\t\\\n+\t\t\tLPI_MUX_##f1,\t\t\t\t\\\n+\t\t\tLPI_MUX_##f2,\t\t\t\t\\\n+\t\t\tLPI_MUX_##f3,\t\t\t\t\\\n+\t\t\tLPI_MUX_##f4,\t\t\t\t\\\n+\t\t},\t\t\t\t\t\t\\\n+\t\t.nfuncs = 5,\t\t\t\t\t\\\n+\t\t.pin_offset = 0,\t\t\t\t\\\n+\t}\n+\n /*\n * Slew rate control is done in the same register as rest of the\n * pin configuration.\n@@ -87,6 +106,7 @@ struct lpi_pingroup {\n \tunsigned int *funcs;\n \tunsigned int nfuncs;\n \tunsigned int pin_offset;\n+\tbool slew_base_spare_1;\n };\n \n struct lpi_function {\n", "prefixes": [ "v2", "2/5" ] }