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GET /api/patches/2230861/?format=api
{ "id": 2230861, "url": "http://patchwork.ozlabs.org/api/patches/2230861/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260430070954.1005564-3-amhetre@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430070954.1005564-3-amhetre@nvidia.com>", "list_archive_url": null, "date": "2026-04-30T07:09:54", "name": "[V2,2/2] memory: tegra: Restore MC interrupt masks on resume", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0397aaa9faed3f78315bbd2fdae4c62e06d1660f", "submitter": { "id": 75198, "url": "http://patchwork.ozlabs.org/api/people/75198/?format=api", "name": "Ashish Mhetre", "email": "amhetre@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260430070954.1005564-3-amhetre@nvidia.com/mbox/", "series": [ { "id": 502220, "url": "http://patchwork.ozlabs.org/api/series/502220/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502220", "date": "2026-04-30T07:09:52", "name": "memory: tegra: Restore MC state on system resume", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502220/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230861/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230861/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-14071-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=YuWpP1/v;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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pr=C", "From": "Ashish Mhetre <amhetre@nvidia.com>", "To": "<krzk@kernel.org>, <thierry.reding@kernel.org>, <jonathanh@nvidia.com>", "CC": "<ketanp@nvidia.com>, <linux-kernel@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, Ashish Mhetre <amhetre@nvidia.com>", "Subject": "[PATCH V2 2/2] memory: tegra: Restore MC interrupt masks on resume", "Date": "Thu, 30 Apr 2026 07:09:54 +0000", "Message-ID": "<20260430070954.1005564-3-amhetre@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260430070954.1005564-1-amhetre@nvidia.com>", "References": "<20260430070954.1005564-1-amhetre@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PEPF00003443:EE_|IA1PR12MB8334:EE_", "X-MS-Office365-Filtering-Correlation-Id": "aba4362c-a621-451c-bf3c-08dea6879106", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|36860700016|376014|82310400026|1800799024|22082099003|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n\tuTr9AdD7EY4+sy1aNWzfBQr4hb6D9JHRXQ2/ze6JOFe9b9xAhcInkMIhzRcmjHdV+MuF5IHOOsbIYuJmbUERprRp5SUXmDW+NzKG6OyrB8aQKqukrDV9infG89eclHCK89VJWjlYxh8etor8PBJY/QDRQoTpDcCVvsSStva3rwtqhlxL6tPZKI7IoM4WmncrKgbIP5JlAq53CD024UdceydxRbGg25SKw6EfSzX8zENCVMF0d6X5NA0XIW6dNyjthprLUu5u4DAvEE/lBZGdF20d5bpNE9N9ab0z/KS5oasPbTABpF+G2qNqAVjYy4UKsMK2NZtYaoWPpOnuWleC3NPbxiNQUdX9ZMd1FCljdzSJPREDObLx8dT7n1bi7wclLVx6MZ7EfS15/tthw11Rfsj7zuZYOASJxuXpxuTObNbtdyKrF78X8Zj+CPpL8702lK6nxjGKSYsOxRofdmx0wKElMomAC3FAJ43wPbJLs8hkGz1U9Xo9z+shvtAuFj9TvUJHcwraPjh8AQzwOKw2kjbvcTjbl3yEyEjDSCLM56/OeXQn4BkmBaGeTbRzFBfXgvr+P3UfF3S9yHAJpym0nFlFv846SL7eoW29WWgfXYjIdW/YAnGMC70auiZSAyYX2+npplBlqhWhSRSXg7O0PpRPDffpK3RP6rtGJxUZ5MEijpVCGWfSxzesD5+dKsYjlQwB9ENOZxxCKi/SRJbl4GgMrDqGQY5WccoUaQNllcrHZhkOk0SQC6T+HK5pBXNFY2rZSJsfJfsYXbwtkqMHiw==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(82310400026)(1800799024)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tBvzt7caBThGu4ZdDVO3LY/RHqJj04hM/WjwGXg9j0nXyLe3Mw08y2gKH+dMQUWzBP0fpUBabj/GFhtklk+7hgOAE6Q9BmqQpxg7loyfA4Ia00oS1Xp2eSXwAnxJJlTv9tDeS5rIAeKPCYi0iJmPIQHp0piblkdURyMhiQvYmMtmDjdG/33NMPMV+5DNANnrLHVFECOxiJGYm1SB+NfARrDheYyFaJZPXFafridTQWaRxMtzvO1+IgUzdg+TsvjGztwfh7chaZPf5EOJBQ1mX4MbrPgg/fk2N4+6/okbNOdc49am7dc54Qsak9GKnbJruSudZWfkjRIYJEp5nN96nie5czdMEI3NjLUCEe4NXgSfs5Xjl79hj6/FpRVP9JKu3MyxbgGCKsh9YjQRzusIWfrlND3Yw2HzVT3OT5b5TygkIK4o1tb0tfanN6+V4Lz3C", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Apr 2026 07:10:31.5577\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n aba4362c-a621-451c-bf3c-08dea6879106", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tDS2PEPF00003443.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB8334" }, "content": "The MC interrupt mask registers lose their state across SC7. Without\nre-applying them on resume, MC interrupts that were enabled at probe\nremain masked after wake, so any post-resume MC error goes unreported.\n\nFactor the existing intmask programming out of tegra_mc_probe() into\ntegra_mc_setup_intmask() and reuse it from the system resume callback\nso the mask state is restored on wake.\n\nSigned-off-by: Ashish Mhetre <amhetre@nvidia.com>\n---\n drivers/memory/tegra/mc.c | 31 ++++++++++++++++++++++---------\n 1 file changed, 22 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c\nindex 343ac0018eba..ea7b489d666b 100644\n--- a/drivers/memory/tegra/mc.c\n+++ b/drivers/memory/tegra/mc.c\n@@ -911,6 +911,19 @@ static void tegra_mc_num_channel_enabled(struct tegra_mc *mc)\n \t}\n }\n \n+static void tegra_mc_setup_intmask(struct tegra_mc *mc)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < mc->soc->num_intmasks; i++) {\n+\t\tif (mc->soc->num_channels)\n+\t\t\tmc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask,\n+\t\t\t\t mc->soc->intmasks[i].reg);\n+\t\telse\n+\t\t\tmc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg);\n+\t}\n+}\n+\n static int tegra_mc_probe(struct platform_device *pdev)\n {\n \tstruct tegra_mc *mc;\n@@ -971,13 +984,7 @@ static int tegra_mc_probe(struct platform_device *pdev)\n \t\t\t}\n \t\t}\n \n-\t\tfor (i = 0; i < mc->soc->num_intmasks; i++) {\n-\t\t\tif (mc->soc->num_channels)\n-\t\t\t\tmc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask,\n-\t\t\t\t\t mc->soc->intmasks[i].reg);\n-\t\t\telse\n-\t\t\t\tmc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg);\n-\t\t}\n+\t\ttegra_mc_setup_intmask(mc);\n \t}\n \n \tif (mc->soc->reset_ops) {\n@@ -1014,9 +1021,15 @@ static void tegra_mc_sync_state(struct device *dev)\n static int tegra_mc_resume(struct device *dev)\n {\n \tstruct tegra_mc *mc = dev_get_drvdata(dev);\n+\tint err;\n+\n+\tif (mc->soc->ops && mc->soc->ops->resume) {\n+\t\terr = mc->soc->ops->resume(mc);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n \n-\tif (mc->soc->ops && mc->soc->ops->resume)\n-\t\treturn mc->soc->ops->resume(mc);\n+\ttegra_mc_setup_intmask(mc);\n \n \treturn 0;\n }\n", "prefixes": [ "V2", "2/2" ] }