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GET /api/patches/2230857/?format=api
{ "id": 2230857, "url": "http://patchwork.ozlabs.org/api/patches/2230857/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/afL6kki_X6CywfNG@cowardly-lion.the-meissners.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<afL6kki_X6CywfNG@cowardly-lion.the-meissners.org>", "list_archive_url": null, "date": "2026-04-30T06:45:38", "name": "GCC 17, PowerPC Dense Math V7 (patch 6/7) -- Use dense math name for MMA instructions if -mdense-math", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "18a4c8fcb993a1d49d2753967aaa9541ebeeb03f", "submitter": { "id": 73991, "url": "http://patchwork.ozlabs.org/api/people/73991/?format=api", "name": "Michael Meissner", "email": "meissner@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/afL6kki_X6CywfNG@cowardly-lion.the-meissners.org/mbox/", "series": [ { "id": 502218, "url": "http://patchwork.ozlabs.org/api/series/502218/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502218", "date": "2026-04-30T06:45:38", "name": "GCC 17, PowerPC Dense Math V7 (patch 6/7) -- Use dense math name for MMA instructions if -mdense-math", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502218/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230857/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230857/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=bRBYLcmO;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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a=rsa-sha256; d=sourceware.org; s=key; t=1777531545; cv=none;\n b=nqYNyoUWqqJMl/s+wRPiL85z7mjg5+IqilJa561LwYBK31DTFnxoM5dhAcqR5wznK0WD7f7+0EM6H3AGU/OsnGrKZp1njgdLqOsAUYT5t2bjeKY793hobwVFtQPgs0djgnp30InuxDLtkrQLMcskTFIfTNZMPQwHp1uwWxkcsQg=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1777531545; c=relaxed/simple;\n bh=m4Fc8OYjUXiUmELQ6NNgt68RDl6FHA3PhY8XyiHcyfo=;\n h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version;\n b=krxf4kxTQpasWofU0fCGStbFKtTfApyxP4zeEVulfshiLeZL8nQ48lSsfYb0uAJ9l6Gg/Oc/iZo6Tml7LdFbSeJT4rBFuJVN0BQJJzHEBrGwQ0ahWKcXFwN+Gp+f/jYkFEMoECsBRAFtLXkVjqsxbhpbUgtMY32BhqDzQRoUMb8=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=\n content-type:date:from:in-reply-to:message-id:mime-version\n :references:subject:to; s=pp1; bh=oZ2B4U/5ljKgYLIbp66l5zF6R68GSe\n 496FDlF0ip7r0=; b=bRBYLcmONmNXolYPggc1QO2DeZBrVcyjm546lrFH7uykrK\n pt9TL904fQiAObCMrOopg/B7wu7T1jumgjGIwkCS4FST5RtfKj6dbOuUjbkTcbwW\n XELY4o2AUmxxqn0EhQSuqLwOWv3zWunQ/sRTz5Ka+Me1RvygdMOM+2LuyCw32fh+\n yfu6tl0/JMD+oQikULXA1Kam9S+hDrnEaGIpvhLarcDmtOs5g4klUk1wCW3JuEgD\n VLg1xoXz9P7LwcXKrkUWDiyn4ZdBbIHx0x7zOc9my0JPUsqbKMj9Tn/NvVSnArGi\n mB3fAGLsvKgBXPXhf/qVkgWSnVIJVeSOhFZRQlzw==", "Date": "Thu, 30 Apr 2026 02:45:38 -0400", "From": "Michael Meissner <meissner@linux.ibm.com>", "To": "Michael Meissner <meissner@linux.ibm.com>, gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "Subject": "GCC 17, PowerPC Dense Math V7 (patch 6/7) -- Use dense math name for\n MMA instructions if -mdense-math", "Message-ID": "<afL6kki_X6CywfNG@cowardly-lion.the-meissners.org>", "Mail-Followup-To": "Michael Meissner <meissner@linux.ibm.com>,\n gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "References": "<afL4oa26tUJlc9zg@cowardly-lion.the-meissners.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=us-ascii", "Content-Disposition": "inline", "In-Reply-To": "<afL4oa26tUJlc9zg@cowardly-lion.the-meissners.org>", "X-TM-AS-GCONF": "00", "X-Authority-Analysis": "v=2.4 cv=CIIamxrD c=1 sm=1 tr=0 ts=69f2fa98 cx=c_pps\n a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17\n a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8\n a=f_Ug1Vp9BB2Rt6NwJwsA:9 a=3ZKOabzyN94A:10 a=CjuIK1q_8ugA:10", "X-Proofpoint-ORIG-GUID": "l6AGWgHPNKiMzqn9LUeC3ZXkNVzyZC44", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDMwMDA2MCBTYWx0ZWRfXzlOnjfnnaBHc\n g6nxFNlGyRJr05fNZ6kp/aEjD5Twa7rhebBfv+io7EWSMT+haqQIC1b+YcLAn4VLIRScoekpDUv\n Z6SYpsgOC6zdEPPNlZfgRZUHNHlpSlnQ0eTdORMYcnQf0SAs2fpHrYrYKKd2X5nczIwsc5rMaRs\n E+DgX3Jl7z3D09h/NQuHEZxMM8nuQrucimyW2RPA2/1Lhwc+UM9RliqBKnKrEBmLbhoGQU4jWDY\n ybcf4IoY1ilai571w90iukcOhrrNgZ2BtJDbbUDcQ9XMbg6YC3aI3ZcDIMDChfyAJgI7sTR+e76\n cMWqEcYAUcI38o52XaT6CkrUnoHdU/q4fHktsfhwGLE823fc+NabBm2xemuhezk81c8w9WzQ69T\n dUF5aoAdG0qXk+rnATRzft58AczRDJoWyVBR1T91RKzbCSuxQFRZTljw1F1kw5FztuCHD1qotA4\n 7AZnUsocV5L2Ky7WWvA==", "X-Proofpoint-GUID": "l6AGWgHPNKiMzqn9LUeC3ZXkNVzyZC44", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-30_02,2026-04-28_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 phishscore=0 malwarescore=0 suspectscore=0 adultscore=0\n impostorscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0\n priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604300060", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This is part six of the dense math register patches for the PowerPC.\n\nThis is an optional patch that on dense math systems changes the XV* MMA\ninstructions to DMXV*. The assembler will generate the same object code for\neither instruction. This is tell the user looking at assembly code that we are\ncompiling MMA code to use dense math registers.\n\nI have built bootstrap little endian compilers on power10 systems, and\nbig endian compiler on power9 systems. There were no regression in the\ntests. Can I add the patches to the GCC trunk after the -mcpu=future\npatch is applied and GCC 17 has opened up?\n\n2026-04-29 Michael Meissner <meissner@linux.ibm.com>\n\ngcc/\n\n\t* config/rs6000/mma.md (vvi4i4i8): Eliminate using the 'pm' prefix here,\n\tso we can emit pmdm* on dense math systems.\n\t(avvi4i4i8): Likewise.\n\t(vvi4i4i2): Likewise.\n\t(avvi4i4i2): Likewise.\n\t(vvi4i4): Likewise.\n\t(avvi4i4): Likewise.\n\t(pvi4i2): Likewise.\n\t(apvi4i2): Likewise.\n\t(vvi4i4i4): Likewise.\n\t(mma_<vv>): If -mdesne-math, emit 'dmxv*' form of the instruction\n\tinstead of 'xv*'.\n\t(mma_<avv>): Likewise.\n\t(mma_<pv>): Likewise.\n\t(mma_<apv>): Likewise.\n\t(mma_pm<vvi4i4i8>): If -mdense-math, emit 'pmdm*' instead of 'pm*'.\n\t(mma_pm<avvi4i4i8>): Likewise.\n\t(mma_pm<vvi4i4i2>): Likewise.\n\t(mma_pm<avvi4i4i2>): Likewise.\n\t(mma_pm<vvi4i4>): Likewise.\n\t(mma_pm<avvi4i4>): Likewise.\n\t(mma_pm<pvi4i2>): Likewise.\n\t(mma_pm<apvi4i2>): Likewise.\n\t(mma_pm<vvi4i4i4>): Likewise.\n\t(mma_pm<avvi4i4i4>): Likewise.\n\t* config/rs6000/rs6000.cc (print_operand): For %!, print 'dm' if\n\t-mdense-math.\n\t* config/rs6000/rs6000.h (PRINT_OPERAND_PUNCT_VALID_P): Allow %!.\n---\n gcc/config/rs6000/mma.md | 108 +++++++++---------\n gcc/config/rs6000/rs6000.cc | 6 +\n gcc/config/rs6000/rs6000.h | 2 +-\n 4 files changed, 125 insertions(+), 54 deletions(-)", "diff": "diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md\nindex 95cee85925b..16a7bb26e0e 100644\n--- a/gcc/config/rs6000/mma.md\n+++ b/gcc/config/rs6000/mma.md\n@@ -230,44 +230,46 @@ (define_int_attr apv\t\t[(UNSPEC_MMA_XVF64GERPP\t\t\"xvf64gerpp\")\n \t\t\t\t (UNSPEC_MMA_XVF64GERNP\t\t\"xvf64gernp\")\n \t\t\t\t (UNSPEC_MMA_XVF64GERNN\t\t\"xvf64gernn\")])\n \n-(define_int_attr vvi4i4i8\t[(UNSPEC_MMA_PMXVI4GER8\t\t\"pmxvi4ger8\")])\n+;; The follwoing instructions do not have the 'pm' prefix, so that on dense\n+;; math systems, we can change the pm to pmdm.\n+(define_int_attr vvi4i4i8\t[(UNSPEC_MMA_PMXVI4GER8\t\t\"xvi4ger8\")])\n \n-(define_int_attr avvi4i4i8\t[(UNSPEC_MMA_PMXVI4GER8PP\t\"pmxvi4ger8pp\")])\n+(define_int_attr avvi4i4i8\t[(UNSPEC_MMA_PMXVI4GER8PP\t\"xvi4ger8pp\")])\n \n-(define_int_attr vvi4i4i2\t[(UNSPEC_MMA_PMXVI16GER2\t\"pmxvi16ger2\")\n-\t\t\t\t (UNSPEC_MMA_PMXVI16GER2S\t\"pmxvi16ger2s\")\n-\t\t\t\t (UNSPEC_MMA_PMXVF16GER2\t\"pmxvf16ger2\")\n-\t\t\t\t (UNSPEC_MMA_PMXVBF16GER2\t\"pmxvbf16ger2\")])\n+(define_int_attr vvi4i4i2\t[(UNSPEC_MMA_PMXVI16GER2\t\"xvi16ger2\")\n+\t\t\t\t (UNSPEC_MMA_PMXVI16GER2S\t\"xvi16ger2s\")\n+\t\t\t\t (UNSPEC_MMA_PMXVF16GER2\t\"xvf16ger2\")\n+\t\t\t\t (UNSPEC_MMA_PMXVBF16GER2\t\"xvbf16ger2\")])\n \n-(define_int_attr avvi4i4i2\t[(UNSPEC_MMA_PMXVI16GER2PP\t\"pmxvi16ger2pp\")\n-\t\t\t\t (UNSPEC_MMA_PMXVI16GER2SPP\t\"pmxvi16ger2spp\")\n-\t\t\t\t (UNSPEC_MMA_PMXVF16GER2PP\t\"pmxvf16ger2pp\")\n-\t\t\t\t (UNSPEC_MMA_PMXVF16GER2PN\t\"pmxvf16ger2pn\")\n-\t\t\t\t (UNSPEC_MMA_PMXVF16GER2NP\t\"pmxvf16ger2np\")\n-\t\t\t\t (UNSPEC_MMA_PMXVF16GER2NN\t\"pmxvf16ger2nn\")\n-\t\t\t\t (UNSPEC_MMA_PMXVBF16GER2PP\t\"pmxvbf16ger2pp\")\n-\t\t\t\t (UNSPEC_MMA_PMXVBF16GER2PN\t\"pmxvbf16ger2pn\")\n-\t\t\t\t (UNSPEC_MMA_PMXVBF16GER2NP\t\"pmxvbf16ger2np\")\n-\t\t\t\t (UNSPEC_MMA_PMXVBF16GER2NN\t\"pmxvbf16ger2nn\")])\n+(define_int_attr avvi4i4i2\t[(UNSPEC_MMA_PMXVI16GER2PP\t\"xvi16ger2pp\")\n+\t\t\t\t (UNSPEC_MMA_PMXVI16GER2SPP\t\"xvi16ger2spp\")\n+\t\t\t\t (UNSPEC_MMA_PMXVF16GER2PP\t\"xvf16ger2pp\")\n+\t\t\t\t (UNSPEC_MMA_PMXVF16GER2PN\t\"xvf16ger2pn\")\n+\t\t\t\t (UNSPEC_MMA_PMXVF16GER2NP\t\"xvf16ger2np\")\n+\t\t\t\t (UNSPEC_MMA_PMXVF16GER2NN\t\"xvf16ger2nn\")\n+\t\t\t\t (UNSPEC_MMA_PMXVBF16GER2PP\t\"xvbf16ger2pp\")\n+\t\t\t\t (UNSPEC_MMA_PMXVBF16GER2PN\t\"xvbf16ger2pn\")\n+\t\t\t\t (UNSPEC_MMA_PMXVBF16GER2NP\t\"xvbf16ger2np\")\n+\t\t\t\t (UNSPEC_MMA_PMXVBF16GER2NN\t\"xvbf16ger2nn\")])\n \n-(define_int_attr vvi4i4\t\t[(UNSPEC_MMA_PMXVF32GER\t\t\"pmxvf32ger\")])\n+(define_int_attr vvi4i4\t\t[(UNSPEC_MMA_PMXVF32GER\t\t\"xvf32ger\")])\n \n-(define_int_attr avvi4i4\t[(UNSPEC_MMA_PMXVF32GERPP\t\"pmxvf32gerpp\")\n-\t\t\t\t (UNSPEC_MMA_PMXVF32GERPN\t\"pmxvf32gerpn\")\n-\t\t\t\t (UNSPEC_MMA_PMXVF32GERNP\t\"pmxvf32gernp\")\n-\t\t\t\t (UNSPEC_MMA_PMXVF32GERNN\t\"pmxvf32gernn\")])\n+(define_int_attr avvi4i4\t[(UNSPEC_MMA_PMXVF32GERPP\t\"xvf32gerpp\")\n+\t\t\t\t (UNSPEC_MMA_PMXVF32GERPN\t\"xvf32gerpn\")\n+\t\t\t\t (UNSPEC_MMA_PMXVF32GERNP\t\"xvf32gernp\")\n+\t\t\t\t (UNSPEC_MMA_PMXVF32GERNN\t\"xvf32gernn\")])\n \n-(define_int_attr pvi4i2\t\t[(UNSPEC_MMA_PMXVF64GER\t\t\"pmxvf64ger\")])\n+(define_int_attr pvi4i2\t\t[(UNSPEC_MMA_PMXVF64GER\t\t\"xvf64ger\")])\n \n-(define_int_attr apvi4i2\t[(UNSPEC_MMA_PMXVF64GERPP\t\"pmxvf64gerpp\")\n-\t\t\t\t (UNSPEC_MMA_PMXVF64GERPN\t\"pmxvf64gerpn\")\n-\t\t\t\t (UNSPEC_MMA_PMXVF64GERNP\t\"pmxvf64gernp\")\n-\t\t\t\t (UNSPEC_MMA_PMXVF64GERNN\t\"pmxvf64gernn\")])\n+(define_int_attr apvi4i2\t[(UNSPEC_MMA_PMXVF64GERPP\t\"xvf64gerpp\")\n+\t\t\t\t (UNSPEC_MMA_PMXVF64GERPN\t\"xvf64gerpn\")\n+\t\t\t\t (UNSPEC_MMA_PMXVF64GERNP\t\"xvf64gernp\")\n+\t\t\t\t (UNSPEC_MMA_PMXVF64GERNN\t\"xvf64gernn\")])\n \n-(define_int_attr vvi4i4i4\t[(UNSPEC_MMA_PMXVI8GER4\t\t\"pmxvi8ger4\")])\n+(define_int_attr vvi4i4i4\t[(UNSPEC_MMA_PMXVI8GER4\t\t\"xvi8ger4\")])\n \n-(define_int_attr avvi4i4i4\t[(UNSPEC_MMA_PMXVI8GER4PP\t\"pmxvi8ger4pp\")\n-\t\t\t\t (UNSPEC_MMA_PMXVI8GER4SPP\t\"pmxvi8ger4spp\")])\n+(define_int_attr avvi4i4i4\t[(UNSPEC_MMA_PMXVI8GER4PP\t\"xvi8ger4pp\")\n+\t\t\t\t (UNSPEC_MMA_PMXVI8GER4SPP\t\"xvi8ger4spp\")])\n \n \n ;; Vector pair support. OOmode can only live in VSRs.\n@@ -620,7 +622,7 @@ (define_insn \"mma_<vv>\"\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")]\n \t\t MMA_VV))]\n \"TARGET_MMA\"\n- \"<vv> %A0,%x1,%x2\"\n+ \"%!<vv> %A0,%x1,%x2\"\n [(set_attr \"type\" \"mma\")])\n \n ;; Instructions:\n@@ -636,7 +638,7 @@ (define_insn \"mma_<avv>\"\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")]\n \t\t MMA_AVV))]\n \"TARGET_MMA\"\n- \"<avv> %A0,%x2,%x3\"\n+ \"%!<avv> %A0,%x2,%x3\"\n [(set_attr \"type\" \"mma\")])\n \n ;; Instruction: xvf64ger\n@@ -647,7 +649,7 @@ (define_insn \"mma_<pv>\"\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")]\n \t\t MMA_PV))]\n \"TARGET_MMA\"\n- \"<pv> %A0,%x1,%x2\"\n+ \"%!<pv> %A0,%x1,%x2\"\n [(set_attr \"type\" \"mma\")])\n \n ;; Instructions: xvf64gerpp xvf64gerpn xvf64gernp xvf64gernn\n@@ -659,12 +661,12 @@ (define_insn \"mma_<apv>\"\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")]\n \t\t MMA_APV))]\n \"TARGET_MMA\"\n- \"<apv> %A0,%x2,%x3\"\n+ \"%!<apv> %A0,%x2,%x3\"\n [(set_attr \"type\" \"mma\")])\n \n ;; Instruction: pmxvi4ger8\n \n-(define_insn \"mma_<vvi4i4i8>\"\n+(define_insn \"mma_pm<vvi4i4i8>\"\n [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:V16QI 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n@@ -673,13 +675,13 @@ (define_insn \"mma_<vvi4i4i8>\"\n \t\t (match_operand:SI 5 \"u8bit_cint_operand\" \"n,n\")]\n \t\t MMA_VVI4I4I8))]\n \"TARGET_MMA\"\n- \"<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5\"\n+ \"pm%!<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n ;; Instruction: pmxvi4ger8pp\n \n-(define_insn \"mma_<avvi4i4i8>\"\n+(define_insn \"mma_pm<avvi4i4i8>\"\n [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n@@ -689,14 +691,14 @@ (define_insn \"mma_<avvi4i4i8>\"\n \t\t (match_operand:SI 6 \"u8bit_cint_operand\" \"n,n\")]\n \t\t MMA_AVVI4I4I8))]\n \"TARGET_MMA\"\n- \"<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6\"\n+ \"pm%!<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n ;; Instructions:\n ;; pmxvi16ger2 pmxvi16ger2s pmxvf16ger2 pmxvbf16ger2\n \n-(define_insn \"mma_<vvi4i4i2>\"\n+(define_insn \"mma_pm<vvi4i4i2>\"\n [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:V16QI 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n@@ -705,7 +707,7 @@ (define_insn \"mma_<vvi4i4i2>\"\n \t\t (match_operand:SI 5 \"const_0_to_3_operand\" \"n,n\")]\n \t\t MMA_VVI4I4I2))]\n \"TARGET_MMA\"\n- \"<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5\"\n+ \"pm%!<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n@@ -714,7 +716,7 @@ (define_insn \"mma_<vvi4i4i2>\"\n ;; pmxvf16ger2np pmxvf16ger2nn pmxvbf16ger2pp pmxvbf16ger2pn\n ;; pmxvbf16ger2np pmxvbf16ger2nn\n \n-(define_insn \"mma_<avvi4i4i2>\"\n+(define_insn \"mma_pm<avvi4i4i2>\"\n [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n@@ -724,13 +726,13 @@ (define_insn \"mma_<avvi4i4i2>\"\n \t\t (match_operand:SI 6 \"const_0_to_3_operand\" \"n,n\")]\n \t\t MMA_AVVI4I4I2))]\n \"TARGET_MMA\"\n- \"<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6\"\n+ \"pm%!<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n ;; Instruction: pmxvf32ger\n \n-(define_insn \"mma_<vvi4i4>\"\n+(define_insn \"mma_pm<vvi4i4>\"\n [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:V16QI 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n@@ -738,13 +740,13 @@ (define_insn \"mma_<vvi4i4>\"\n \t\t (match_operand:SI 4 \"const_0_to_15_operand\" \"n,n\")]\n \t\t MMA_VVI4I4))]\n \"TARGET_MMA\"\n- \"<vvi4i4> %A0,%x1,%x2,%3,%4\"\n+ \"pm%!<vvi4i4> %A0,%x1,%x2,%3,%4\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n ;; Instructions: pmxvf32gerpp pmxvf32gerpn pmxvf32gernp pmxvf32gernn\n \n-(define_insn \"mma_<avvi4i4>\"\n+(define_insn \"mma_pm<avvi4i4>\"\n [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n@@ -753,13 +755,13 @@ (define_insn \"mma_<avvi4i4>\"\n \t\t (match_operand:SI 5 \"const_0_to_15_operand\" \"n,n\")]\n \t\t MMA_AVVI4I4))]\n \"TARGET_MMA\"\n- \"<avvi4i4> %A0,%x2,%x3,%4,%5\"\n+ \"pm%!<avvi4i4> %A0,%x2,%x3,%4,%5\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n ;; Instruction: pmxvf64ger\n \n-(define_insn \"mma_<pvi4i2>\"\n+(define_insn \"mma_pm<pvi4i2>\"\n [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:OO 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n@@ -767,13 +769,13 @@ (define_insn \"mma_<pvi4i2>\"\n \t\t (match_operand:SI 4 \"const_0_to_3_operand\" \"n,n\")]\n \t\t MMA_PVI4I2))]\n \"TARGET_MMA\"\n- \"<pvi4i2> %A0,%x1,%x2,%3,%4\"\n+ \"pm%!<pvi4i2> %A0,%x1,%x2,%3,%4\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n ;; Instructions: pmxvf64gerpp pmxvf64gerpn pmxvf64gernp pmxvf64gernn\n \n-(define_insn \"mma_<apvi4i2>\"\n+(define_insn \"mma_pm<apvi4i2>\"\n [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:OO 2 \"vsx_register_operand\" \"v,?wa\")\n@@ -782,13 +784,13 @@ (define_insn \"mma_<apvi4i2>\"\n \t\t (match_operand:SI 5 \"const_0_to_3_operand\" \"n,n\")]\n \t\t MMA_APVI4I2))]\n \"TARGET_MMA\"\n- \"<apvi4i2> %A0,%x2,%x3,%4,%5\"\n+ \"pm%!<apvi4i2> %A0,%x2,%x3,%4,%5\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n ;; Instruction: pmxvi8ger4\n \n-(define_insn \"mma_<vvi4i4i4>\"\n+(define_insn \"mma_pm<vvi4i4i4>\"\n [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:V16QI 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n@@ -797,13 +799,13 @@ (define_insn \"mma_<vvi4i4i4>\"\n \t\t (match_operand:SI 5 \"const_0_to_15_operand\" \"n,n\")]\n \t\t MMA_VVI4I4I4))]\n \"TARGET_MMA\"\n- \"<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5\"\n+ \"pm%!<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n ;; Instructions: pmxvi8ger4pp pmxvi8ger4spp\n \n-(define_insn \"mma_<avvi4i4i4>\"\n+(define_insn \"mma_pm<avvi4i4i4>\"\n [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n@@ -813,7 +815,7 @@ (define_insn \"mma_<avvi4i4i4>\"\n \t\t (match_operand:SI 6 \"const_0_to_15_operand\" \"n,n\")]\n \t\t MMA_AVVI4I4I4))]\n \"TARGET_MMA\"\n- \"<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6\"\n+ \"pm%!<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \f\ndiff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc\nindex 9bbdc983b40..f18d1de08c6 100644\n--- a/gcc/config/rs6000/rs6000.cc\n+++ b/gcc/config/rs6000/rs6000.cc\n@@ -14832,6 +14832,12 @@ print_operand (FILE *file, rtx x, int code)\n \t\t\t\t\"local dynamic TLS references\");\n return;\n \n+ /* Print out 'dm' if dense math registers are available. */\n+ case '!':\n+ if (TARGET_DENSE_MATH)\n+\tfputs (\"dm\", file);\n+ return;\n+\n default:\n output_operand_lossage (\"invalid %%xn code\");\n }\ndiff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h\nindex 495fe884f33..9903ee7f36f 100644\n--- a/gcc/config/rs6000/rs6000.h\n+++ b/gcc/config/rs6000/rs6000.h\n@@ -2204,7 +2204,7 @@ extern char rs6000_reg_names[][8];\t/* register names (0 vs. %r0). */\n \n /* Define which CODE values are valid. */\n \n-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&')\n+#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&' || (CODE) == '!')\n \n /* Print a memory address as an operand to reference that memory location. */\n \n", "prefixes": [] }