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{ "id": 2230855, "url": "http://patchwork.ozlabs.org/api/patches/2230855/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/afL6QNhpdK17Fgs1@cowardly-lion.the-meissners.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<afL6QNhpdK17Fgs1@cowardly-lion.the-meissners.org>", "list_archive_url": null, "date": "2026-04-30T06:44:16", "name": "GCC 17, PowerPC Dense Math V7 (patch 5/7) -- Implement 1,024 bit dense math registers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1631d67f4e87da75600bfb65d91fd88070fbf6d9", "submitter": { "id": 73991, "url": "http://patchwork.ozlabs.org/api/people/73991/?format=api", "name": "Michael Meissner", "email": "meissner@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/afL6QNhpdK17Fgs1@cowardly-lion.the-meissners.org/mbox/", "series": [ { "id": 502216, "url": "http://patchwork.ozlabs.org/api/series/502216/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502216", "date": "2026-04-30T06:44:16", "name": "GCC 17, PowerPC Dense Math V7 (patch 5/7) -- Implement 1,024 bit dense math registers", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502216/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230855/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230855/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=WjAVm2XX;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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a=rsa-sha256; d=sourceware.org; s=key; t=1777531463; cv=none;\n b=ZaqjDvHPL8dOygvU6hA1XeOftmHXMDjJrqZpE3pRHQvEdL1uyh+ZIb/YihGpkWgXXf5pmrG5iJHsig3kPUYaJCGlYrehTMQWlNGg9CdfqHkPLvCV8pishHxVj9bqHLombNVGJy6V7erdlnoCGX4/ZXprEfrcGgZxo5Ykcw7paaU=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1777531463; c=relaxed/simple;\n bh=3fB1y1o3NIRuYQMJll7RXiTW/WTWz8/kN7z8n1CqYm4=;\n h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version;\n b=ZLxvodh3fCm0l/HHnK/0jysRRHYA2w1rxFYGLyWl6JzKL3/6SuihVcrkrx2u5T82kW6fvcfFlHST6vvbVP8ql61hplkHsOCTyi+ud4EGrNcGgQw5MTHwFkS0XwHYKurbjz3Ld3/+RuQtrJjBiHFNzTc7KP1mCJF/CDebT7o+DQs=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=\n content-type:date:from:in-reply-to:message-id:mime-version\n :references:subject:to; s=pp1; bh=kK79668eio15QkTgdBxO2uUiAZx0PV\n snRyVli/iZCeM=; b=WjAVm2XXvm/iwHh0Ie797fJyE9NGzuN/PMjzdV9hbn/mQZ\n mHS1Q6XoWaCyWw5r4nM7odqFICDZoZsHkz5oAJaZUAGLnPalvQTFoWUI/fG5iUXu\n sAwyJ3wX0jcQQaynp10onRgRWZRwUR2nDp+vEl5l2hfSgkLuWywUEHWdzEgce/PV\n ufI5gt0lGDoO2V4kY0W014imUGTASX8GJbh7OXQFzK9C0JKsEWSrPdnAPVwwTij2\n VVYStSJjicK4McNiHcKuHNq78LkI3uxTV8CUsnZiD7efNhEUxJE9OjrO8yWpgVqg\n k/ye0TGqhS2rQ/NRdR5kx9QTNxzTpH7gCHf2F51Q==", "Date": "Thu, 30 Apr 2026 02:44:16 -0400", "From": "Michael Meissner <meissner@linux.ibm.com>", "To": "Michael Meissner <meissner@linux.ibm.com>, gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "Subject": "GCC 17, PowerPC Dense Math V7 (patch 5/7) -- Implement 1,024 bit\n dense math registers", "Message-ID": "<afL6QNhpdK17Fgs1@cowardly-lion.the-meissners.org>", "Mail-Followup-To": "Michael Meissner <meissner@linux.ibm.com>,\n gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "References": "<afL4oa26tUJlc9zg@cowardly-lion.the-meissners.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=us-ascii", "Content-Disposition": "inline", "In-Reply-To": "<afL4oa26tUJlc9zg@cowardly-lion.the-meissners.org>", "X-TM-AS-GCONF": "00", "X-Authority-Analysis": "v=2.4 cv=CIIamxrD c=1 sm=1 tr=0 ts=69f2fa46 cx=c_pps\n a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17\n a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=mDV3o1hIAAAA:8\n a=VnNF1IyMAAAA:8 a=UJit8S1sEH1VzGorIX8A:9 a=3ZKOabzyN94A:10 a=CjuIK1q_8ugA:10", "X-Proofpoint-ORIG-GUID": "P-c-WGwmAvqL4lOYjgl9n0v5CD7X3Qp3", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDMwMDA2MCBTYWx0ZWRfXxGN0G5bIzsnx\n W6RBzQaN3/oI5YsPHrGDvYxhGfviAdMiUsCtOQ7Tgc6rEkYGGPqPyQbez06hjNbqz4NBh0/Sb59\n JuDvsDMUQrAY4gS0xn1wOANGyv2F+pY+yZ1wpCYyrRSlbi7Jm2ctfbnEx52CB009Y/TayZC8jmy\n 7Uiw28z3kM+AT5NToHoa+n8r3/tvjHyco18JU9G+0GTl0BW9K8UqbRfBdfn9oUWqoSccJ697BoP\n k7XgaIsfpH1gbyqA7Hl2UjStEfjd9X3mQczXqnucMaud0A6IBU8tzGPiPXm2XKPa3A/tpX6jII9\n BKCcPiDWdntXi7THUQvQNnooF+zgrF7QoAInEg9xTog5ZT501wcHWPA0zq55C4x/ylukzPsL8Vk\n Bca25/FakOibVgHw5n0omJrezG+L2Q1Q+x+Q0HolXMjWfEGhsry+nCuQ/rPNuURe1/cqfk6kGrp\n DsL7xPXZQ9lOZM4ZOCQ==", "X-Proofpoint-GUID": "P-c-WGwmAvqL4lOYjgl9n0v5CD7X3Qp3", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-30_02,2026-04-28_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 phishscore=0 malwarescore=0 suspectscore=0 adultscore=0\n impostorscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0\n priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604300060", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This is part five of the dense math register patches for the PowerPC.\nThis is the 7th version of the dense math patches.\n\nVersion 6 of the dense math register patches were posted on April 21st,\n2026.\n\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713352.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713353.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713354.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713355.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713356.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713357.html\n\nThis patch needs the -mcpu=future patch posted on April 8th, 2026:\n\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/712532.html\n\nThis patch is functionally the same as the version 6 patch, except I made the\nsame name changes as I discussed in the previous patch.\n\nThis patch (#5) is a prelimianry patch to add the full 1,024 bit dense math\nregister (DMFs) for -mcpu=future. The MMA 512-bit accumulators map onto the top\nof the DMR register.\n\nThis patch only adds the new 1,024 bit register support. It does not add\nsupport for any instructions that need 1,024 bit registers instead of 512 bit\nregisters.\n\nI used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit\nregisters. The 'wD' constraint added in previous patches is used for these\nregisters. I added support to do load and store of DMRs via the VSX registers,\nsince there are no load/store dense math instructions. I added the new keyword\n'__dm1024' to create 1,024 bit types that can be loaded into dense math\nregisters.\n\nI have built bootstrap little endian compilers on power10 systems, and\nbig endian compiler on power9 systems. There were no regression in the\ntests. Can I add the patches to the GCC trunk after the -mcpu=future\npatch is applied and GCC 17 has opened up?\n\n2026-04-29 Michael Meissner <meissner@linux.ibm.com>\n\ngcc/\n\n\t* config/rs6000/mma.md (UNSPEC_DMF_INSERT512_UPPER): New unspec.\n\t(UNSPEC_DMF_INSERT512_LOWER): Likewise.\n\t(UNSPEC_DMF_EXTRACT512): Likewise.\n\t(UNSPEC_DMF_RELOAD_FROM_MEMORY): Likewise.\n\t(UNSPEC_DMF_RELOAD_TO_MEMORY): Likewise.\n\t(movtdo): New define_expand and define_insn_and_split to implement 1,024\n\tbit dense math registers.\n\t(movtdo_insert512_upper): New insn.\n\t(movtdo_insert512_lower): Likewise.\n\t(movtdo_extract512): Likewise.\n\t(reload_tdo_from_memory): Likewise.\n\t(reload_tdo_to_memory): Likewise.\n\t* config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add dense math\n\tregister support.\n\t(rs6000_init_builtins): Add support for __dm1024 keyword.\n\t* config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add support\n\tfor TDOmode.\n\t(rs6000_function_arg): Likewise.\n\t* config/rs6000/rs6000-modes.def (TDOmode): New mode.\n\t* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add\n\tsupport for TDOmode.\n\t(rs6000_hard_regno_mode_ok): Likewise.\n\t(rs6000_modes_tieable_p): Likewise.\n\t(rs6000_debug_reg_global): Likewise.\n\t(rs6000_setup_reg_addr_masks): Likewise.\n\t(rs6000_init_hard_regno_mode_ok): Add support for TDOmode. Setup reload\n\thooks for dense math TDO reload mode.\n\t(reg_offset_addressing_ok_p): Add support for TDOmode.\n\t(rs6000_emit_move): Likewise.\n\t(rs6000_secondary_reload_simple_move): Likewise.\n\t(rs6000_preferred_reload_class): Likewise.\n\t(rs6000_mangle_type): Add mangling for __dm1024 type.\n\t(rs6000_dmf_register_move_cost): Add support for TDOmode.\n\t(rs6000_split_multireg_move): Likewise.\n\t(rs6000_invalid_conversion): Likewise.\n\t* config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode.\n\t(enum rs6000_builtin_type_index): Add dense math register type nodes.\n\t(dm1024_type_node): Likewise.\n\t(ptr_dm1024_type_node): Likewise.\n\ngcc/testsuite/\n\n\t* gcc.target/powerpc/dm-1024bit.c: New test.\n---\n gcc/config/rs6000/mma.md | 155 ++++++++++++++++++++++++++++\n gcc/config/rs6000/rs6000-builtin.cc | 17 +++\n gcc/config/rs6000/rs6000-call.cc | 10 +-\n gcc/config/rs6000/rs6000-modes.def | 4 +\n gcc/config/rs6000/rs6000.cc | 109 ++++++++++++++-----\n gcc/config/rs6000/rs6000.h | 6 +-\n 6 files changed, 270 insertions(+), 31 deletions(-)", "diff": "diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md\nindex c017b7ca1e7..95cee85925b 100644\n--- a/gcc/config/rs6000/mma.md\n+++ b/gcc/config/rs6000/mma.md\n@@ -92,6 +92,11 @@ (define_c_enum \"unspec\"\n UNSPEC_MMA_XXMFACC\n UNSPEC_MMA_XXMTACC\n UNSPEC_MMA_DMSETDMRZ\n+ UNSPEC_DMF_INSERT512_UPPER\n+ UNSPEC_DMF_INSERT512_LOWER\n+ UNSPEC_DMF_EXTRACT512\n+ UNSPEC_DMF_RELOAD_FROM_MEMORY\n+ UNSPEC_DMF_RELOAD_TO_MEMORY\n ])\n \n (define_c_enum \"unspecv\"\n@@ -811,3 +816,153 @@ (define_insn \"mma_<avvi4i4i4>\"\n \"<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n+\f\n+;; TDOmode (__dmf keyword for 1,024 bit registers).\n+(define_expand \"movtdo\"\n+ [(set (match_operand:TDO 0 \"nonimmediate_operand\")\n+\t(match_operand:TDO 1 \"input_operand\"))]\n+ \"TARGET_DENSE_MATH\"\n+{\n+ rs6000_emit_move (operands[0], operands[1], TDOmode);\n+ DONE;\n+})\n+\n+(define_insn_and_split \"*movtdo\"\n+ [(set (match_operand:TDO 0 \"nonimmediate_operand\" \"=wa,m,wa,wD,wD,wa\")\n+\t(match_operand:TDO 1 \"input_operand\" \"m,wa,wa,wa,wD,wD\"))]\n+ \"TARGET_DENSE_MATH\n+ && (gpc_reg_operand (operands[0], TDOmode)\n+ || gpc_reg_operand (operands[1], TDOmode))\"\n+ \"@\n+ #\n+ #\n+ #\n+ #\n+ dmmr %0,%1\n+ #\"\n+ \"&& reload_completed\n+ && (!dmf_register_operand (operands[0], TDOmode)\n+ || !dmf_register_operand (operands[1], TDOmode))\"\n+ [(const_int 0)]\n+{\n+ rtx op0 = operands[0];\n+ rtx op1 = operands[1];\n+\n+ if (REG_P (op0) && REG_P (op1))\n+ {\n+ int regno0 = REGNO (op0);\n+ int regno1 = REGNO (op1);\n+\n+ if (DMF_REGNO_P (regno0) && VSX_REGNO_P (regno1))\n+\t{\n+\t rtx op1_upper = gen_rtx_REG (XOmode, regno1);\n+\t rtx op1_lower = gen_rtx_REG (XOmode, regno1 + 4);\n+\t emit_insn (gen_movtdo_insert512_upper (op0, op1_upper));\n+\t emit_insn (gen_movtdo_insert512_lower (op0, op0, op1_lower));\n+\t DONE;\n+\t}\n+\n+ else if (VSX_REGNO_P (regno0) && DMF_REGNO_P (regno1))\n+\t{\n+\t rtx op0_upper = gen_rtx_REG (XOmode, regno0);\n+\t rtx op0_lower = gen_rtx_REG (XOmode, regno0 + 4);\n+\t emit_insn (gen_movtdo_extract512 (op0_upper, op1, const0_rtx));\n+\t emit_insn (gen_movtdo_extract512 (op0_lower, op1, const1_rtx));\n+\t DONE;\n+\t}\n+\n+ else\n+\tgcc_assert (VSX_REGNO_P (regno0) && VSX_REGNO_P (regno1));\n+ }\n+\n+ rs6000_split_multireg_move (operands[0], operands[1]);\n+ DONE;\n+}\n+ [(set_attr \"type\" \"vecload,vecstore,vecmove,vecmove,vecmove,vecmove\")\n+ (set_attr \"length\" \"*,*,32,8,*,8\")\n+ (set_attr \"max_prefixed_insns\" \"4,4,*,*,*,*\")])\n+\n+;; Move from VSX registers to dense math registers via two insert 512 bit\n+;; instructions.\n+(define_insn \"movtdo_insert512_upper\"\n+ [(set (match_operand:TDO 0 \"dmf_register_operand\" \"=wD\")\n+\t(unspec:TDO [(match_operand:XO 1 \"vsx_register_operand\" \"wa\")]\n+\t\t UNSPEC_DMF_INSERT512_UPPER))]\n+ \"TARGET_DENSE_MATH\"\n+ \"dmxxinstdmr512 %0,%1,%Y1,0\"\n+ [(set_attr \"type\" \"mma\")])\n+\n+(define_insn \"movtdo_insert512_lower\"\n+ [(set (match_operand:TDO 0 \"dmf_register_operand\" \"=wD\")\n+\t(unspec:TDO [(match_operand:TDO 1 \"dmf_register_operand\" \"0\")\n+\t\t (match_operand:XO 2 \"vsx_register_operand\" \"wa\")]\n+\t\t UNSPEC_DMF_INSERT512_LOWER))]\n+ \"TARGET_DENSE_MATH\"\n+ \"dmxxinstdmr512 %0,%2,%Y2,1\"\n+ [(set_attr \"type\" \"mma\")])\n+\n+;; Move from dense math registers to VSX registers via two extract 512 bit\n+;; instructions.\n+(define_insn \"movtdo_extract512\"\n+ [(set (match_operand:XO 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:XO [(match_operand:TDO 1 \"dmf_register_operand\" \"wD\")\n+\t\t (match_operand 2 \"const_0_to_1_operand\" \"n\")]\n+\t\t UNSPEC_DMF_EXTRACT512))]\n+ \"TARGET_DENSE_MATH\"\n+ \"dmxxextfdmr512 %0,%Y0,%1,%2\"\n+ [(set_attr \"type\" \"mma\")])\n+\n+;; Reload dense math registers from memory.\n+(define_insn_and_split \"reload_tdo_from_memory\"\n+ [(set (match_operand:TDO 0 \"dmf_register_operand\" \"=wD\")\n+\t(unspec:TDO [(match_operand:TDO 1 \"memory_operand\" \"m\")]\n+\t\t UNSPEC_DMF_RELOAD_FROM_MEMORY))\n+ (clobber (match_operand:XO 2 \"vsx_register_operand\" \"=wa\"))]\n+ \"TARGET_DENSE_MATH\"\n+ \"#\"\n+ \"&& reload_completed\"\n+ [(const_int 0)]\n+{\n+ rtx dest = operands[0];\n+ rtx src = operands[1];\n+ rtx tmp = operands[2];\n+ rtx mem_upper = adjust_address (src, XOmode, BYTES_BIG_ENDIAN ? 0 : 64);\n+ rtx mem_lower = adjust_address (src, XOmode, BYTES_BIG_ENDIAN ? 64 : 0);\n+\n+ emit_move_insn (tmp, mem_upper);\n+ emit_insn (gen_movtdo_insert512_upper (dest, tmp));\n+\n+ emit_move_insn (tmp, mem_lower);\n+ emit_insn (gen_movtdo_insert512_lower (dest, dest, tmp));\n+ DONE;\n+}\n+ [(set_attr \"length\" \"16\")\n+ (set_attr \"max_prefixed_insns\" \"2\")\n+ (set_attr \"type\" \"vecload\")])\n+\n+;; Reload dense math registers to memory\n+(define_insn_and_split \"reload_tdo_to_memory\"\n+ [(set (match_operand:TDO 0 \"memory_operand\" \"=m\")\n+\t(unspec:TDO [(match_operand:TDO 1 \"dmf_register_operand\" \"wD\")]\n+\t\t UNSPEC_DMF_RELOAD_TO_MEMORY))\n+ (clobber (match_operand:XO 2 \"vsx_register_operand\" \"=wa\"))]\n+ \"TARGET_DENSE_MATH\"\n+ \"#\"\n+ \"&& reload_completed\"\n+ [(const_int 0)]\n+{\n+ rtx dest = operands[0];\n+ rtx src = operands[1];\n+ rtx tmp = operands[2];\n+ rtx mem_upper = adjust_address (dest, XOmode, BYTES_BIG_ENDIAN ? 0 : 64);\n+ rtx mem_lower = adjust_address (dest, XOmode, BYTES_BIG_ENDIAN ? 64 : 0);\n+\n+ emit_insn (gen_movtdo_extract512 (tmp, src, const0_rtx));\n+ emit_move_insn (mem_upper, tmp);\n+\n+ emit_insn (gen_movtdo_extract512 (tmp, src, const1_rtx));\n+ emit_move_insn (mem_lower, tmp);\n+ DONE;\n+}\n+ [(set_attr \"length\" \"16\")\n+ (set_attr \"max_prefixed_insns\" \"2\")])\ndiff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc\nindex de9f4b519f1..19ff2c1e29b 100644\n--- a/gcc/config/rs6000/rs6000-builtin.cc\n+++ b/gcc/config/rs6000/rs6000-builtin.cc\n@@ -500,6 +500,8 @@ const char *rs6000_type_string (tree type_node)\n return \"__vector_pair\";\n else if (type_node == vector_quad_type_node)\n return \"__vector_quad\";\n+ else if (type_node == dm1024_type_node)\n+ return \"__dm1024\";\n \n return \"unknown\";\n }\n@@ -786,6 +788,21 @@ rs6000_init_builtins (void)\n t = build_qualified_type (vector_quad_type_node, TYPE_QUAL_CONST);\n ptr_vector_quad_type_node = build_pointer_type (t);\n \n+ /* For TDOmode (1,024 bit dense math accumulators), don't use an alignment of\n+ 1,024, use 512. TDOmode loads and stores are always broken up into 2\n+ vector pair loads or stores. In addition, we don't have support for\n+ aligning the stack to 1,024 bits. */\n+ dm1024_type_node = make_node (OPAQUE_TYPE);\n+ SET_TYPE_MODE (dm1024_type_node, TDOmode);\n+ TYPE_SIZE (dm1024_type_node) = bitsize_int (GET_MODE_BITSIZE (TDOmode));\n+ TYPE_PRECISION (dm1024_type_node) = GET_MODE_BITSIZE (TDOmode);\n+ TYPE_SIZE_UNIT (dm1024_type_node) = size_int (GET_MODE_SIZE (TDOmode));\n+ SET_TYPE_ALIGN (dm1024_type_node, 512);\n+ TYPE_USER_ALIGN (dm1024_type_node) = 0;\n+ lang_hooks.types.register_builtin_type (dm1024_type_node, \"__dm1024\");\n+ t = build_qualified_type (dm1024_type_node, TYPE_QUAL_CONST);\n+ ptr_dm1024_type_node = build_pointer_type (t);\n+\n tdecl = add_builtin_type (\"__bool char\", bool_char_type_node);\n TYPE_NAME (bool_char_type_node) = tdecl;\n \ndiff --git a/gcc/config/rs6000/rs6000-call.cc b/gcc/config/rs6000/rs6000-call.cc\nindex e31b147a3b9..e57162f3b20 100644\n--- a/gcc/config/rs6000/rs6000-call.cc\n+++ b/gcc/config/rs6000/rs6000-call.cc\n@@ -437,14 +437,15 @@ rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)\n if (cfun\n && !cfun->machine->mma_return_type_error\n && TREE_TYPE (cfun->decl) == fntype\n- && (TYPE_MODE (type) == OOmode || TYPE_MODE (type) == XOmode))\n+ && OPAQUE_MODE_P (TYPE_MODE (type)))\n {\n /* Record we have now handled function CFUN, so the next time we\n \t are called, we do not re-report the same error. */\n cfun->machine->mma_return_type_error = true;\n if (TYPE_CANONICAL (type) != NULL_TREE)\n \ttype = TYPE_CANONICAL (type);\n- error (\"invalid use of MMA type %qs as a function return value\",\n+ error (\"invalid use of %s type %qs as a function return value\",\n+\t (TYPE_MODE (type) == TDOmode) ? \"dense math\" : \"MMA\",\n \t IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))));\n }\n \n@@ -1632,11 +1633,12 @@ rs6000_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)\n int n_elts;\n \n /* We do not allow MMA types being used as function arguments. */\n- if (mode == OOmode || mode == XOmode)\n+ if (OPAQUE_MODE_P (mode))\n {\n if (TYPE_CANONICAL (type) != NULL_TREE)\n \ttype = TYPE_CANONICAL (type);\n- error (\"invalid use of MMA operand of type %qs as a function parameter\",\n+ error (\"invalid use of %s operand of type %qs as a function parameter\",\n+\t (mode == TDOmode) ? \"dense math\" : \"MMA\",\n \t IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))));\n return NULL_RTX;\n }\ndiff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def\nindex 7140b634c41..6fca027949d 100644\n--- a/gcc/config/rs6000/rs6000-modes.def\n+++ b/gcc/config/rs6000/rs6000-modes.def\n@@ -79,3 +79,7 @@ PARTIAL_INT_MODE (TI, 128, PTI);\n /* Modes used by __vector_pair and __vector_quad. */\n OPAQUE_MODE (OO, 32);\n OPAQUE_MODE (XO, 64);\n+\n+/* Mode used by __dmf. */\n+OPAQUE_MODE (TDO, 128);\n+\ndiff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc\nindex 745d57b1d76..9bbdc983b40 100644\n--- a/gcc/config/rs6000/rs6000.cc\n+++ b/gcc/config/rs6000/rs6000.cc\n@@ -1897,7 +1897,22 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)\n \t\t&& (regno & 1) == 0);\n }\n \n- /* No other types other than XOmode can go in dense math registers. */\n+ if (mode == TDOmode)\n+ {\n+ if (!TARGET_DENSE_MATH)\n+\treturn 0;\n+\n+ if (DMF_REGNO_P (regno))\n+ return 1;\n+\n+ else\n+ return (VSX_REGNO_P (regno)\n+ && VSX_REGNO_P (last_regno)\n+ && (regno & 1) == 0);\n+ }\n+\n+ /* No other types other than XOmode or TDOmode can go in dense math\n+ registers. */\n if (DMF_REGNO_P (regno))\n return 0;\n \n@@ -2005,9 +2020,11 @@ rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)\n GPR registers, and TImode can go in any GPR as well as VSX registers (PR\n 57744).\n \n- Similarly, don't allow OOmode (vector pair, restricted to even VSX\n- registers) or XOmode (vector quad, restricted to FPR registers divisible\n- by 4) to tie with other modes.\n+ Similarly, don't allow OOmode (vector pair), XOmode (vector quad), or\n+ TDOmode (dense math register) to pair with anything else. Vector pairs are\n+ restricted to even/odd VSX registers. Without dense math, vector quads are\n+ limited to FPR registers divisible by 4. With dense math, vector quads are\n+ limited to even VSX registers or dense math registers.\n \n Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE\n 128-bit floating point on VSX systems ties with other vectors. */\n@@ -2016,7 +2033,8 @@ static bool\n rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)\n {\n if (mode1 == PTImode || mode1 == OOmode || mode1 == XOmode\n- || mode2 == PTImode || mode2 == OOmode || mode2 == XOmode)\n+ || mode1 == TDOmode || mode2 == PTImode || mode2 == OOmode\n+ || mode2 == XOmode || mode2 == TDOmode)\n return mode1 == mode2;\n \n if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))\n@@ -2307,6 +2325,7 @@ rs6000_debug_reg_global (void)\n V4DFmode,\n OOmode,\n XOmode,\n+ TDOmode,\n CCmode,\n CCUNSmode,\n CCEQmode,\n@@ -2672,7 +2691,7 @@ rs6000_setup_reg_addr_masks (void)\n \t /* Special case dense math registers. */\n \t if (rc == RELOAD_REG_DMR)\n \t {\n-\t if (TARGET_DENSE_MATH && m2 == XOmode)\n+\t if (TARGET_DENSE_MATH && (m2 == XOmode || m2 == TDOmode))\n \t\t{\n \t\t addr_mask = RELOAD_REG_VALID;\n \t\t reg_addr[m].addr_mask[rc] = addr_mask;\n@@ -2779,10 +2798,10 @@ rs6000_setup_reg_addr_masks (void)\n \n \t /* Vector pairs can do both indexed and offset loads if the\n \t instructions are enabled, otherwise they can only do offset loads\n-\t since it will be broken into two vector moves. Vector quads can\n-\t only do offset loads. */\n+\t since it will be broken into two vector moves. Vector quads and\n+\t dense math types can only do offset loads. */\n \t else if ((addr_mask != 0) && TARGET_MMA\n-\t\t && (m2 == OOmode || m2 == XOmode))\n+\t\t && (m2 == OOmode || m2 == XOmode || m2 == TDOmode))\n \t {\n \t addr_mask |= RELOAD_REG_OFFSET;\n \t if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)\n@@ -3010,6 +3029,14 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)\n rs6000_vector_align[XOmode] = 512;\n }\n \n+ /* Add support for 1,024 bit dense math registers. */\n+ if (TARGET_DENSE_MATH)\n+ {\n+ rs6000_vector_unit[TDOmode] = VECTOR_NONE;\n+ rs6000_vector_mem[TDOmode] = VECTOR_VSX;\n+ rs6000_vector_align[TDOmode] = 512;\n+ }\n+\n /* Register class constraints for the constraints that depend on compile\n switches. When the VSX code was added, different constraints were added\n based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all\n@@ -3223,6 +3250,12 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)\n \t}\n }\n \n+ if (TARGET_DENSE_MATH)\n+ {\n+ reg_addr[TDOmode].reload_load = CODE_FOR_reload_tdo_from_memory;\n+ reg_addr[TDOmode].reload_store = CODE_FOR_reload_tdo_to_memory;\n+ }\n+\n /* Precalculate HARD_REGNO_NREGS. */\n for (r = 0; HARD_REGISTER_NUM_P (r); ++r)\n for (m = 0; m < NUM_MACHINE_MODES; ++m)\n@@ -8736,12 +8769,15 @@ reg_offset_addressing_ok_p (machine_mode mode)\n \treturn mode_supports_dq_form (mode);\n break;\n \n- /* The vector pair/quad types support offset addressing if the\n-\t underlying vectors support offset addressing. */\n+ /* The vector pair/quad types and the dense math types support offset\n+\t addressing if the underlying vectors support offset addressing. */\n case E_OOmode:\n case E_XOmode:\n return TARGET_MMA;\n \n+ case E_TDOmode:\n+ return TARGET_DENSE_MATH;\n+\n case E_SDmode:\n /* If we can do direct load/stores of SDmode, restrict it to reg+reg\n \t addressing for the LFIWZX and STFIWX instructions. */\n@@ -11295,6 +11331,12 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode)\n \t (mode == OOmode) ? \"__vector_pair\" : \"__vector_quad\");\n break;\n \n+ case E_TDOmode:\n+ if (CONST_INT_P (operands[1]))\n+\terror (\"%qs is an opaque type, and you cannot set it to constants\",\n+\t \"__dm1024\");\n+ break;\n+\n case E_SImode:\n case E_DImode:\n /* Use default pattern for address of ELF small data */\n@@ -12758,7 +12800,7 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,\n \n /* We can transfer between VSX registers and dense math registers without\n needing extra registers. */\n- if (TARGET_DENSE_MATH && mode == XOmode\n+ if (TARGET_DENSE_MATH && (mode == XOmode || mode == TDOmode)\n && ((to_type == DMF_REG_TYPE && from_type == VSX_REG_TYPE)\n \t || (to_type == VSX_REG_TYPE && from_type == DMF_REG_TYPE)))\n return true;\n@@ -13559,6 +13601,9 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass)\n if (mode == XOmode)\n \treturn TARGET_DENSE_MATH ? VSX_REGS : FLOAT_REGS;\n \n+ if (mode == TDOmode)\n+\treturn VSX_REGS;\n+\n if (GET_MODE_CLASS (mode) == MODE_INT)\n \treturn GENERAL_REGS;\n }\n@@ -20733,6 +20778,8 @@ rs6000_mangle_type (const_tree type)\n return \"u13__vector_pair\";\n if (type == vector_quad_type_node)\n return \"u13__vector_quad\";\n+ if (type == dm1024_type_node)\n+ return \"u8__dm1024\";\n \n /* For all other types, use the default mangling. */\n return NULL;\n@@ -22863,6 +22910,10 @@ rs6000_dmf_register_move_cost (machine_mode mode, reg_class_t rclass)\n if (mode == XOmode)\n \treturn reg_move_base;\n \n+ /* __dm1024 (i.e. TDOmode) is transferred in 2 instructions. */\n+ else if (mode == TDOmode)\n+\treturn reg_move_base * 2;\n+\n else\n \treturn reg_move_base * 2 * hard_regno_nregs (FIRST_DMF_REGNO, mode);\n }\n@@ -27549,9 +27600,10 @@ rs6000_split_multireg_move (rtx dst, rtx src)\n mode = GET_MODE (dst);\n nregs = hard_regno_nregs (reg, mode);\n \n- /* If we have a vector quad register for MMA, and this is a load or store,\n- see if we can use vector paired load/stores. */\n- if (mode == XOmode && TARGET_MMA\n+ /* If we have a vector quad register for MMA or dense math register\n+ and this is a load or store, see if we can use vector paired\n+ load/stores. */\n+ if ((mode == XOmode || mode == TDOmode) && TARGET_MMA\n && (MEM_P (dst) || MEM_P (src)))\n {\n reg_mode = OOmode;\n@@ -27559,7 +27611,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)\n }\n /* If we have a vector pair/quad mode, split it into two/four separate\n vectors. */\n- else if (mode == OOmode || mode == XOmode)\n+ else if (mode == OOmode || mode == XOmode || mode == TDOmode)\n reg_mode = V1TImode;\n else if (FP_REGNO_P (reg))\n reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :\n@@ -27605,13 +27657,13 @@ rs6000_split_multireg_move (rtx dst, rtx src)\n return;\n }\n \n- /* The __vector_pair and __vector_quad modes are multi-register\n- modes, so if we have to load or store the registers, we have to be\n- careful to properly swap them if we're in little endian mode\n- below. This means the last register gets the first memory\n- location. We also need to be careful of using the right register\n- numbers if we are splitting XO to OO. */\n- if (mode == OOmode || mode == XOmode)\n+ /* The __vector_pair, __vector_quad, and __dm1024 modes are multi-register\n+ modes, so if we have to load or store the registers, we have to be careful\n+ to properly swap them if we're in little endian mode below. This means\n+ the last register gets the first memory location. We also need to be\n+ careful of using the right register numbers if we are splitting XO to\n+ OO. */\n+ if (mode == OOmode || mode == XOmode || mode == TDOmode)\n {\n nregs = hard_regno_nregs (reg, mode);\n int reg_mode_nregs = hard_regno_nregs (reg, reg_mode);\n@@ -27748,7 +27800,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)\n \t overlap. */\n int i;\n /* XO/OO are opaque so cannot use subregs. */\n- if (mode == OOmode || mode == XOmode )\n+ if (mode == OOmode || mode == XOmode || mode == TDOmode)\n \t{\n \t for (i = nregs - 1; i >= 0; i--)\n \t {\n@@ -27922,7 +27974,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)\n \t continue;\n \n \t /* XO/OO are opaque so cannot use subregs. */\n-\t if (mode == OOmode || mode == XOmode )\n+\t if (mode == OOmode || mode == XOmode || mode == TDOmode)\n \t {\n \t rtx dst_i = gen_rtx_REG (reg_mode, REGNO (dst) + j);\n \t rtx src_i = gen_rtx_REG (reg_mode, REGNO (src) + j);\n@@ -28950,7 +29002,8 @@ rs6000_invalid_conversion (const_tree fromtype, const_tree totype)\n \n if (frommode != tomode)\n {\n- /* Do not allow conversions to/from XOmode and OOmode types. */\n+ /* Do not allow conversions to/from XOmode, OOmode, and TDOmode\n+\t types. */\n if (frommode == XOmode)\n \treturn N_(\"invalid conversion from type %<__vector_quad%>\");\n if (tomode == XOmode)\n@@ -28959,6 +29012,10 @@ rs6000_invalid_conversion (const_tree fromtype, const_tree totype)\n \treturn N_(\"invalid conversion from type %<__vector_pair%>\");\n if (tomode == OOmode)\n \treturn N_(\"invalid conversion to type %<__vector_pair%>\");\n+ if (frommode == TDOmode)\n+\treturn N_(\"invalid conversion from type %<__dm1024%>\");\n+ if (tomode == TDOmode)\n+\treturn N_(\"invalid conversion to type %<__dm1024%>\");\n }\n \n /* Conversion allowed. */\ndiff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h\nindex a33b482a67b..495fe884f33 100644\n--- a/gcc/config/rs6000/rs6000.h\n+++ b/gcc/config/rs6000/rs6000.h\n@@ -989,7 +989,7 @@ enum data_align { align_abi, align_opt, align_both };\n /* Modes that are not vectors, but require vector alignment. Treat these like\n vectors in terms of loads and stores. */\n #define VECTOR_ALIGNMENT_P(MODE)\t\t\t\t\t\\\n- (FLOAT128_VECTOR_P (MODE) || (MODE) == OOmode || (MODE) == XOmode)\n+ (FLOAT128_VECTOR_P (MODE) || OPAQUE_MODE_P (MODE))\n \n #define ALTIVEC_VECTOR_MODE(MODE)\t\t\t\t\t\\\n ((MODE) == V16QImode\t\t\t\t\t\t\t\\\n@@ -2280,6 +2280,7 @@ enum rs6000_builtin_type_index\n RS6000_BTI_const_str,\t\t /* pointer to const char * */\n RS6000_BTI_vector_pair,\t /* unsigned 256-bit types (vector pair). */\n RS6000_BTI_vector_quad,\t /* unsigned 512-bit types (vector quad). */\n+ RS6000_BTI_dm1024,\t\t /* unsigned 1,024-bit types (dmf). */\n RS6000_BTI_const_ptr_void, /* const pointer to void */\n RS6000_BTI_ptr_V16QI,\n RS6000_BTI_ptr_V1TI,\n@@ -2318,6 +2319,7 @@ enum rs6000_builtin_type_index\n RS6000_BTI_ptr_dfloat128,\n RS6000_BTI_ptr_vector_pair,\n RS6000_BTI_ptr_vector_quad,\n+ RS6000_BTI_ptr_dm1024,\n RS6000_BTI_ptr_long_long,\n RS6000_BTI_ptr_long_long_unsigned,\n RS6000_BTI_MAX\n@@ -2375,6 +2377,7 @@ enum rs6000_builtin_type_index\n #define const_str_type_node\t\t (rs6000_builtin_types[RS6000_BTI_const_str])\n #define vector_pair_type_node\t\t (rs6000_builtin_types[RS6000_BTI_vector_pair])\n #define vector_quad_type_node\t\t (rs6000_builtin_types[RS6000_BTI_vector_quad])\n+#define dm1024_type_node\t\t (rs6000_builtin_types[RS6000_BTI_dm1024])\n #define pcvoid_type_node\t\t (rs6000_builtin_types[RS6000_BTI_const_ptr_void])\n #define ptr_V16QI_type_node\t\t (rs6000_builtin_types[RS6000_BTI_ptr_V16QI])\n #define ptr_V1TI_type_node\t\t (rs6000_builtin_types[RS6000_BTI_ptr_V1TI])\n@@ -2413,6 +2416,7 @@ enum rs6000_builtin_type_index\n #define ptr_dfloat128_type_node\t\t (rs6000_builtin_types[RS6000_BTI_ptr_dfloat128])\n #define ptr_vector_pair_type_node\t (rs6000_builtin_types[RS6000_BTI_ptr_vector_pair])\n #define ptr_vector_quad_type_node\t (rs6000_builtin_types[RS6000_BTI_ptr_vector_quad])\n+#define ptr_dm1024_type_node\t\t (rs6000_builtin_types[RS6000_BTI_ptr_dm1024])\n #define ptr_long_long_integer_type_node\t (rs6000_builtin_types[RS6000_BTI_ptr_long_long])\n #define ptr_long_long_unsigned_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_long_unsigned])\n \n", "prefixes": [] }