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GET /api/patches/2230761/?format=api
{ "id": 2230761, "url": "http://patchwork.ozlabs.org/api/patches/2230761/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-29-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430002046.59739-29-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-04-30T00:20:27", "name": "[v3,28/47] target/arm: Implement BFCVTN for SVE", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "48628f3608ff0389c4cd18b4284298ae3067182d", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-29-richard.henderson@linaro.org/mbox/", "series": [ { "id": 502175, "url": "http://patchwork.ozlabs.org/api/series/502175/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175", "date": "2026-04-30T00:20:06", "name": "target/arm: Implement FEAT_FP8", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502175/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230761/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230761/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=rBoi4C98;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5Zl12Yp2z1yHv\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 10:27:57 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wIFAP-0007Xi-6A; Wed, 29 Apr 2026 20:22:09 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIFAD-00070d-A1\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:22:00 -0400", "from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIFAB-0006Ry-52\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:56 -0400", "by mail-pl1-x62c.google.com with SMTP id\n d9443c01a7336-2b9705613ddso2086175ad.1\n for <qemu-devel@nongnu.org>; Wed, 29 Apr 2026 17:21:54 -0700 (PDT)", "from stoup.. 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helo=mail-pl1-x62c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/helper-fp8-defs.h | 2 +\n target/arm/tcg/fp8_helper.c | 96 ++++++++++++++++++++++++++++++++\n target/arm/tcg/translate-sve.c | 3 +\n target/arm/tcg/sve.decode | 2 +\n 4 files changed, 103 insertions(+)", "diff": "diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex b5dc2b7064..bbc8d69e28 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -12,3 +12,5 @@ DEF_HELPER_FLAGS_4(advsimd_fcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sve2_fcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_fcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_fcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+\n+DEF_HELPER_FLAGS_4(sve2_bfcvtn_bh, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex 3e1ce24bd0..4270e13a8e 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -78,6 +78,15 @@ static FP8Context fp8_src_start(CPUARMState *env, uint32_t desc, int scale_mask)\n return fp8_start(env, desc, f8fmt, scale);\n }\n \n+static FP8Context fp8_dst_start(CPUARMState *env, uint32_t desc)\n+{\n+ uint64_t fpmr = env->vfp.fpmr;\n+ FPMRType f8fmt = FIELD_EX64(fpmr, FPMR, F8D);\n+ int scale = FIELD_SEX64(fpmr, FPMR, NSCALE);\n+\n+ return fp8_start(env, desc, f8fmt, scale);\n+}\n+\n /*\n * Invalid input format is treated as snan, then the conversion operation\n * converts to default nan and raises invalid.\n@@ -102,6 +111,13 @@ static void float16_invalid_input(float16 *d, size_t nelem, float_status *s)\n float_raise(float_flag_invalid | float_flag_invalid_snan, s);\n }\n \n+/* Invalid output format writes -1 and raises invalid. */\n+static void float8_invalid_output(uint8_t *d, size_t nelem, float_status *s)\n+{\n+ memset(d, -1, nelem);\n+ float_raise(float_flag_invalid, s);\n+}\n+\n static bfloat16 fcvt_fp8e4m3_to_b16(float8_e4m3 x, int scale, float_status *s)\n {\n FloatParts64 p = float8_e4m3_unpack_canonical(x, s);\n@@ -130,6 +146,47 @@ static float16 fcvt_fp8e5m2_to_f16(float8_e5m2 x, int scale, float_status *s)\n return float16_round_pack_canonical(&p, s);\n }\n \n+static float8_e4m3 fcvt_b16_to_fp8e4m3(bfloat16 x, int scale,\n+ bool saturate, float_status *s)\n+{\n+ FloatParts64 p = bfloat16_unpack_canonical(x, s);\n+\n+ p = parts64_scalbn(&p, scale, s);\n+ /*\n+ * Saturating Inf -> Max handled in uncanon_e4m3_overflow\n+ * because there is no infinity encoding.\n+ */\n+ return float8_e4m3_round_pack_canonical(&p, s, saturate);\n+}\n+\n+/*\n+ * Because e5m2 has an infinity encoding, we need to handle\n+ * conversion of Inf -> Max manually. This will be converted\n+ * to the actual maximum value during rounding.\n+ */\n+static void scalbn_to_fp8e5m2(FloatParts64 *p, int scale,\n+ bool saturate, float_status *s)\n+{\n+ if (unlikely(p->cls == float_class_inf)) {\n+ if (saturate) {\n+ p->cls = float_class_normal;\n+ p->exp = INT_MAX;\n+ p->frac = -1;\n+ }\n+ } else {\n+ *p = parts64_scalbn(p, scale, s);\n+ }\n+}\n+\n+static float8_e5m2 fcvt_b16_to_fp8e5m2(bfloat16 x, int scale,\n+ bool saturate, float_status *s)\n+{\n+ FloatParts64 p = bfloat16_unpack_canonical(x, s);\n+\n+ scalbn_to_fp8e5m2(&p, scale, saturate, s);\n+ return float8_e5m2_round_pack_canonical(&p, s, saturate);\n+}\n+\n void HELPER(advsimd_bfcvtl)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n {\n FP8Context ctx = fp8_src_start(env, desc, 0x3f);\n@@ -406,3 +463,42 @@ void HELPER(sme2_fcvtl_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n \n fp8_finish(env, &ctx);\n }\n+\n+void HELPER(sve2_bfcvtn_bh)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_dst_start(env, desc);\n+ uint16_t *n0 = vn;\n+ uint16_t *n1 = vn + sizeof(ARMVectorReg);\n+ uint8_t *d = vd;\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+ bool osc = FIELD_EX64(env->vfp.fpmr, FPMR, OSC);\n+\n+ switch (ctx.f8fmt) {\n+ case OFP8_E5M2:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ bfloat16 e0 = n0[H2(i)];\n+ bfloat16 e1 = n1[H2(i)];\n+ d[H1(2 * i + 0)] =\n+ fcvt_b16_to_fp8e5m2(e0, ctx.scale, osc, &ctx.stat);\n+ d[H1(2 * i + 1)] =\n+ fcvt_b16_to_fp8e5m2(e1, ctx.scale, osc, &ctx.stat);\n+ }\n+ break;\n+ case OFP8_E4M3:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ bfloat16 e0 = n0[H2(i)];\n+ bfloat16 e1 = n1[H2(i)];\n+ d[H1(2 * i + 0)] =\n+ fcvt_b16_to_fp8e4m3(e0, ctx.scale, osc, &ctx.stat);\n+ d[H1(2 * i + 1)] =\n+ fcvt_b16_to_fp8e4m3(e1, ctx.scale, osc, &ctx.stat);\n+ }\n+ break;\n+ default:\n+ float8_invalid_output(d, oprsz, &ctx.stat);\n+ break;\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\ndiff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c\nindex 5200f3d034..7276d9c44a 100644\n--- a/target/arm/tcg/translate-sve.c\n+++ b/target/arm/tcg/translate-sve.c\n@@ -4099,6 +4099,9 @@ TRANS_FEAT(BF1CVTLT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n TRANS_FEAT(BF2CVTLT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n gen_helper_sve2_bfcvt, true, true)\n \n+TRANS_FEAT(BFCVTN, aa64_sme2_or_sve2_f8cvt, do_f8cvt,\n+ a, gen_helper_sve2_bfcvtn_bh, false, false)\n+\n /*\n *** SVE Floating Point Compare with Zero Group\n */\ndiff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode\nindex ca110f4bc1..b6ef8ed8de 100644\n--- a/target/arm/tcg/sve.decode\n+++ b/target/arm/tcg/sve.decode\n@@ -1101,6 +1101,8 @@ BF2CVT 01100101 00 001 000 001111 ..... ..... @rd_rn_e0\n BF1CVTLT 01100101 00 001 001 001110 ..... ..... @rd_rn_e0\n BF2CVTLT 01100101 00 001 001 001111 ..... ..... @rd_rn_e0\n \n+BFCVTN 01100101 00 001 010 001110 ....0 ..... @rd_rnx2 esz=1\n+\n ### SVE FP Compare with Zero Group\n \n FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn\n", "prefixes": [ "v3", "28/47" ] }