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GET /api/patches/2230744/?format=api
{ "id": 2230744, "url": "http://patchwork.ozlabs.org/api/patches/2230744/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-31-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430002046.59739-31-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-04-30T00:20:29", "name": "[v3,30/47] target/arm: Implement FCVTN, FCVTN2 (32- to 8-bit fp) for AdvSIMD", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d16f4f6d6f93aa62b163c4ce736113264eeda2c9", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-31-richard.henderson@linaro.org/mbox/", "series": [ { "id": 502175, "url": "http://patchwork.ozlabs.org/api/series/502175/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175", "date": "2026-04-30T00:20:06", "name": "target/arm: Implement FEAT_FP8", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502175/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230744/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230744/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=CZMcM1P9;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5Zhk6phrz1yHv\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 10:25:58 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wIFAN-0007Tg-6J; Wed, 29 Apr 2026 20:22:07 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIFAI-00079t-CM\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:22:02 -0400", "from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIFAF-0006U6-Pw\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:22:02 -0400", "by mail-pf1-x434.google.com with SMTP id\n d2e1a72fcca58-82f0884bcfaso257309b3a.1\n for <qemu-devel@nongnu.org>; Wed, 29 Apr 2026 17:21:58 -0700 (PDT)", "from stoup.. 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helo=mail-pf1-x434.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/helper-fp8-defs.h | 2 ++\n target/arm/tcg/fp8_helper.c | 60 ++++++++++++++++++++++++++++++++\n target/arm/tcg/translate-a64.c | 16 +++++++++\n target/arm/tcg/a64.decode | 1 +\n 4 files changed, 79 insertions(+)", "diff": "diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 6530d1a6da..023a49e12f 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -16,3 +16,5 @@ DEF_HELPER_FLAGS_4(sme2_fcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sve2_bfcvtn_bh, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \n DEF_HELPER_FLAGS_5(gvec_fcvt_bh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n+\n+DEF_HELPER_FLAGS_5(advsimd_fcvt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex 9658eeac8d..facbf4f6c6 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -205,6 +205,24 @@ static float8_e5m2 fcvt_f16_to_fp8e5m2(float16 x, int scale,\n return float8_e5m2_round_pack_canonical(&p, s, saturate);\n }\n \n+static float8_e4m3 fcvt_f32_to_fp8e4m3(float32 x, int scale,\n+ bool saturate, float_status *s)\n+{\n+ FloatParts64 p = float32_unpack_canonical(x, s);\n+\n+ p = parts64_scalbn(&p, scale, s);\n+ return float8_e4m3_round_pack_canonical(&p, s, saturate);\n+}\n+\n+static float8_e5m2 fcvt_f32_to_fp8e5m2(float32 x, int scale,\n+ bool saturate, float_status *s)\n+{\n+ FloatParts64 p = float32_unpack_canonical(x, s);\n+\n+ scalbn_to_fp8e5m2(&p, scale, saturate, s);\n+ return float8_e5m2_round_pack_canonical(&p, s, saturate);\n+}\n+\n void HELPER(advsimd_bfcvtl)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n {\n FP8Context ctx = fp8_src_start(env, desc, 0x3f);\n@@ -568,3 +586,45 @@ void HELPER(gvec_fcvt_bh)(void *vd, void *vn, void *vm,\n fp8_finish(env, &ctx);\n clear_tail(vd, oprsz, simd_maxsz(desc));\n }\n+\n+void HELPER(advsimd_fcvt_bs)(void *vd, void *vn, void *vm,\n+ CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_dst_start(env, desc);\n+ uint32_t *n = vn, *m = vm, scratch[4];\n+ uint8_t *d = vd + 8 * ctx.high;\n+ bool osc = FIELD_EX64(env->vfp.fpmr, FPMR, OSC);\n+\n+ if (vd == vm) {\n+ m = memcpy(scratch, vm, 16);\n+ }\n+\n+ switch (ctx.f8fmt) {\n+ case OFP8_E5M2:\n+ for (size_t i = 0; i < 4; ++i) {\n+ float32 e = n[H4(i)];\n+ d[H1(i + 0)] = fcvt_f32_to_fp8e5m2(e, ctx.scale, osc, &ctx.stat);\n+ }\n+ for (size_t i = 0; i < 4; ++i) {\n+ float32 e = m[H4(i)];\n+ d[H1(i + 4)] = fcvt_f32_to_fp8e5m2(e, ctx.scale, osc, &ctx.stat);\n+ }\n+ break;\n+ case OFP8_E4M3:\n+ for (size_t i = 0; i < 4; ++i) {\n+ float32 e = n[H4(i)];\n+ d[H1(i + 0)] = fcvt_f32_to_fp8e4m3(e, ctx.scale, osc, &ctx.stat);\n+ }\n+ for (size_t i = 0; i < 4; ++i) {\n+ float32 e = m[H4(i)];\n+ d[H1(i + 4)] = fcvt_f32_to_fp8e4m3(e, ctx.scale, osc, &ctx.stat);\n+ }\n+ break;\n+ default:\n+ float8_invalid_output(d, 8, &ctx.stat);\n+ break;\n+ }\n+\n+ fp8_finish(env, &ctx);\n+ clear_tail(vd, ctx.high ? 16 : 8, simd_maxsz(desc));\n+}\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 0927eb6516..3c784afc99 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -6537,6 +6537,22 @@ static bool trans_FCVTN_bh(DisasContext *s, arg_qrrr_e *a)\n return true;\n }\n \n+static bool trans_FCVTN_bs(DisasContext *s, arg_qrrr_e *a)\n+{\n+ if (!dc_isar_feature(aa64_f8cvt, s)) {\n+ return false;\n+ }\n+ if (fpmr_access_check(s) && fp_access_check(s)) {\n+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),\n+ vec_full_reg_offset(s, a->rn),\n+ vec_full_reg_offset(s, a->rm),\n+ tcg_env, 16, vec_full_reg_size(s),\n+ (a->q << 1) | FPST_A64 << 2,\n+ gen_helper_advsimd_fcvt_bs);\n+ }\n+ return true;\n+}\n+\n static bool do_fmlal(DisasContext *s, arg_qrrr_e *a, bool is_s, bool is_2)\n {\n if (fp_access_check(s)) {\ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex 71456d44e1..a9cf259b9b 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -1202,6 +1202,7 @@ FSCALE 0.10 1110 110 ..... 00111 1 ..... ..... @qrrr_h\n FSCALE 0.10 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd\n \n FCVTN_bh 0.00 1110 010 ..... 11110 1 ..... ..... @qrrr_h\n+FCVTN_bs 0.00 1110 000 ..... 11110 1 ..... ..... @qrrr_h\n \n ### Advanced SIMD scalar x indexed element\n \n", "prefixes": [ "v3", "30/47" ] }