Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2230742/?format=api
{ "id": 2230742, "url": "http://patchwork.ozlabs.org/api/patches/2230742/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-9-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430002046.59739-9-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-04-30T00:20:07", "name": "[v3,08/47] target/arm: Introduce FPMR", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2cc6533c169c1b1f36aa58549a030c72eb0f9cc8", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-9-richard.henderson@linaro.org/mbox/", "series": [ { "id": 502175, "url": "http://patchwork.ozlabs.org/api/series/502175/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175", "date": "2026-04-30T00:20:06", "name": "target/arm: Implement FEAT_FP8", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502175/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230742/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230742/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Tu7VGxMX;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5Zhd2bvQz1yHv\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 10:25:53 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wIF9q-0006YM-9Y; Wed, 29 Apr 2026 20:21:35 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIF9V-0006Nc-3F\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:16 -0400", "from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIF9T-0006G4-ED\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:12 -0400", "by mail-pf1-x430.google.com with SMTP id\n d2e1a72fcca58-83177129e28so162057b3a.1\n for <qemu-devel@nongnu.org>; Wed, 29 Apr 2026 17:21:11 -0700 (PDT)", "from stoup.. ([180.233.125.15]) by smtp.gmail.com with ESMTPSA id\n d2e1a72fcca58-834ed5cd3b8sm3461727b3a.16.2026.04.29.17.21.08\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 29 Apr 2026 17:21:09 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777508470; x=1778113270; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=73otMSm/BuymaPP3YE3sIV7Wl7PcxvDt8khsJ+zToKU=;\n b=Tu7VGxMXw83S2Iu4tUFkFXu9MorQ7OxPXFZf2LUfKgtN6kgLoZj8TnBda880tdDsv3\n EksPOz3Bv/le7XNWm4Angpi/pmxs1VheF70T6jafruXV3xlzcRc5htR6utF4m8JnRhWS\n mUPQwEcWUdoX7axPZ7Nl4/bgIe/nZ1DAmWClDMO2Qc5DYKPSP/dfQYAdvLhaaqsyYT90\n 5hXnnYZjHvvxtcpGoUBJ+hBu9mfUEI0Hc34upzIgrodVahCRisV6vWVNbo4ggGbDyNBa\n bfoa6N7fUlsjwLT+TrnFQmtZfmiCCkf9CC39NYn8wN6jsft+fFA3QwFXnxQrKvZFR0J7\n afgg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777508470; x=1778113270;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=73otMSm/BuymaPP3YE3sIV7Wl7PcxvDt8khsJ+zToKU=;\n b=hR3GGgVa05YQvTgcuJ1U8kBQ+5SImny4P3H7QKTb3vvWsc64LWWvlL+ZQhc96pIhK7\n TgKnXtAb5lFxc5ZkoRDhZZPaHyxIXOmunLuAH5ourYEfH0iXrYB+7wOvNQak1ZzsT8yt\n NvF+yRulaZSl5Eenw79/+9ax+lCvM6UWGc2gn3BIJYLnMJ8cSgQQJEVf+j4xaJa5w4aL\n jDG1Hij4KWar2apvC/bX2xaPJNbPEZhNdfQjcfO+Wl1PNAi6waJWl9h6TzVQq/cGobGy\n v4ifnR+Lk7PfWx9rEouqK2yuqmYGj/tXc5o3C16vFcI+TiSnY65W1v4gLKXdmVQQSoZ2\n xpug==", "X-Gm-Message-State": "AOJu0YxV/DVWrfvDxfTdqRuKj3NvWgUjToql7k0QAxeTyScnMhuE69rW\n UjmWSNKPg/0LDDQ/2tO3hZidnhyscVX+StF1TwvuwSyAyS68bS8IxEOWpav/uvqRlSGAX2KSvck\n mU+XDfO4=", "X-Gm-Gg": "AeBDies87KRTcvV8zOdd9yf5GyIyX+y4tAZW+R32NgTulZxxON4qzHJ1pV/QjgYlNwQ\n 4yagZ52RMp3RTXgGE9Dj86TPZsGcRcVJHKsCLfVJpfnLkgRGeUX4eOYGTTMDacVV5Y7uwkuNBI8\n 9Br6lh/0eervmfg5Vsia4iR3OG8g4wSdIiDFZBLITtd/EPHdZ8eXWlpUPFPWz5+SJYaqvleQADr\n WIhwXyia9IZ6d4YewCKsMS+F5dl9B59ylyMlIydcD6Duqha4rcubUdd0/Rc25ndZdQzo8MLnRA7\n rum1fTN+/MPbgkIUQ32KdLmlGtUKgV2a9S+gAjmN80YqZvEjMEF7qgmRZpID1V/p+sS4TO2edYc\n 7bg7ucfuDzjJjqfM/4WuACvhr0WmeW985h1iEAvyzyJcNSLR1M1ORJS86ebT1o/hx3LVikgwqPJ\n iQtI4yBG68QmNnwtRDuxYxnrOF+TH41Br6niSTt67BujzNjJUCQxU=", "X-Received": "by 2002:a05:6a00:a256:b0:82a:6de8:fa50 with SMTP id\n d2e1a72fcca58-834fdb87d67mr842175b3a.18.1777508469869;\n Wed, 29 Apr 2026 17:21:09 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-arm@nongnu.org", "Subject": "[PATCH v3 08/47] target/arm: Introduce FPMR", "Date": "Thu, 30 Apr 2026 10:20:07 +1000", "Message-ID": "<20260430002046.59739-9-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260430002046.59739-1-richard.henderson@linaro.org>", "References": "<20260430002046.59739-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::430;\n envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Introduce the special register FPMR and its fields.\nMigrate it when present.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpregs.h | 5 +++++\n target/arm/cpu-features.h | 5 +++++\n target/arm/cpu.h | 1 +\n target/arm/internals.h | 9 +++++++++\n target/arm/helper.c | 12 +++++++++++-\n target/arm/machine.c | 20 ++++++++++++++++++++\n 6 files changed, 51 insertions(+), 1 deletion(-)", "diff": "diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h\nindex f5ec7484c1..391c0e322b 100644\n--- a/target/arm/cpregs.h\n+++ b/target/arm/cpregs.h\n@@ -149,6 +149,11 @@ enum {\n * should not trap to EL2 when HCR_EL2.NV is set.\n */\n ARM_CP_NV_NO_TRAP = 1 << 22,\n+ /*\n+ * Flag: Access check for this sysreg is constrained by the\n+ * ARM pseudocode function CheckFPMREnabled().\n+ */\n+ ARM_CP_FPMR = 1 << 23,\n };\n \n /*\ndiff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 5b1c0cf76d..35e281699c 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1178,6 +1178,11 @@ static inline bool isar_feature_aa64_gcs(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64PFR1, GCS) != 0;\n }\n \n+static inline bool isar_feature_aa64_fpmr(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64PFR2, FPMR) != 0;\n+}\n+\n static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)\n {\n return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >= 1;\ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex da1b7fde1d..1a55275e80 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -692,6 +692,7 @@ typedef struct CPUArchState {\n */\n uint64_t fpsr;\n uint64_t fpcr;\n+ uint64_t fpmr;\n \n uint32_t xregs[16];\n \ndiff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 6376ae1ca3..08024943c3 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -292,6 +292,15 @@ FIELD(CNTHCTL, EVNTIS, 17, 1)\n FIELD(CNTHCTL, CNTVMASK, 18, 1)\n FIELD(CNTHCTL, CNTPMASK, 19, 1)\n \n+FIELD(FPMR, F8S1, 0, 3)\n+FIELD(FPMR, F8S2, 3, 3)\n+FIELD(FPMR, F8D, 6, 3)\n+FIELD(FPMR, OSM, 14, 1)\n+FIELD(FPMR, OSC, 15, 1)\n+FIELD(FPMR, LSCALE, 16, 7)\n+FIELD(FPMR, NSCALE, 24, 8)\n+FIELD(FPMR, LSCALE2, 32, 6)\n+\n /* We use a few fake FSR values for internal purposes in M profile.\n * M profile cores don't have A/R format FSRs, but currently our\n * get_phys_addr() code assumes A/R profile and reports failures via\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 66813bb298..304db1a479 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6209,6 +6209,14 @@ static const ARMCPRegInfo aie_reginfo[] = {\n .type = ARM_CP_CONST, .resetvalue = 0 },\n };\n \n+static const ARMCPRegInfo fpmr_reginfo[] = {\n+ { .name = \"FPMR\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 4, .opc2 = 2,\n+ .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_FPMR,\n+ .fieldoffset = offsetof(CPUARMState, vfp.fpmr),\n+ }\n+};\n+\n void register_cp_regs_for_features(ARMCPU *cpu)\n {\n /* Register all the coprocessor registers based on feature bits */\n@@ -7481,10 +7489,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)\n define_arm_cp_regs(cpu, mec_mte_reginfo);\n }\n }\n-\n if (cpu_isar_feature(aa64_aie, cpu)) {\n define_arm_cp_regs(cpu, aie_reginfo);\n }\n+ if (cpu_isar_feature(aa64_fpmr, cpu)) {\n+ define_arm_cp_regs(cpu, fpmr_reginfo);\n+ }\n \n if (cpu_isar_feature(any_predinv, cpu)) {\n define_arm_cp_regs(cpu, predinv_reginfo);\ndiff --git a/target/arm/machine.c b/target/arm/machine.c\nindex 8dc766d322..58f8dfd53c 100644\n--- a/target/arm/machine.c\n+++ b/target/arm/machine.c\n@@ -960,6 +960,25 @@ static const VMStateDescription vmstate_syndrome64 = {\n },\n };\n \n+static bool fpmr_needed(void *opaque)\n+{\n+ ARMCPU *cpu = opaque;\n+\n+ return arm_feature(&cpu->env, ARM_FEATURE_AARCH64)\n+ && cpu_isar_feature(aa64_fpmr, cpu);\n+}\n+\n+static const VMStateDescription vmstate_fpmr = {\n+ .name = \"cpu/fpmr\",\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .needed = fpmr_needed,\n+ .fields = (const VMStateField[]) {\n+ VMSTATE_UINT64(env.vfp.fpmr, ARMCPU),\n+ VMSTATE_END_OF_LIST()\n+ },\n+};\n+\n static int cpu_pre_save(void *opaque)\n {\n ARMCPU *cpu = opaque;\n@@ -1323,6 +1342,7 @@ const VMStateDescription vmstate_arm_cpu = {\n &vmstate_syndrome64,\n &vmstate_pstate64,\n &vmstate_event,\n+ &vmstate_fpmr,\n NULL\n }\n };\n", "prefixes": [ "v3", "08/47" ] }