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GET /api/patches/2230740/?format=api
{ "id": 2230740, "url": "http://patchwork.ozlabs.org/api/patches/2230740/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-37-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430002046.59739-37-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-04-30T00:20:35", "name": "[v3,36/47] target/arm: Implement LUTI2, LUTI4 for SVE", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "66b7f279720e6e6915fb4003720dd4fb2d413a8d", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-37-richard.henderson@linaro.org/mbox/", "series": [ { "id": 502175, "url": "http://patchwork.ozlabs.org/api/series/502175/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175", "date": "2026-04-30T00:20:06", "name": "target/arm: Implement FEAT_FP8", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502175/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230740/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230740/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=BCYBOEQP;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5ZgV1VC4z1yHZ\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 10:24:54 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wIFAY-00080E-Cs; Wed, 29 Apr 2026 20:22:18 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIFAU-0007nN-9N\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:22:14 -0400", "from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIFAS-0006bU-2u\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:22:13 -0400", "by mail-pf1-x42a.google.com with SMTP id\n d2e1a72fcca58-82f943870baso170802b3a.1\n for <qemu-devel@nongnu.org>; Wed, 29 Apr 2026 17:22:11 -0700 (PDT)", "from stoup.. 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"<20260430002046.59739-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::42a;\n envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu-features.h | 6 +++\n target/arm/tcg/translate.h | 8 ++++\n target/arm/tcg/translate-a64.c | 1 +\n target/arm/tcg/translate-sve.c | 68 ++++++++++++++++++++++++++++++++++\n target/arm/tcg/sve.decode | 11 +++++-\n 5 files changed, 93 insertions(+), 1 deletion(-)", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 334ff480bc..03fd860406 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1635,6 +1635,12 @@ isar_feature_aa64_sme2_or_sve2_f8cvt(const ARMISARegisters *id)\n return isar_feature_aa64_sme2_or_sve2(id) && isar_feature_aa64_f8cvt(id);\n }\n \n+static inline bool\n+isar_feature_aa64_sme2_or_sve2_lut(const ARMISARegisters *id)\n+{\n+ return isar_feature_aa64_sme2_or_sve2(id) && isar_feature_aa64_lut(id);\n+}\n+\n /*\n * Feature tests for \"does this exist in either 32-bit or 64-bit?\"\n */\ndiff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h\nindex 1648c2c96f..b703e75b70 100644\n--- a/target/arm/tcg/translate.h\n+++ b/target/arm/tcg/translate.h\n@@ -90,6 +90,7 @@ typedef struct DisasContext {\n int vl; /* current vector length in bytes */\n int svl; /* current streaming vector length in bytes */\n int max_svl; /* maximum implemented streaming vector length */\n+ int max_any_vl; /* maximum implemented vector length */\n bool vfp_enabled; /* FP enabled via FPSCR.EN */\n int vec_len;\n int vec_stride;\n@@ -874,4 +875,11 @@ static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst)\n return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \\\n }\n \n+#define TRANS_FEAT_SME1_NONSTREAMING(NAME, FEAT, FUNC, ...) \\\n+ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \\\n+ { \\\n+ s->is_nonstreaming = !dc_isar_feature(aa64_sme2, s); \\\n+ return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \\\n+ }\n+\n #endif /* TARGET_ARM_TRANSLATE_H */\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 508d8e377b..ee71c63116 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -10820,6 +10820,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,\n dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;\n dc->svl = (EX_TBFLAG_A64(tb_flags, SVL) + 1) * 16;\n dc->max_svl = arm_cpu->sme_max_vq * 16;\n+ dc->max_any_vl = MAX(dc->max_svl, arm_cpu->sve_max_vq * 16);\n dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE);\n dc->bt = EX_TBFLAG_A64(tb_flags, BT);\n dc->btype = EX_TBFLAG_A64(tb_flags, BTYPE);\ndiff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c\nindex 13f7ab01af..ea0d66178e 100644\n--- a/target/arm/tcg/translate-sve.c\n+++ b/target/arm/tcg/translate-sve.c\n@@ -8268,3 +8268,71 @@ TRANS_FEAT(LD1_zcrr_stride, aa64_sme2, gen_ldst_zcrr_c, a, false, true)\n TRANS_FEAT(LD1_zcri_stride, aa64_sme2, gen_ldst_zcri_c, a, false, true)\n TRANS_FEAT(ST1_zcrr_stride, aa64_sme2, gen_ldst_zcrr_c, a, true, true)\n TRANS_FEAT(ST1_zcri_stride, aa64_sme2, gen_ldst_zcri_c, a, true, true)\n+\n+TRANS_FEAT_SME1_NONSTREAMING(LUTI2_1b, aa64_sme2_or_sve2_lut,\n+ gen_gvec_ool_zzz, gen_helper_gvec_luti2_b,\n+ a->rd, a->rn, a->rm, a->index)\n+TRANS_FEAT_SME1_NONSTREAMING(LUTI2_1h, aa64_sme2_or_sve2_lut,\n+ gen_gvec_ool_zzz, gen_helper_gvec_luti2_h,\n+ a->rd, a->rn, a->rm, a->index)\n+TRANS_FEAT_SME1_NONSTREAMING(LUTI4_1b, aa64_sme2_or_sve2_lut,\n+ gen_gvec_ool_zzz, gen_helper_gvec_luti4_b,\n+ a->rd, a->rn, a->rm, a->index)\n+\n+static bool trans_LUTI4_1h(DisasContext *s, arg_LUTI4_1h *a)\n+{\n+ if (!dc_isar_feature(aa64_sme2_or_sve2_lut, s)) {\n+ return false;\n+ }\n+ s->is_nonstreaming = !dc_isar_feature(aa64_sme2, s);\n+\n+ /*\n+ * The MaxImplementedAnyVL check happens in the decode pseudocode,\n+ * before the Check*SVEEnabled check in the operation pseudocode.\n+ */\n+ if (s->max_any_vl < 32) {\n+ unallocated_encoding(s);\n+ } else if (sve_access_check(s)) {\n+ unsigned vsz = vec_full_reg_size(s);\n+\n+ /* Then there's a second check against CurrentVL. */\n+ if (vsz < 32) {\n+ unallocated_encoding(s);\n+ } else {\n+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),\n+ vec_full_reg_offset(s, a->rn),\n+ vec_full_reg_offset(s, a->rm),\n+ vsz, vsz, a->index,\n+ gen_helper_gvec_luti4_h);\n+ }\n+ }\n+ return true;\n+}\n+\n+static bool trans_LUTI4_2h(DisasContext *s, arg_LUTI4_2h *a)\n+{\n+ if (!dc_isar_feature(aa64_sme2_or_sve2_lut, s)) {\n+ return false;\n+ }\n+ s->is_nonstreaming = !dc_isar_feature(aa64_sme2, s);\n+\n+ if (sve_access_check(s)) {\n+ unsigned vsz = vec_full_reg_size(s);\n+ /*\n+ * (Ab)use preg_tmp to merge two disjoint 128-bit quantities\n+ * into a sequential 256-bit table.\n+ */\n+ QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, vfp.preg_tmp) < 32);\n+ unsigned tmp_ofs = offsetof(CPUARMState, vfp.preg_tmp);\n+ unsigned rn0_ofs = vec_full_reg_offset(s, a->rn);\n+ unsigned rn1_ofs = vec_full_reg_offset(s, (a->rn + 1) % 32);\n+\n+ tcg_gen_gvec_mov(MO_64, tmp_ofs, rn0_ofs, 16, 16);\n+ tcg_gen_gvec_mov(MO_64, tmp_ofs + 16, rn1_ofs, 16, 16);\n+\n+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), tmp_ofs,\n+ vec_full_reg_offset(s, a->rm),\n+ vsz, vsz, a->index, gen_helper_gvec_luti4_h);\n+ }\n+ return true;\n+}\ndiff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode\nindex 7fce189b36..a11ea08eb3 100644\n--- a/target/arm/tcg/sve.decode\n+++ b/target/arm/tcg/sve.decode\n@@ -31,6 +31,7 @@\n %dtype_23_13 23:2 13:2\n %index3_22_19 22:1 19:2\n %index3_22_17 22:1 17:2\n+%index3_22_12 22:2 12:1\n %index3_19_11 19:2 11:1\n %index2_20_11 20:1 11:1\n \n@@ -1737,11 +1738,19 @@ RSUBHNT 01000101 .. 1 ..... 011 111 ..... ..... @rd_rn_rm\n MATCH 01000101 .. 1 ..... 100 ... ..... 0 .... @pd_pg_rn_rm\n NMATCH 01000101 .. 1 ..... 100 ... ..... 1 .... @pd_pg_rn_rm\n \n-### SVE2 Histogram Computation\n+### SVE2 Histogram Computation and Lookup Table\n \n HISTCNT 01000101 .. 1 ..... 110 ... ..... ..... @rd_pg_rn_rm\n HISTSEG 01000101 .. 1 ..... 101 000 ..... ..... @rd_rn_rm\n \n+LUTI2_1b 01000101 index:2 1 rm:5 101100 rn:5 rd:5 &rrx_esz esz=0\n+LUTI2_1h 01000101 .. 1 rm:5 101.10 rn:5 rd:5 \\\n+ &rrx_esz esz=1 index=%index3_22_12\n+\n+LUTI4_1b 01000101 index:1 11 rm:5 101001 rn:5 rd:5 &rrx_esz esz=0\n+LUTI4_1h 01000101 index:2 1 rm:5 101111 rn:5 rd:5 &rrx_esz esz=1\n+LUTI4_2h 01000101 index:2 1 rm:5 101101 rn:5 rd:5 &rrx_esz esz=1\n+\n ## SVE2 floating-point pairwise operations\n \n FADDP 01100100 .. 010 00 0 100 ... ..... ..... @rdn_pg_rm\n", "prefixes": [ "v3", "36/47" ] }