Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2230738/?format=api
{ "id": 2230738, "url": "http://patchwork.ozlabs.org/api/patches/2230738/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-19-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430002046.59739-19-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-04-30T00:20:17", "name": "[v3,18/47] target/arm: Implement FSCALE for SME", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e48206ef67012bbffe9ae5a7e92a138e2a089988", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-19-richard.henderson@linaro.org/mbox/", "series": [ { "id": 502175, "url": "http://patchwork.ozlabs.org/api/series/502175/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175", "date": "2026-04-30T00:20:06", "name": "target/arm: Implement FEAT_FP8", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502175/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230738/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230738/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=uJdcHmPu;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5Zft1Yj7z1yHZ\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 10:24:20 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wIF9z-0006on-1h; Wed, 29 Apr 2026 20:21:43 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIF9q-0006c6-LH\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:35 -0400", "from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIF9o-0006Kp-VW\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:34 -0400", "by mail-pf1-x430.google.com with SMTP id\n d2e1a72fcca58-83177129e28so162111b3a.1\n for <qemu-devel@nongnu.org>; Wed, 29 Apr 2026 17:21:32 -0700 (PDT)", "from stoup.. ([180.233.125.15]) by smtp.gmail.com with ESMTPSA id\n d2e1a72fcca58-834ed5cd3b8sm3461727b3a.16.2026.04.29.17.21.29\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 29 Apr 2026 17:21:31 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777508492; x=1778113292; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=Y4y3ds3PSya04tloOheNtG2Ax9QruENgFVm/k1Dpe8E=;\n b=uJdcHmPu57QnSl+tMFX6VtmXVpxlgx2VUMh6UapB9OvvU+vsiI2wi2uYcoxsRx2+ib\n HsNR4gedU2bfkSz+ScnRHJlFvRqPwRv+0ji0TI0bCTofh+Ot4Jlw7/ak+FHH0FA1AXdB\n /nidrPfMkieoRl2P0PYzYFuTZVX6tSpiZzCyvrmKMQ2ypqaSGASOYhPwjU4t3mOFmF/m\n z2zKJw3b5AmZJkao6sUX8RlirymGEhqUGHY2ZcSa+w3gZVRd1Em//2tcZtw6bv+17/Mu\n jZGZx6psw4NyrEWjlgx9mgDw/GTTRwPJKrL405KBfScBLwkLKmfoOfvpoexZQbXhLT1Y\n VAsQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777508492; x=1778113292;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=Y4y3ds3PSya04tloOheNtG2Ax9QruENgFVm/k1Dpe8E=;\n b=SDxvra+F0Zn5G263fesXQJ4pnzPk2MNLfpmRsLcWe68LeUwt0PV5hMFCSxjpd5aBkN\n r81FNVBWBK6Le1qYNWJXHxoSRkWDQal+Iy0gEDF69Lhk4FnFbG83ao7Wmi+e48blvNZH\n oiNmXl2TZBzCajED/+IkAv0EuYqkDnoyiQackFigtPmJV/A8sfDx/8fA1vqWjovdjtIw\n cWvhJWifMGmKwFBfw5uwvtufkan9awQGvYG2PhnrRAyt7BdGnUp1ZTQAgNQH4TGF1vHf\n vOD3pXEOZ+7yp1OQIHklQg9mjx7UPRjsmx0gbBkJ5JJDwA62u1DZO71XiWCOKRpMn3Y8\n uFwQ==", "X-Gm-Message-State": "AOJu0Yxl/i9dJaSBM3QL83Ch9nYxfgvb5u4r7O1fuJiAxPIl4Z4e4qbr\n KBXXY+P2CqBdQ/6kZ78n0VzdfnMZfQuxtZhRnZcyK7gNbAkUIAQtbV7fJgsbrD4fc/LhM36VgJc\n cCdCRJIg=", "X-Gm-Gg": "AeBDievUbe8Eb3mriKnNULNWQqjrKnxrT83YV8VCUAM9AgeGHhhYnJfql39S4lp6yND\n kHUpdaOOg6YHTLtXBLcoIuNsV33xUCpV3teEmWs8qvHsLQs1hfv0PuG4AZVdBHHS26TgWhGk2iB\n JWCLCqZMeaYQfreK/B7gN8DCPcjZ2YWJiUo/pkPw+WKsezf5SacDokyQdBzZbz38mDZaFkLl7U5\n S1nxMW39D8WQeJugCGnnLB16nskqOlGS8YQOlnFsSkHshGWYfgVdbDZrBLufYSLHuDjjrJrTaAb\n eIMg6/+CrFORieae9v6oq3sGSka4HkvWLKgYwjwKcxIT9UgMXUewUTE/7kWnT0w2HgCpEoEDI/V\n ZmYG/d7qVW27ueWhw8bYw2ye1m3iA6be1Q2QmdDTJqrSqxvsFpprxX20iZKawB0sGDhYjvkQqIM\n Xdpuu8FaDP9eWAoFVZXee8sCxgRTbOL1hmRtr776wI", "X-Received": "by 2002:a05:6a00:290e:b0:82f:8696:5a75 with SMTP id\n d2e1a72fcca58-834fdc5bf05mr823467b3a.28.1777508491535;\n Wed, 29 Apr 2026 17:21:31 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-arm@nongnu.org", "Subject": "[PATCH v3 18/47] target/arm: Implement FSCALE for SME", "Date": "Thu, 30 Apr 2026 10:20:17 +1000", "Message-ID": "<20260430002046.59739-19-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260430002046.59739-1-richard.henderson@linaro.org>", "References": "<20260430002046.59739-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::430;\n envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/tcg/translate-sme.c | 15 +++++++++++++--\n target/arm/tcg/sme.decode | 6 ++++++\n 3 files changed, 24 insertions(+), 2 deletions(-)", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 590a7f6cf7..104e36b3ae 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1608,6 +1608,11 @@ static inline bool isar_feature_aa64_sme2_faminmax(const ARMISARegisters *id)\n return isar_feature_aa64_sme2(id) && isar_feature_aa64_faminmax(id);\n }\n \n+static inline bool isar_feature_aa64_sme2_f8cvt(const ARMISARegisters *id)\n+{\n+ return isar_feature_aa64_sme2(id) && isar_feature_aa64_f8cvt(id);\n+}\n+\n static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)\n {\n return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_i8mm(id);\ndiff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c\nindex a67501226f..e2d17de165 100644\n--- a/target/arm/tcg/translate-sme.c\n+++ b/target/arm/tcg/translate-sme.c\n@@ -707,9 +707,12 @@ static bool do_z2z_n1_fpst(DisasContext *s, arg_z2z_en *a,\n {\n int esz = a->esz, n, dn, vsz, mofs;\n bool overlap = false;\n- gen_helper_gvec_3_ptr *fn;\n+ gen_helper_gvec_3_ptr *fn = fns[esz];\n TCGv_ptr fpst;\n \n+ if (fn == NULL) {\n+ return false;\n+ }\n /* These insns use MO_8 to encode BFloat16. */\n if (esz == MO_8 && !dc_isar_feature(aa64_sme_b16b16, s)) {\n return false;\n@@ -719,7 +722,6 @@ static bool do_z2z_n1_fpst(DisasContext *s, arg_z2z_en *a,\n }\n \n fpst = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64);\n- fn = fns[esz];\n n = a->n;\n dn = a->zdn;\n mofs = vec_full_reg_offset(s, a->zm);\n@@ -831,6 +833,15 @@ static gen_helper_gvec_3_ptr * const f_vector_famin[4] = {\n };\n TRANS_FEAT(FAMIN_nn, aa64_sme2_faminmax, do_z2z_nn_fpst, a, f_vector_famin)\n \n+static gen_helper_gvec_3_ptr * const f_vector_fscale[4] = {\n+ NULL,\n+ gen_helper_gvec_fscale_h,\n+ gen_helper_gvec_fscale_s,\n+ gen_helper_gvec_fscale_d,\n+};\n+TRANS_FEAT(FSCALE_n1, aa64_sme2_f8cvt, do_z2z_n1_fpst, a, f_vector_fscale)\n+TRANS_FEAT(FSCALE_nn, aa64_sme2_f8cvt, do_z2z_nn_fpst, a, f_vector_fscale)\n+\n /* Add/Sub vector Z[m] to each Z[n*N] with result in ZA[d*N]. */\n static bool do_azz_n1(DisasContext *s, arg_azz_n *a, int esz,\n GVecGen3FnVar *fn)\ndiff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode\nindex 9dec7318a4..ee874be1a6 100644\n--- a/target/arm/tcg/sme.decode\n+++ b/target/arm/tcg/sme.decode\n@@ -250,6 +250,9 @@ ADD_n1 1100000 1 .. 10 .... 1010.0 11000 .... 0 @z2z_4x1\n SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 .... 0 @z2z_2x1\n SQDMULH_n1 1100000 1 .. 10 .... 1010.1 00000 .... 0 @z2z_4x1\n \n+FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_2x1\n+FSCALE_n1 1100000 1 .. 10 .... 1010.0 01100 .... 0 @z2z_4x1\n+\n ### SME2 Multi-vector Multiple Vectors SVE Destructive\n \n %zm_ax2 17:4 !function=times_2\n@@ -291,6 +294,9 @@ FAMAX_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 0 @z2z_4x4\n FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_2x2\n FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_4x4\n \n+FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_2x2\n+FSCALE_nn 1100000 1 .. 1 ..... 1011.0 01100 .... 0 @z2z_4x4\n+\n ### SME2 Multi-vector Multiple and Single Array Vectors\n \n &azz_n n off rv zn zm\n", "prefixes": [ "v3", "18/47" ] }