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GET /api/patches/2230736/?format=api
{ "id": 2230736, "url": "http://patchwork.ozlabs.org/api/patches/2230736/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-20-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430002046.59739-20-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-04-30T00:20:18", "name": "[v3,19/47] target/arm: Split vector-type.h from cpu.h", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "26c1d7f17e59c4323b0f89079f1be8f8b66324c0", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-20-richard.henderson@linaro.org/mbox/", "series": [ { "id": 502175, "url": "http://patchwork.ozlabs.org/api/series/502175/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175", "date": "2026-04-30T00:20:06", "name": "target/arm: Implement FEAT_FP8", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502175/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230736/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230736/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=S4YdfPe2;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5Zff756tz1yHZ\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 10:24:10 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wIF9z-0006ol-0n; Wed, 29 Apr 2026 20:21:43 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIF9t-0006ic-Et\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:37 -0400", "from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIF9r-0006LO-HM\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:37 -0400", "by mail-pg1-x533.google.com with SMTP id\n 41be03b00d2f7-c736261ee8dso93022a12.1\n for <qemu-devel@nongnu.org>; Wed, 29 Apr 2026 17:21:35 -0700 (PDT)", "from stoup.. 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::533;\n envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "We want to be able to reference ARMVectorType etc from\ncommon code, so move it out of cpu.h.\n\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu.h | 38 +---------------------------------\n target/arm/vector-type.h | 44 ++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 45 insertions(+), 37 deletions(-)\n create mode 100644 target/arm/vector-type.h", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 5d051e1d2d..f986602722 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -35,6 +35,7 @@\n #include \"target/arm/gtimer.h\"\n #include \"target/arm/cpu-sysregs.h\"\n #include \"target/arm/mmuidx.h\"\n+#include \"target/arm/vector-type.h\"\n \n #define EXCP_UDEF 1 /* undefined instruction */\n #define EXCP_SWI 2 /* software interrupt */\n@@ -140,43 +141,6 @@ typedef struct ARMGenericTimer {\n uint64_t ctl; /* Timer Control register */\n } ARMGenericTimer;\n \n-/* Define a maximum sized vector register.\n- * For 32-bit, this is a 128-bit NEON/AdvSIMD register.\n- * For 64-bit, this is a 2048-bit SVE register.\n- *\n- * Note that the mapping between S, D, and Q views of the register bank\n- * differs between AArch64 and AArch32.\n- * In AArch32:\n- * Qn = regs[n].d[1]:regs[n].d[0]\n- * Dn = regs[n / 2].d[n & 1]\n- * Sn = regs[n / 4].d[n % 4 / 2],\n- * bits 31..0 for even n, and bits 63..32 for odd n\n- * (and regs[16] to regs[31] are inaccessible)\n- * In AArch64:\n- * Zn = regs[n].d[*]\n- * Qn = regs[n].d[1]:regs[n].d[0]\n- * Dn = regs[n].d[0]\n- * Sn = regs[n].d[0] bits 31..0\n- * Hn = regs[n].d[0] bits 15..0\n- *\n- * This corresponds to the architecturally defined mapping between\n- * the two execution states, and means we do not need to explicitly\n- * map these registers when changing states.\n- *\n- * Align the data for use with TCG host vector operations.\n- */\n-\n-#define ARM_MAX_VQ 16\n-\n-typedef struct ARMVectorReg {\n- uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);\n-} ARMVectorReg;\n-\n-/* In AArch32 mode, predicate registers do not exist at all. */\n-typedef struct ARMPredicateReg {\n- uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);\n-} ARMPredicateReg;\n-\n /* In AArch32 mode, PAC keys do not exist at all. */\n typedef struct ARMPACKey {\n uint64_t lo, hi;\ndiff --git a/target/arm/vector-type.h b/target/arm/vector-type.h\nnew file mode 100644\nindex 0000000000..d94c0d986e\n--- /dev/null\n+++ b/target/arm/vector-type.h\n@@ -0,0 +1,44 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+\n+#ifndef TARGET_ARM_VECTOR_TYPE_H\n+#define TARGET_ARM_VECTOR_TYPE_H\n+\n+/*\n+ * Define a maximum sized vector register.\n+ * For 32-bit, this is a 128-bit NEON/AdvSIMD register.\n+ * For 64-bit, this is a 2048-bit SVE register.\n+ *\n+ * Note that the mapping between S, D, and Q views of the register bank\n+ * differs between AArch64 and AArch32.\n+ * In AArch32:\n+ * Qn = regs[n].d[1]:regs[n].d[0]\n+ * Dn = regs[n / 2].d[n & 1]\n+ * Sn = regs[n / 4].d[n % 4 / 2],\n+ * bits 31..0 for even n, and bits 63..32 for odd n\n+ * (and regs[16] to regs[31] are inaccessible)\n+ * In AArch64:\n+ * Zn = regs[n].d[*]\n+ * Qn = regs[n].d[1]:regs[n].d[0]\n+ * Dn = regs[n].d[0]\n+ * Sn = regs[n].d[0] bits 31..0\n+ * Hn = regs[n].d[0] bits 15..0\n+ *\n+ * This corresponds to the architecturally defined mapping between\n+ * the two execution states, and means we do not need to explicitly\n+ * map these registers when changing states.\n+ *\n+ * Align the data for use with TCG host vector operations.\n+ */\n+\n+#define ARM_MAX_VQ 16\n+\n+typedef struct ARMVectorReg {\n+ uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);\n+} ARMVectorReg;\n+\n+/* In AArch32 mode, predicate registers do not exist at all. */\n+typedef struct ARMPredicateReg {\n+ uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);\n+} ARMPredicateReg;\n+\n+#endif\n", "prefixes": [ "v3", "19/47" ] }