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GET /api/patches/2230733/?format=api
{ "id": 2230733, "url": "http://patchwork.ozlabs.org/api/patches/2230733/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-33-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430002046.59739-33-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-04-30T00:20:31", "name": "[v3,32/47] target/arm: Implement FCVTNB, FCVTNT for SVE", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3bda5c8ad9acff9e4cfe1eeaf511c6c675e6d4e0", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-33-richard.henderson@linaro.org/mbox/", "series": [ { "id": 502175, "url": "http://patchwork.ozlabs.org/api/series/502175/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175", "date": "2026-04-30T00:20:06", "name": "target/arm: Implement FEAT_FP8", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502175/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230733/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230733/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Z/YhzmDP;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5Zdy0m7zz1yHZ\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 10:23:34 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wIFAS-0007hF-EA; Wed, 29 Apr 2026 20:22:12 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIFAL-0007NB-GY\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:22:05 -0400", "from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIFAJ-0006YN-Gd\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:22:05 -0400", "by mail-pf1-x42d.google.com with SMTP id\n d2e1a72fcca58-82f431c0ab6so189668b3a.0\n for <qemu-devel@nongnu.org>; Wed, 29 Apr 2026 17:22:03 -0700 (PDT)", "from stoup.. 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helo=mail-pf1-x42d.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/helper-fp8-defs.h | 2 +\n target/arm/tcg/fp8_helper.c | 87 +++++++++++++++++++++++++++++++-\n target/arm/tcg/translate-sve.c | 4 ++\n target/arm/tcg/sve.decode | 2 +\n 4 files changed, 94 insertions(+), 1 deletion(-)", "diff": "diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex e67fb191c2..5863a6dbb8 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -19,3 +19,5 @@ DEF_HELPER_FLAGS_5(gvec_fcvt_bh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sve2_fcvtn_bh, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \n DEF_HELPER_FLAGS_5(advsimd_fcvt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_4(sve2_fcvtnb_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_4(sve2_fcvtnt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex 9c89964721..f92ffe68e3 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -626,7 +626,6 @@ void HELPER(sve2_fcvtn_bh)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n fp8_finish(env, &ctx);\n }\n \n-\n void HELPER(advsimd_fcvt_bs)(void *vd, void *vn, void *vm,\n CPUARMState *env, uint32_t desc)\n {\n@@ -668,3 +667,89 @@ void HELPER(advsimd_fcvt_bs)(void *vd, void *vn, void *vm,\n fp8_finish(env, &ctx);\n clear_tail(vd, ctx.high ? 16 : 8, simd_maxsz(desc));\n }\n+\n+void HELPER(sve2_fcvtnb_bs)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_dst_start(env, desc);\n+ uint32_t *n0 = vn;\n+ uint32_t *n1 = vn + sizeof(ARMVectorReg);\n+ uint16_t *d = vd;\n+ bool osc = FIELD_EX64(env->vfp.fpmr, FPMR, OSC);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 4;\n+\n+ switch (ctx.f8fmt) {\n+ case OFP8_E5M2:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float32 e0 = n0[H2(i)];\n+ float32 e1 = n1[H2(i)];\n+ d[H2(2 * i + 0)] =\n+ fcvt_f32_to_fp8e5m2(e0, ctx.scale, osc, &ctx.stat);\n+ d[H2(2 * i + 1)] =\n+ fcvt_f32_to_fp8e5m2(e1, ctx.scale, osc, &ctx.stat);\n+ }\n+ break;\n+ case OFP8_E4M3:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float32 e0 = n0[H2(i)];\n+ float32 e1 = n1[H2(i)];\n+ d[H2(2 * i + 0)] =\n+ fcvt_f32_to_fp8e4m3(e0, ctx.scale, osc, &ctx.stat);\n+ d[H2(2 * i + 1)] =\n+ fcvt_f32_to_fp8e4m3(e1, ctx.scale, osc, &ctx.stat);\n+ }\n+ break;\n+ default:\n+ /* -1 in each even field, 0 in each odd field. */\n+ for (size_t i = 0; i < oprsz; i += 8) {\n+ *(uint64_t *)(vd + i) = 0x00ff00ff00ff00ffull;\n+ }\n+ float_raise(float_flag_invalid, &ctx.stat);\n+ break;\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\n+\n+void HELPER(sve2_fcvtnt_bs)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_dst_start(env, desc);\n+ uint32_t *n0 = vn;\n+ uint32_t *n1 = vn + sizeof(ARMVectorReg);\n+ uint8_t *d = vd;\n+ bool osc = FIELD_EX64(env->vfp.fpmr, FPMR, OSC);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 4;\n+\n+ switch (ctx.f8fmt) {\n+ case OFP8_E5M2:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float32 e0 = n0[H2(i)];\n+ float32 e1 = n1[H2(i)];\n+ d[H1(4 * i + 1)] =\n+ fcvt_f32_to_fp8e5m2(e0, ctx.scale, osc, &ctx.stat);\n+ d[H1(4 * i + 3)] =\n+ fcvt_f32_to_fp8e5m2(e1, ctx.scale, osc, &ctx.stat);\n+ }\n+ break;\n+ case OFP8_E4M3:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float32 e0 = n0[H2(i)];\n+ float32 e1 = n1[H2(i)];\n+ d[H1(4 * i + 1)] =\n+ fcvt_f32_to_fp8e4m3(e0, ctx.scale, osc, &ctx.stat);\n+ d[H1(4 * i + 3)] =\n+ fcvt_f32_to_fp8e4m3(e1, ctx.scale, osc, &ctx.stat);\n+ }\n+ break;\n+ default:\n+ /* -1 in each odd field, even fields unchanged. */\n+ for (size_t i = 0; i < oprsz; i += 8) {\n+ *(uint64_t *)(vd + i) |= 0xff00ff00ff00ff00ull;\n+ }\n+ float_raise(float_flag_invalid, &ctx.stat);\n+ break;\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\ndiff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c\nindex c7fcf27183..13f7ab01af 100644\n--- a/target/arm/tcg/translate-sve.c\n+++ b/target/arm/tcg/translate-sve.c\n@@ -4103,6 +4103,10 @@ TRANS_FEAT(FCVTN, aa64_sme2_or_sve2_f8cvt, do_f8cvt,\n a, gen_helper_sve2_fcvtn_bh, false, false)\n TRANS_FEAT(BFCVTN, aa64_sme2_or_sve2_f8cvt, do_f8cvt,\n a, gen_helper_sve2_bfcvtn_bh, false, false)\n+TRANS_FEAT(FCVTNB, aa64_sme2_or_sve2_f8cvt, do_f8cvt,\n+ a, gen_helper_sve2_fcvtnb_bs, false, false)\n+TRANS_FEAT(FCVTNT, aa64_sme2_or_sve2_f8cvt, do_f8cvt,\n+ a, gen_helper_sve2_fcvtnt_bs, false, false)\n \n /*\n *** SVE Floating Point Compare with Zero Group\ndiff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode\nindex 806953bc35..7fce189b36 100644\n--- a/target/arm/tcg/sve.decode\n+++ b/target/arm/tcg/sve.decode\n@@ -1103,6 +1103,8 @@ BF2CVTLT 01100101 00 001 001 001111 ..... ..... @rd_rn_e0\n \n FCVTN 01100101 00 001 010 001100 ....0 ..... @rd_rnx2 esz=1\n BFCVTN 01100101 00 001 010 001110 ....0 ..... @rd_rnx2 esz=1\n+FCVTNB 01100101 00 001 010 001101 ....0 ..... @rd_rnx2 esz=1\n+FCVTNT 01100101 00 001 010 001111 ....0 ..... @rd_rnx2 esz=1\n \n ### SVE FP Compare with Zero Group\n \n", "prefixes": [ "v3", "32/47" ] }