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GET /api/patches/2230687/?format=api
{ "id": 2230687, "url": "http://patchwork.ozlabs.org/api/patches/2230687/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430000524.56046-25-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430000524.56046-25-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-04-30T00:05:07", "name": "[v2,24/40] fpu: Split scalbn from partsN(muladd_scalbn)", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0a1fdd9b5f95d093870b3deb413a7dd693115fb6", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430000524.56046-25-richard.henderson@linaro.org/mbox/", "series": [ { "id": 502170, "url": "http://patchwork.ozlabs.org/api/series/502170/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502170", "date": "2026-04-30T00:04:48", "name": "fpu: Export some internals for targets", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502170/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230687/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230687/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=CZfFJgl1;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5ZKH5gQKz1yHZ\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 10:09:07 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wIEvr-0008IV-5S; Wed, 29 Apr 2026 20:07:09 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIEvC-0007oh-V6\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:06:29 -0400", "from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIEvA-0001sS-L9\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:06:26 -0400", "by mail-pf1-x435.google.com with SMTP id\n d2e1a72fcca58-8296d553142so203866b3a.3\n for <qemu-devel@nongnu.org>; Wed, 29 Apr 2026 17:06:24 -0700 (PDT)", "from stoup.. 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"<20260430000524.56046-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::435;\n envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Handle the scaling separately with parts64_scalbn.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n fpu/softfloat.c | 37 ++++++++++++++++++++++++-------------\n fpu/softfloat-parts.c.inc | 20 ++++++++++----------\n 2 files changed, 34 insertions(+), 23 deletions(-)", "diff": "diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex 168181858f..2e5c1d4a32 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -1907,11 +1907,14 @@ float16_muladd_scalbn(float16 a, float16 b, float16 c,\n FloatParts64 pa = float16_unpack_canonical(a, status);\n FloatParts64 pb = float16_unpack_canonical(b, status);\n FloatParts64 pc = float16_unpack_canonical(c, status);\n- FloatParts64 *pr =\n- parts64_muladd_scalbn(&pa, &pb, &pc, scale, flags, status);\n+ FloatParts64 *pr = parts64_muladd(&pa, &pb, &pc, flags, status);\n \n- /* Round before applying negate result. */\n+ /* Before rounding, scale. */\n+ if (scale) {\n+ parts64_scalbn(pr, scale, status);\n+ }\n parts64_uncanon(pr, status, &float16_params, false);\n+ /* After rounding, apply negate result, especially for -0.0. */\n if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n pr->sign ^= 1;\n }\n@@ -1931,10 +1934,14 @@ float32_muladd_scalbn(float32 a, float32 b, float32 c,\n FloatParts64 pa = float32_unpack_canonical(a, status);\n FloatParts64 pb = float32_unpack_canonical(b, status);\n FloatParts64 pc = float32_unpack_canonical(c, status);\n- FloatParts64 *pr = parts64_muladd_scalbn(&pa, &pb, &pc, scale, flags, status);\n+ FloatParts64 *pr = parts64_muladd(&pa, &pb, &pc, flags, status);\n \n- /* Round before applying negate result. */\n+ /* Before rounding, scale. */\n+ if (scale) {\n+ parts64_scalbn(pr, scale, status);\n+ }\n parts64_uncanon(pr, status, &float32_params, false);\n+ /* After rounding, apply negate result, especially for -0.0. */\n if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n pr->sign ^= 1;\n }\n@@ -1948,10 +1955,14 @@ float64_muladd_scalbn(float64 a, float64 b, float64 c,\n FloatParts64 pa = float64_unpack_canonical(a, status);\n FloatParts64 pb = float64_unpack_canonical(b, status);\n FloatParts64 pc = float64_unpack_canonical(c, status);\n- FloatParts64 *pr = parts64_muladd_scalbn(&pa, &pb, &pc, scale, flags, status);\n+ FloatParts64 *pr = parts64_muladd(&pa, &pb, &pc, flags, status);\n \n- /* Round before applying negate result. */\n+ /* Before rounding, scale. */\n+ if (scale) {\n+ parts64_scalbn(pr, scale, status);\n+ }\n parts64_uncanon(pr, status, &float64_params, false);\n+ /* After rounding, apply negate result, especially for -0.0. */\n if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n pr->sign ^= 1;\n }\n@@ -2105,7 +2116,7 @@ float64 float64r32_muladd(float64 a, float64 b, float64 c,\n FloatParts64 pa = float64_unpack_canonical(a, status);\n FloatParts64 pb = float64_unpack_canonical(b, status);\n FloatParts64 pc = float64_unpack_canonical(c, status);\n- FloatParts64 *pr = parts64_muladd_scalbn(&pa, &pb, &pc, 0, flags, status);\n+ FloatParts64 *pr = parts64_muladd(&pa, &pb, &pc, flags, status);\n \n /* Round before applying negate result. */\n parts64_uncanon(pr, status, &float32_params, false);\n@@ -2121,7 +2132,7 @@ bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c,\n FloatParts64 pa = bfloat16_unpack_canonical(a, status);\n FloatParts64 pb = bfloat16_unpack_canonical(b, status);\n FloatParts64 pc = bfloat16_unpack_canonical(c, status);\n- FloatParts64 *pr = parts64_muladd_scalbn(&pa, &pb, &pc, 0, flags, status);\n+ FloatParts64 *pr = parts64_muladd(&pa, &pb, &pc, flags, status);\n \n /* Round before applying negate result. */\n parts64_uncanon(pr, status, &bfloat16_params, false);\n@@ -2137,7 +2148,7 @@ float128 QEMU_FLATTEN float128_muladd(float128 a, float128 b, float128 c,\n FloatParts128 pa = float128_unpack_canonical(a, status);\n FloatParts128 pb = float128_unpack_canonical(b, status);\n FloatParts128 pc = float128_unpack_canonical(c, status);\n- FloatParts128 *pr = parts128_muladd_scalbn(&pa, &pb, &pc, 0, flags, status);\n+ FloatParts128 *pr = parts128_muladd(&pa, &pb, &pc, flags, status);\n \n /* Round before applying negate result. */\n parts128_uncanon(pr, status, &float128_params, false);\n@@ -5116,7 +5127,7 @@ float32 float32_exp2(float32 a, float_status *status)\n rp = float64_unpack_canonical(float64_one, status);\n for (int i = 0; i < 15; i++) {\n tp = float64_unpack_canonical(float32_exp2_coefficients[i], status);\n- rp = *parts64_muladd_scalbn(&tp, &xnp, &rp, 0, 0, status);\n+ rp = *parts64_muladd(&tp, &xnp, &rp, 0, status);\n xnp = *parts64_mul(&xnp, &xp, status);\n }\n \n@@ -5195,8 +5206,8 @@ static void parts_s390_divide_to_integer(FloatParts64 *a, FloatParts64 *b,\n \n /* Compute precise remainder */\n r_precise_buf = *b;\n- r_precise = parts64_muladd_scalbn(&r_precise_buf, n, a, 0,\n- float_muladd_negate_product, status);\n+ r_precise = parts64_muladd(&r_precise_buf, n, a,\n+ float_muladd_negate_product, status);\n \n /* Round remainder to the target format */\n *r = *r_precise;\ndiff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex 028c2daa27..b8baaf1e76 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -669,17 +669,19 @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b,\n * `b' then adding 'c', with no intermediate rounding step after the\n * multiplication. The operation is performed according to the\n * IEC/IEEE Standard for Binary Floating-Point Arithmetic 754-2008.\n- * The flags argument allows the caller to select negation of the\n- * addend, the intermediate product, or the final result. (The\n- * difference between this and having the caller do a separate\n- * negation is that negating externally will flip the sign bit on NaNs.)\n+ * The flags argument allows the caller to select negation of the addend\n+ * or the intermediate product. (The difference between this and having\n+ * the caller do a separate negation is that negating externally will\n+ * flip the sign bit on NaNs.) Note that float_muladd_negate_result\n+ * is not applied here, and should be handled separately after rounding\n+ * chooses the final sign of 0.0.\n *\n * Requires A and C extracted into a double-sized structure to provide the\n * extra space for the widening multiply.\n */\n-static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b,\n- FloatPartsN *c, int scale,\n- int flags, float_status *s)\n+static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,\n+ FloatPartsN *c,\n+ int flags, float_status *s)\n {\n int ab_mask, abc_mask;\n FloatPartsW p_widen, c_widen;\n@@ -725,7 +727,7 @@ static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b,\n g_assert(ab_mask & float_cmask_zero);\n if (is_anynorm(c->cls)) {\n *a = *c;\n- goto return_normal;\n+ goto finish_sign;\n }\n if (c->cls == float_class_zero) {\n if (flags & float_muladd_suppress_add_product_zero) {\n@@ -770,8 +772,6 @@ static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b,\n a->sign = p_widen.sign;\n a->exp = p_widen.exp;\n \n- return_normal:\n- a->exp += scale;\n finish_sign:\n /*\n * All result types except for \"return the default NaN\n", "prefixes": [ "v2", "24/40" ] }