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GET /api/patches/2230592/?format=api
{ "id": 2230592, "url": "http://patchwork.ozlabs.org/api/patches/2230592/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429220155.24546-3-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260429220155.24546-3-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-04-29T22:01:54", "name": "[PULL,2/3] tcg/aarch64/tcg-target.c.inc: Manual replace of I3310, I3313", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a769edefad5bf55ce804f0b16e1532143f0b44f5", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429220155.24546-3-richard.henderson@linaro.org/mbox/", "series": [ { "id": 502159, "url": "http://patchwork.ozlabs.org/api/series/502159/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502159", "date": "2026-04-29T22:01:52", "name": "[PULL,1/3] tcg/aarch64/tcg-target.c.inc: Replacement of I3XXX names", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502159/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230592/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230592/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=rFAhLFVp;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5WX203gjz1yGq\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 08:03:14 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wICyy-0002S2-6U; Wed, 29 Apr 2026 18:02:12 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wICyw-0002Rs-VD\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 18:02:10 -0400", "from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wICyu-0006YZ-Tl\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 18:02:10 -0400", "by mail-pl1-x62f.google.com with SMTP id\n d9443c01a7336-2b461310af5so1178425ad.1\n for <qemu-devel@nongnu.org>; Wed, 29 Apr 2026 15:02:08 -0700 (PDT)", "from stoup.. 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helo=mail-pl1-x62f.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Jim MacArthur <jim.macarthur@linaro.org>\n\nThese are not formats in themselves, but extra constants to OR in with\nthe existing ldst_imm format.\n\nSigned-off-by: Jim MacArthur <jim.macarthur@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-ID: <20260402-aarch64-tcg-instruction-format-rename2-v1-2-0998a08a515c@linaro.org>\n---\n tcg/aarch64/tcg-target.c.inc | 64 ++++++++++++++++++++----------------\n 1 file changed, 35 insertions(+), 29 deletions(-)", "diff": "diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc\nindex 23d96a7960..cc9c2a5158 100644\n--- a/tcg/aarch64/tcg-target.c.inc\n+++ b/tcg/aarch64/tcg-target.c.inc\n@@ -458,8 +458,9 @@ typedef enum {\n Ildst_imm_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30,\n Ildst_imm_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30,\n \n- Ildst_imm_TO_I3310 = 0x00200800,\n- Ildst_imm_TO_I3313 = 0x01000000,\n+ /* Additions to the ldst_imm format */\n+ ldst_imm_to_reg = 0x00200800,\n+ ldst_imm_to_uimm = 0x01000000,\n \n /* Load/store register pair instructions. */\n Ildstpair_LDP = 0x28400000,\n@@ -880,13 +881,13 @@ static void tcg_out_insn_qrr_e(TCGContext *s, AArch64Insn insn, bool q,\n | (rn & 0x1f) << 5 | (rd & 0x1f));\n }\n \n-static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn,\n- TCGReg rd, TCGReg base, TCGType ext,\n- TCGReg regoff)\n+static void tcg_out_insn_ldst_reg(TCGContext *s, AArch64Insn insn,\n+ TCGReg rd, TCGReg base, TCGType ext,\n+ TCGReg regoff)\n {\n /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */\n- tcg_out32(s, insn | Ildst_imm_TO_I3310 | regoff << 16 |\n- 0x4000 | ext << 13 | base << 5 | (rd & 0x1f));\n+ tcg_out32(s, insn | ldst_imm_to_reg | regoff << 16 | 0x4000 | ext << 13 |\n+ base << 5 | (rd & 0x1f));\n }\n \n static void tcg_out_insn_ldst_imm(TCGContext *s, AArch64Insn insn,\n@@ -895,11 +896,11 @@ static void tcg_out_insn_ldst_imm(TCGContext *s, AArch64Insn insn,\n tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f));\n }\n \n-static void tcg_out_insn_3313(TCGContext *s, AArch64Insn insn,\n- TCGReg rd, TCGReg rn, uintptr_t scaled_uimm)\n+static void tcg_out_insn_ldst_uimm(TCGContext *s, AArch64Insn insn,\n+ TCGReg rd, TCGReg rn, uintptr_t scaled_uimm)\n {\n /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */\n- tcg_out32(s, insn | Ildst_imm_TO_I3313 | scaled_uimm << 10\n+ tcg_out32(s, insn | ldst_imm_to_uimm | scaled_uimm << 10\n | rn << 5 | (rd & 0x1f));\n }\n \n@@ -1203,9 +1204,6 @@ static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,\n g_assert_not_reached();\n }\n \n-/* Define something more legible for general use. */\n-#define tcg_out_ldst_r tcg_out_insn_3310\n-\n static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,\n TCGReg rn, intptr_t offset, int lgsize)\n {\n@@ -1214,7 +1212,7 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,\n if (offset >= 0 && !(offset & ((1 << lgsize) - 1))) {\n uintptr_t scaled_uimm = offset >> lgsize;\n if (scaled_uimm <= 0xfff) {\n- tcg_out_insn_3313(s, insn, rd, rn, scaled_uimm);\n+ tcg_out_insn_ldst_uimm(s, insn, rd, rn, scaled_uimm);\n return;\n }\n }\n@@ -1227,7 +1225,7 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,\n \n /* Worst-case scenario, move offset to temp register, use reg offset. */\n tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, offset);\n- tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP0);\n+ tcg_out_insn_ldst_reg(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP0);\n }\n \n static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)\n@@ -1764,28 +1762,32 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,\n {\n switch (memop & MO_SSIZE) {\n case MO_UB:\n- tcg_out_ldst_r(s, Ildst_imm_LDRB, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_insn_ldst_reg(s, Ildst_imm_LDRB, data_r, h.base,\n+ h.index_ext, h.index);\n break;\n case MO_SB:\n- tcg_out_ldst_r(s, ext ? Ildst_imm_LDRSBX : Ildst_imm_LDRSBW,\n- data_r, h.base, h.index_ext, h.index);\n+ tcg_out_insn_ldst_reg(s, ext ? Ildst_imm_LDRSBX : Ildst_imm_LDRSBW,\n+ data_r, h.base, h.index_ext, h.index);\n break;\n case MO_UW:\n- tcg_out_ldst_r(s, Ildst_imm_LDRH, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_insn_ldst_reg(s, Ildst_imm_LDRH, data_r, h.base, h.index_ext,\n+ h.index);\n break;\n case MO_SW:\n- tcg_out_ldst_r(s, (ext ? Ildst_imm_LDRSHX : Ildst_imm_LDRSHW),\n- data_r, h.base, h.index_ext, h.index);\n+ tcg_out_insn_ldst_reg(s, ext ? Ildst_imm_LDRSHX : Ildst_imm_LDRSHW,\n+ data_r, h.base, h.index_ext, h.index);\n break;\n case MO_UL:\n- tcg_out_ldst_r(s, Ildst_imm_LDRW, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_insn_ldst_reg(s, Ildst_imm_LDRW, data_r, h.base, h.index_ext,\n+ h.index);\n break;\n case MO_SL:\n- tcg_out_ldst_r(s, Ildst_imm_LDRSWX, data_r, h.base, h.index_ext,\n- h.index);\n+ tcg_out_insn_ldst_reg(s, Ildst_imm_LDRSWX, data_r, h.base, h.index_ext,\n+ h.index);\n break;\n case MO_UQ:\n- tcg_out_ldst_r(s, Ildst_imm_LDRX, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_insn_ldst_reg(s, Ildst_imm_LDRX, data_r, h.base, h.index_ext,\n+ h.index);\n break;\n default:\n g_assert_not_reached();\n@@ -1797,16 +1799,20 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,\n {\n switch (memop & MO_SIZE) {\n case MO_8:\n- tcg_out_ldst_r(s, Ildst_imm_STRB, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_insn_ldst_reg(s, Ildst_imm_STRB, data_r, h.base,\n+ h.index_ext, h.index);\n break;\n case MO_16:\n- tcg_out_ldst_r(s, Ildst_imm_STRH, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_insn_ldst_reg(s, Ildst_imm_STRH, data_r, h.base,\n+ h.index_ext, h.index);\n break;\n case MO_32:\n- tcg_out_ldst_r(s, Ildst_imm_STRW, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_insn_ldst_reg(s, Ildst_imm_STRW, data_r, h.base,\n+ h.index_ext, h.index);\n break;\n case MO_64:\n- tcg_out_ldst_r(s, Ildst_imm_STRX, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_insn_ldst_reg(s, Ildst_imm_STRX, data_r, h.base,\n+ h.index_ext, h.index);\n break;\n default:\n g_assert_not_reached();\n", "prefixes": [ "PULL", "2/3" ] }